JPS6217767B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for displaying output processed by a microcomputer on a scanning type display element such as a cathode ray tube, and provides a device that can be realized with a simple configuration.

First, Figure 1 shows the content of the output processed by a central processing unit (CPU) using a microcomputer.
This shows a conventional display device such as a CRT. here,
1 is a CPU, 2 is a memory such as a character generator for display signal generation, 3 is an input/output device, and 4 is a
Shows a display device including a CRT. A, B, and C represent data paths, and a and b represent control signal paths.

As shown in the figure, the CPU 1 releases the address bus and the data bus B by itself or by a request signal from the input/output device 3, and the control thereof is left to the input/output device 3. The input/output device 3 sends an address designation signal to the address bus B, and in response, obtains data from the memory 2 from the data bus B, and synchronizes it with an external synchronization signal or an internally generated synchronization signal. Convert to a temporally serial signal using a gated oscillator or the like. Then, it is supplied to the video display device 4 for display.

This method does not pass the CPU through the display data path, so the data readout time is
This is a commonly used method because it does not have the disadvantage of being limited in time by the internal clock of the CPU, but it does not allow the CPU to process data for display. In other words, because CPU1 has a clock frequency limit, it is not possible to pass display data to CPU1, and in the device shown in Figure 1, the address and data bus B is
It is necessary to separate the address data bus B from the input/output device 3 and control the address data bus B by using the input/output device 3. For this reason, the input/output device 3 is complicated and cannot be used in a normal 4-bit or other 1-chip microcomputer.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide a video display device capable of outputting display data from a CPU using a microcomputer and displaying the video.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

First, a block diagram of its basic configuration is shown in FIG. Here, 5 is determined by the microcomputer.
A CPU, 6 a memory for display data, 7 an input/output device, and 8 a display device. A, B, and C are data paths, a, b are control signal paths, and D and E are vertical and horizontal synchronization signals.

In such a device, when the display start switch is turned on, the CPU 5 starts operating according to the program, controls the input/output device 5 through the control bus b, and receives the vertical synchronization signal from D. Read through data bus B to determine the presence or absence of a vertical synchronization signal. Check the vertical sync signal and the CPU
5 requests display data from memory 6 through control bus a, and memory 6 sends display data to CPU 5 through data bus A. The CPU 5 sends the received display data to the input/output device 7 through the data bus B. The CPU 5 enters a standby routine as soon as the data is sent, creating wasted time. The input/output device 7 latches the display data received from the CPU 5, generates an internal clock at the same time as the horizontal synchronization signal is input from E, and converts the received display data into a temporally serial display video signal. and sends it to the display device 8 through the data bus C. The display device 8 uses this to display images on the CRT. On the other hand, I was stuck in the standby routine.
When the standby routine is completed, the CPU 5 determines whether output of display data for one frame of pixels has been completed, and if the output has not been completed, the CPU 5 increments the address of the memory 6 and requests the next display data. This data is processed in the same manner as described above and an image is displayed. Further, when the display of pixels for one frame is completed, the processing program returns to the beginning and starts again in order from the step of determining the presence or absence of a vertical synchronization signal.

FIG. 3 shows the display state.

In the present invention, when data for display is output through the CPU in this way,
The input/output device 7 is configured so that images can be effectively displayed on the CRT even if the CPU clock frequency is low. In other words, this input/output device 7
In this case, video is displayed using a horizontal synchronization signal and a vertical synchronization signal, and the horizontal period and vertical period are temporally divided into many periods, and in each divided period, a high-level signal is output depending on the display data from the CPU. , the video signal is constructed by providing a low level signal. FIG. 4 shows a detailed circuit diagram of one embodiment. The horizontal synchronizing signal supplied from the line E may be supplied externally or generated internally, but the oscillator 9 whose initial phase is adjusted by this horizontal synchronizing signal
is provided, and its frequency is selected to be approximately n times the frequency of the horizontal synchronizing signal, where n is the number of pixel divisions in the horizontal direction. The oscillation output is generated by a switching pulse generator 10 such as a ring counter or a shift register, which has n output terminals, and generates an output in order from the first to the nth output terminal every time one bit of the oscillation output is generated. It will be done. The output value can be changed over time using programs etc.
The number of output terminals of the output port 11 of the CPU 5 is also provided, and the bit-by-bit logical product of the output terminal of the CPU 5 and the output terminal of the switching pulse generator 10 is
It is created by AND gate group 12. Then, the outputs are combined by an OR gate 13, and an output display video signal is obtained by a data bus C. Therefore, the output video signal is a signal obtained by temporally converting the parallel output data of the CPU 5 into serial data at the oscillation frequency of the oscillator 9. This video signal is vertical
It is supplied to a video display device 8 that displays video using a horizontal synchronization signal, and if a television receiver is used, it is added to a brightness signal, a cathode of a CRT, etc.

In this way, according to this device, the interval between the data output for display from the CPU 5 is the same as that for display.
For example, one horizontal scanning period of CRT is 63.5μsec ( _H
= 15.75KHz) or less, there is no problem; this is
With a CPU 5 or the like using a microcomputer using MOS gates, the time is sufficient and there is no problem.

As described above, according to the present invention, images can be easily displayed on a cathode ray tube even if a microcomputer with a low clock frequency is used.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional video display device.
FIG. 2 is a block diagram of a video display device according to an embodiment of the present invention, FIG. 3 is a front view of a display mode of the device, and FIG. 4 is a circuit diagram of a main part of the device. 5...CPU, 6...Memory, 7...I/O device, 8...Display device.

Claims (1)

[Claims] 1 When the number of horizontal pixel divisions is n,
An oscillator that outputs at a frequency approximately n times that of the horizontal synchronizing signal, a switching pulse generator that sequentially generates outputs from the 1st to nth output terminals every time one bit of the oscillator output is generated, and an image display device. a central processing unit having n output ports that output data signals in parallel and whose output value can be changed over time by a program, each output of the output ports, and the switching pulse generator; bitwise AND with the output of
It is equipped with a group of AND gates and an OR gate for synthesizing each output of the group of AND gates, and the switching pulse generator sequentially gates and extracts each bit of the video data signal and converts it into a serial video signal. A video display device characterized in that a video signal is used to display a video on the display element.