JPS62159393A - Time code reader - Google Patents

Abstract

PURPOSE:To reduce the number of logic elements by changing the generated frequency of a clock generator when the value of a register is out of a regulated range, and controlling the value so as to be within the regulated range. CONSTITUTION:A 15-20 bit counter 2 outputs the frequencies of half, quarter, one eighth, one sixteenth, ..., and when the counter is of 16 bits, it outputs the divided frequencies of up to one 2<16>-th. a data selector 3 selects one frequency out of each output frequency of the counter 2 with the data of SELo-m, and outputs it as a clock CK. A 5-8 bit counter 4 counts the clock CK, and continues a count operation during the pulse width of a time code signal, and a 5-8 bit register 5 stores a counted value with a latch pulse L at rear stage, and after that, the counter 4 is reset with a clear pulse CL. And an oscillation frequency control circuit 6, when the value of the register 5 is not within the range of a set value, generates a SELo-m signal, and changes the frequency of the clock CK generated from the data selector 3.

Description

[Detailed Description of the Invention] Industrial field of use Broadcasting VTRs and professional VTRs record time code signals on dedicated time code tracks or audio tracks, and define the absolute position of video information for each frame. There is. This time code signal allows editing and sending operations to be performed with O-frame accuracy. The time code signal includes a longitudinal time code (LTC) recorded on an audio track or a dedicated track (audio band),
Time code (ViT) recorded during the vertical blanking period
C), and the present invention relates to a longitudinal time code reading device.

In conventional technical broadcasting VTRs, the tape speed can be 1/40 to 50 times faster on the playback side than the recording speed (1x speed). In this case, the time code signal also changes accordingly during the pulse.

The longitudinal time code records and reproduces a pulse signal on an audio track or dedicated track in synchronization with the video signal, and one frame of the video signal is divided into 80 equal parts.
Records bit information. The time code signal takes a binary voltage of positive or 0, and the clock changes from positive to 0 or 0.
This is shown by the transition from to positive. Further, in the 80-bit information, bit 1 assumes that a transition is provided at the center of the clock interval, but bit O does not have a transition during the clock interval. This method is called the two-phase modulation force method (Bi-phase Mod
ulation). For example, all 80 bit signals are 0
If.

The modulation signal becomes 80 rectangular waves (40 cycles), and if all 80-bit signals are 1, it becomes 160 rectangular waves (80 cycles).

As a synchronization signal, 16 bits are used, with 12 consecutive bits being bit 1, the previous two bits being OO1, and the following two bits being 01. The running direction of the tape can be detected by detecting synchronization with consecutive 12 bits and checking whether the preceding and succeeding bits are 00 or Ol. The remaining 64 bits are 4 bits each for time data and user area (user can use it freely)
are arranged alternately to prevent 12 consecutive bits of data 1 from occurring.

When reading such a time code signal, the first method is used.

■Measure and store the time from one time code signal transition to the next.

■ Measure the time until the next transition and compare it with the time in ■. If it is less than 0.75%, the data bit is 1, and this transition is not a clock, but a 5th transition. , continue time measurement.

If it is 075% or more, this transition is determined to be a clock and is stored. Further, the data bit is set to O.

Problems to be Solved by the Invention In a digital time code reader, since there are 211 changes in a pulse, the frequency counter and register are made up of 15 to 20 bits. .

However, when the pulse of the time code is short (during high-speed running), only the lower 3 to 5 bits are used, and the upper bits are not used. On the other hand, when the time code pulse is long (during low-speed running), the counter uses up to the upper bits, but in order to use the data bit 1 or O for judgment, the effective bits are about the upper 5 bits. Often, bits below that amount are invalid data. In this way, although the number of effective bits is small, frequency counters, registers, adders, and comparators with a large number of bits must be provided.

The present invention solves the above problems and changes the frequency of the clock generator to generate a frequency counter, register,
It is an object of the present invention to provide a time code reading device that can set the number of bits of an adder and a comparator to an effective number of bits, and furthermore can easily create a pulse of 75% of the clock interval.

Means for Solving the Problems In order to solve the above problems, the present invention provides a clock generator whose generation frequency can be changed, a frequency counter, a register, and a clock generator whose generation frequency can be varied, and a register which can change the frequency of the longitudinal time code signal to be read during the pulses of the longitudinal time code signal. A control circuit that causes a counter to count the clock of a clock generator and stores the count value in a register, and when the value of the register is not within a certain range, changes the frequency generated by the clock generator to keep the count value constant. It is equipped with an oscillation frequency control circuit that controls the frequency to within the range.

Further, in the control circuit of the present invention, the control circuit sets the value of the register to 1 bit and 2 bits for the summand and the addend, respectively.
It is two-phase modulated by the 75% time signal obtained by comparing the output of the frequency counter with the output of the adder, which applies the bit-shifted value and the sum becomes three-quarters of the value in the register. This device is configured to demodulate a longitudinal time code signal, and is incorporated into a gate array.

Effect With the above configuration, the adder,
The number of bits in parts such as comparators that have a large number of gates per bit can be reduced, and the overall number of logic elements can be reduced.

EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 shows a block diagram of the time code pulse width meter side. 1
is an oscillator, which oscillates at 3.58 MHz in the example. 2 is a 15-20 bit counter.

1/2, 1/4, 1/8, 1/16 of the frequency of oscillator 1. ...outputs the frequency of counter 2
When is 16 bits, the frequency divided up to 1/216 is output. 3 is a data selector which selects one frequency from the data of 5ELo to 11 among the output frequencies of the counter 2 and outputs it as a clock CK. 4
is a 5- to 8-bit counter that counts the clock GK and continues counting during the pulse width of the time code signal. At the trailing edge, the 5- to 8-bit register 5 stores the count value by the latch pulse L, and then , the counter 4 is reset by the clear pulse CL. Reference numeral 6 denotes an oscillation frequency control circuit, which generates an SELo=m signal when the value of the register 5 is not within the set value range, and changes the frequency of the clock CK generated from the data selector 3. 7 is a control circuit that extracts the clock of the longitudinal time code and generates a latch pulse L at the timing of 5 clocks;
Thereafter, a clear pulse CL is generated and applied to the counter 4 and register 5, respectively.

FIG. 2 shows a time code reading time chart. 1
1 is the waveform of the time code signal. 12 is an etch pulse generated at the time of transition. 13 is a T7 pulse representing a 75% pulse, and by gate with the etch pulse, the etch pulse at Hi of the T7 pulse is determined to be data 1 as a transition at the clock midpoint, and rlJ pulse 14
occurs. Etch pulses other than those determined to be 1 are treated as clock pulses (pulse 2L) of the time code signal.
The value of the counter 4 is stored in the register 5 by this latch pulse L15, and the value of the counter 4 is cleared by a clear pulse CL16 created by shifting the latch pulse L. In this way, data PWo to PWn corresponding to the interval between latch pulses L are stored in the register 5.

FIG. 3 shows an example of the oscillation frequency control circuit 6. A comparator 21 compares the upper limit setting data set in the upper limit setting @23 with the value PWo=PWn of the register 5 (FIG. 1). 22 is a comparator, which similarly compares with the lower limit setting data set by the lower limit setting device 24.

Reference numeral 25 is a gate circuit which generates a pulse of 30 Ins from the pulse generator 26 every 30 m5 when the register values PWo to PWn are above the upper limit setting data or below the lower limit setting data.
The signal is applied to the up/down counter 27 at a rate of once every 24 hours.

Further, the up/down counter 27 changes the count value based on the output from the comparator 2I. At this time, if the frequency is higher than the upper limit setting data, the clock CK applied to the counter 4 is changed to lower the frequency, and if it is lower than the lower limit setting data, the clock CK applied to the counter 4 is changed to increase the frequency by one. 5 of this count value
By ELo”=m.

The frequency of the clock CK generated from the data selector 3 is selected, and the values PWo to PWn of the register 5 are set within the range between the upper and lower limits.

Note that if the counter 4 overflows and is reset, the above control will no longer be possible.

In case of overflow, it is necessary to install a gate circuit and use an overflow lock method to prevent further counting.

Fig. 4 shows a 75% pulse (T7 pulse) generation circuit. 31 is an adder, and a P is added to the register value PW.
W is being generated. A comparator 32 compares the value of TPW and the value CN of the counter, and generates a T7 pulse based on the comparison result. That is, the value of the register 5 (FIG. 1) is shifted by 1 bit to the X terminal of the adder 31, and the value is 1/2.
PWo''PWfi-1 is applied as the value of , and the value of register 5 is shifted by 2 bits and PWo=PWn-2 is applied as a 1/4 value to the Y terminal.The addition result is as follows.
Including carry C, the value is three-quarters of register 5.

This value is applied to the comparator 32, and the value CNo-CNn of the counter 4 (FIG. 1) is applied as the other comparison signal,
The output that becomes Hi when 3/4 PW>CN becomes the T7 pulse.

Effects of the Invention According to the present invention, in order to make the oscillation frequency variable regarding the number of register pits in the effective number of cow bones, it is necessary to install a counter, a data selector, and an oscillation frequency control circuit. It is possible to reduce the number of bits in parts such as , comparators, etc. where the number of gates per bit is large, and the number of logic elements can be reduced as a whole.

[Brief explanation of drawings]

FIG. 1 is a time code pulse width measurement block diagram showing an embodiment of the present invention, FIG. 2 is a time chart for reading a time code signal in the longitudinal direction, and FIG. 3 is a diagram showing an example of an oscillation frequency control circuit. FIG. 4 is a generation circuit diagram of a 75% pulse (T7 pulse). 1... Oscillator, 2... Counter, 3... Data selector, 4... Counter, 5... Register, 6... -
・Oscillation frequency control circuit, 7... control circuit, 21.22
...Comparator, 23... Upper limit setter, 24... Lower limit setter, 25... Gate circuit. 26... Pulse generator, 27... Up/down counter, 31... Adder, 32... Comparator agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 4 ■f■・■

Claims (1)

[Claims] 1. A clock generator whose generation frequency can be changed, a frequency counter, a register, and a counter that counts the clock of the clock generator during the pulse width of the longitudinal time code signal to be read. , a control circuit that stores the count value in a register, and an oscillation frequency that controls the frequency generated by the clock generator to be within a certain range by changing the frequency generated by the clock generator when the value of the register is not within a certain range. A time code reader equipped with a control circuit. 2. The control circuit applies values obtained by shifting the register value by 1 bit and 2 bits to the summand and addend, respectively, and performs addition such that the sum is three-quarters of the register value. Claim 1, characterized in that the device is configured to demodulate a two-phase modulated longitudinal time code signal using a 75% time signal obtained by comparing the output of the frequency counter with the output of the frequency counter. The time code reading device described in Section 1.