JP2592559B2 - Phase synchronization circuit of information recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit of an information recording / reproducing apparatus for recording information such as audio and video on a recording medium in which absolute time information is previously written in a recording area.

[0002]

2. Description of the Related Art A recordable optical disk such as a write-once optical disk (CD-WO) or a magneto-optical disk (CD-MO) has a recording area in which tracks undulating with a slight amplitude are spirally cut in advance. ing. The undulation of the track represents absolute time information called ATIP (Absolute Time In Progroove) data.
The frequency of the swell having a fundamental frequency of Hz is the ATI
Unit length corresponding to 1 bit of P data (frequency 44.1k
Every 7 cycles of Hz), ± 1 kHz changes according to the contents of the bit, ie, “1” or “0”.
In other words, ATIP data is written on the optical disc in advance as a change in the frequency of the undulation of the track.

[0003] The ATIP data is composed of a number of consecutive frames each including a fixed number (84 bits) of bits in one frame and having a fixed pattern of a frame synchronization signal at a predetermined position. The frame is to be repeated at a period of 75 Hz.

On the other hand, when information such as audio and video is recorded on the optical disk, the number of channels of the music, the presence or absence of pre-emphasis, the number of the music, the time from the start of the music, and the absolute time from the innermost circumference of the disk Are recorded at the same time. In the subcode Q data, one frame includes a fixed number (98 bits) of bits (however, the unit length corresponding to one bit is different from that in the case of ATIP data), and a fixed pattern of frame synchronization is provided at a predetermined position. It is composed of a number of frames consisting of bit strings with signals, and each frame is recorded at a period of 75 Hz.

[0005] Here, in the case where information such as audio and video is actually recorded on an optical disk, it is specified by standards that ATIP data and subcode Q data must be recorded in frame synchronization.

Conventionally, when information such as audio and video is recorded on an optical disk, a clock signal synchronized with ATIP data reproduced from the optical disk, a signal generation circuit for generating subcode Q data together with information such as audio and video, Here, the clock signal of the CD encoder (strictly speaking, this is A
The frequency is divided in accordance with the clock signal of the TIP data) into a servo system circuit for controlling the relative movement of the optical disk and the recording head to synchronize the phase, and the CD encoder performs frame synchronization of the ATIP data. The phase of the frame synchronization signal of the ATIP data and the phase of the frame synchronization signal of the subcode Q data are synchronized by generating the subcode Q data in synchronization with the signal.

[0007]

However, some CD encoders generate subcode Q data in synchronization with a frame synchronization signal of ATIP data only at the start of recording, and thereafter independently generate subcode Q data according to a predetermined format. In some cases, code Q data is generated. In this case, if synchronization between clock signals is disturbed due to offset, scratches, dust, or the like of an optical disc, the phase between frame synchronization signals is shifted and cannot be corrected as it is. There was a problem.

The present invention has been made in view of the above-mentioned conventional problems, and therefore, even when a signal generating circuit having no function of synchronizing the phase between frame synchronization signals is used except at the start of recording, the phase shift between the frame synchronization signals can be achieved. It is an object of the present invention to provide a phase synchronization circuit of an information recording / reproducing apparatus which can detect and correct this.

[0009]

According to the present invention, in order to achieve the above object, according to the present invention, one frame includes a fixed number of bits in a recording area in advance and a fixed pattern frame synchronizing signal is provided at a predetermined position. A frame including a fixed number of bits together with information such as audio and video and a fixed pattern of frame synchronization at a predetermined position are recorded on a recording medium on which absolute time information composed of a large number of consecutive frames composed of bit strings is recorded. A clock signal synchronized with absolute time information reproduced from the recording medium when recording control information composed of a large number of frames composed of a bit string including a signal;
A clock signal of a signal generation circuit that generates control information together with the information such as the audio and the video is input to a servo system circuit that controls the relative movement of the recording medium and the recording head, and is recorded so that their phases are synchronized. A phase synchronizing circuit of the information recording / reproducing apparatus, which has a function of changing a frequency dividing ratio, and divides a clock signal of a signal generating circuit to supply the clock signal to a servo system circuit; A second frequency divider having a function of dividing a clock signal synchronized with the absolute time information and supplying the divided signal to a servo system circuit; a phase of a frame synchronization signal of the absolute time information; A phase difference detection circuit for detecting the delay or advance of the control signal, and, when the frame synchronization signal of the absolute time information is behind the frame synchronization signal of the control information, reducing the frequency division ratio in the second frequency division circuit; , When the frame synchronization signal of the time information is ahead of the frame synchronization signal of the control information, the phase synchronization of the information recording / reproducing apparatus including a phase difference correction circuit for reducing the frequency division ratio in the first frequency division circuit A circuit is proposed. In claim 2, when the amount of delay or advance of the phase is large, the amount of reduction of the frequency division ratio in the second or first frequency dividing circuit is not increased, and the amount of phase delay or 2. A phase synchronization circuit for an information recording / reproducing apparatus according to claim 1, wherein when the amount of advance is small, the amount of reduction of the frequency division ratio in the second or first frequency dividing circuit is reduced.

[0010]

According to the first aspect of the present invention, the clock signal of the signal generation circuit and the clock signal synchronized with the absolute time information are divided by the first and second frequency divider circuits having the function of varying the frequency division ratio. The phase difference is supplied to the servo circuit. The phase difference detection circuit detects the delay or advance of the phase between the frame synchronization signal of the absolute time information and the frame synchronization signal of the control information. When the information frame synchronization signal is behind the control information frame synchronization signal, the frequency division ratio in the second frequency divider is reduced,
When the frame synchronization signal of the absolute time information is ahead of the frame synchronization signal of the control information, the frequency division ratio in the first frequency dividing circuit is reduced. According to the second aspect, when the amount of phase delay or the amount of advance is large, the second or first phase is set.
When the amount of decrease of the frequency division ratio in the frequency divider circuit is large, and when the amount of phase delay or advance is small, the second or first
Of the frequency dividing circuit in the frequency dividing circuit of (1) is reduced.

[0011]

FIG. 1 shows an embodiment of a phase synchronization circuit of an information recording / reproducing apparatus according to the present invention. In FIG. 1, 1, 2, 3, and 4 are input terminals, 5, 6 are output terminals, and 10 is an output terminal. A first frequency divider,
20 is a second frequency dividing circuit, 30 is a phase difference detecting circuit, and 40 is a phase difference correcting circuit.

The first frequency dividing circuit 10 receives an input signal from a CD encoder (not shown) via an input terminal 1 at 22.05 kHz.
The clock signal of z (hereinafter referred to as a reference clock) is divided and supplied to a servo system circuit (not shown) through an output terminal 5, and as shown in FIG. It comprises a bit binary counter 11, D flip-flops 12, 13, and 14, an inverter 15, a NOR gate 16, and a NAND gate 17.

The 4-bit binary counter 11 actually divides the frequency of the reference clock. Unless a load signal described later is supplied from the NAND gate 17 to the preset enable terminal PE, or when the load signal is supplied, Unless the 4-bit correction data other than “0001” is supplied from the phase difference correction circuit 40 to the preset data input terminals D3 to D0, the reference clock input to the clock terminal C is divided by 16, and the divided reference is input. A clock (hereinafter, referred to as a reference frequency-divided clock) is output from a terminal Q3. D flip-flops 12, 13
The NOR gate 16 detects the falling edge of the above-mentioned reference frequency-divided clock, and generates a short pulse synchronized with the falling edge, in this case, a pulse corresponding to one period of 22.05 kHz. The short pulse synchronized with the falling is input to the NAND gate 17 together with the later-described ATIP data delay signal, and becomes a load signal for the 4-bit binary counter 11. The load signal is supplied to the phase difference correction circuit 40 via the D flip-flop 14.

The second frequency dividing circuit 20 is a 22.05 kHz clock signal (hereinafter referred to as a wobble clock) synchronized with ATIP data of the optical disk inputted from the reproducing system of the optical head (not shown) via the input terminal 2. Is supplied to a servo system circuit (not shown) via the output terminal 6. As shown in FIG. 2, a 4-bit binary counter 21 with presets and D flip-flops 22 and 2 are provided.
3, 24, an inverter 25, a NOR gate 26, and a NAND gate 27.

The 4-bit binary counter 21 actually divides the frequency of the wobble clock. Unless a load signal described later is supplied from the NAND gate 27 to the preset enable terminal PE or when the load signal is supplied, Preset data input terminals D3 to D0
Unless the 4-bit correction data other than “0001” is supplied from the phase difference correction circuit 40 to the wobble clock input to the clock terminal C, the wobble clock is divided by 16 and the divided wobble clock (hereinafter referred to as wobble divided clock) It is called.)
From the terminal Q3. The D flip-flops 22 and 23 and the NOR gate 26 detect the falling edge of the wobble frequency-divided clock, and generate a short pulse synchronized with the falling edge, here a pulse corresponding to one period of 22.05 kHz. Has become. The short pulse synchronized with the falling is input to the NAND gate 27 together with an ATIP data advance signal described later, and becomes a load signal for the 4-bit binary counter 21. Also,
The load signal is supplied to the phase difference correction circuit 40 via the D flip-flop 24.

The phase difference detection circuit 30 includes a frame synchronization pulse (hereinafter, referred to as a subcode synchronization pulse) of the subcode Q data input through the input terminal 3 and an optical disk input through the input terminal 4. A delay or advance of a phase with respect to a frame synchronization pulse (hereinafter, referred to as an ATIP synchronization pulse) of the ATIP data of the ATIP data is detected. ATI of high level by the corresponding width
A P-data delay signal is supplied to the phase difference correction circuit 40, and when the ATIP sync pulse is advanced with respect to the subcode sync pulse, an ATIP data advance signal of a high level by a width corresponding to the advancing time is supplied to the phase difference correction circuit 40. As shown in FIG. 3, D flip-flops 31 and 32, an inverter 3
3. It comprises a NAND gate 34 and NOR gates 35 and 36.

The above-mentioned frame synchronization pulse of the subcode Q data is a short pulse output simultaneously with the frame synchronization signal of the subcode Q data from a CD encoder (not shown), and the frame synchronization pulse of the ATIP data of the optical disk. Is obtained by supplying a frame synchronizing signal of ATIP data of an optical disk, which is output from a reproducing system of an optical head (not shown), to a circuit (not shown) for outputting a predetermined short pulse when the pattern is detected. Both are substantially the same as the frame synchronization signal of the subcode Q data and the frame synchronization signal of the ATIP data of the optical disk.

The phase difference correction circuit 40 includes a phase difference detection circuit 3
ATIP data delay signal or AT input from 0
The time width of the IP data advance signal, that is, the delay amount or the advance amount is measured, and the correction data corresponding to the delay amount or the advance amount is supplied to the first frequency dividing circuit 10 or the second frequency dividing circuit 20 to perform the correction. The frequency dividing ratio in the second frequency dividing circuit 20 or the first frequency dividing circuit 10 is reduced in accordance with the delay amount or the advance amount. As shown in FIG. It comprises inverters 43 and 44 and AND gates 45 and 46.

A reference clock is input to a clock terminal C of the 4-bit binary counter 41 via an inverter 43, and a count enable terminal CEP
Is supplied with an ATIP data delay signal via an AND gate 45. When the ATIP data delay signal becomes a high level, the reference clock is counted and its time width is measured (however, ripple Since the carry-out terminal TC is connected to the other input terminal of the AND gate 45, when the count value reaches "1111", the operation stops and no further counting is performed.) The 4-bit count value corresponding to the time width of the ATIP data delay signal is supplied to the 4-bit binary counter 11 of the first frequency dividing circuit 10 as correction data. The data of "0001" is fixedly input to the input terminals D3 to D0 of the preset data of the 4-bit binary counter 41, and the data is input to the D flip-flop 14 of the first frequency dividing circuit 10.
And the correction data for the 4-bit binary counter 11 is fixed to "0001".

The 4-bit binary counter 42
The wobble clock is input to the clock terminal C of the UART through the inverter 44, the ATIP data advance signal is input to the count enable terminal CEP via the AND gate 46, and the ATIP data advance signal is high. When the level reaches the level, the wobble clock is counted and its time width is measured (however, since the ripple carry-out terminal TC is connected to the other input terminal of the AND gate 46, the counted value is "111").
When it reaches "1", it stops and there is no further counting. ). The 4-bit count value corresponding to the time width of the ATIP data advance signal is used as correction data in the second frequency dividing circuit 2.
0 is supplied to a 4-bit binary counter 21. The data "0001" is fixedly input to the preset data input terminals D3 to D0 of the 4-bit binary counter 42.
And the correction data for the 4-bit binary counter 21 is fixed to "0001" at the timing of the load signal supplied from the D flip-flop 24.

The first and second frequency dividing circuits 10 and 2
The outputs of the inverters 15 and 25 during 0 may be input to the clock terminals C of the 4-bit binary counters 41 and 42, respectively. In this case, the inverters 43 and 44 become unnecessary.

FIGS. 5 and 6 are signal waveform diagrams showing an example of the operation of the circuit of FIG. 1. Hereinafter, the operation of the circuit will be described with reference to FIGS.

The reference clock a input from the input terminals 1 and 2 to the first and second frequency dividing circuits 10 and 20, respectively.
If the phases of the subcode synchronization pulse c and the ATIP synchronization pulse d input to the phase difference detection circuit 30 from the input terminals 3 and 4 match, the wobble clock b is 16 minutes by the 4-bit binary counters 11 and 21, respectively. The signal is circulated and becomes a reference frequency-divided clock and a wobble frequency-divided clock, which are output to servo circuits via output terminals 5 and 6. The servo system circuit compares the phases of the reference frequency-divided clock and the wobble frequency-divided clock, and controls the rotation of the optical disk so that they match.

Here, the subcode synchronization pulse c and AT
When the phase of the IP synchronization pulse d is shifted as shown in the figure, that is, when the ATIP synchronization pulse d is delayed with respect to the subcode synchronization pulse c, the phase difference detection circuit 30 sets the phase difference detection circuit 30 high by a width corresponding to the delay time. A level ATIP data delay signal e is output. In this case, the ATIP data advance signal f remains at the low level.

When the ATIP data delay signal e becomes high level, the 4-bit binary counter 41 of the phase difference correction circuit 40 starts counting the reference clock a. At this time, if the delay of the ATIP synchronization pulse d with respect to the subcode synchronization pulse c is large, that is, if the period of the high level of the ATIP data delay signal e is long, the count value of the 4-bit binary counter 41 reaches “1111” and the ripple carry Since the signal g is output from the out terminal TC, the output h of the AND gate 45 becomes low level, and the counting stops. The terminals Q3 to Q0 of the 4-bit binary counter 41
Is output as correction data i by the first frequency divider 1
0 is input to preset data input terminals D3 to D0 of the 4-bit binary counter 11.

On the other hand, the ATIP data delay signal e is also input to the NAND gate 17 of the first frequency divider 10, and the pulse synchronized with the falling edge of the reference frequency-divided clock output from the NOR gate 16 is set to the low level. And supplies it to the preset enable terminal PE of the 4-bit binary counter 11 as the load signal j. Therefore, the above-mentioned correction data i is loaded into the 4-bit binary counter 11 with the reference clock a immediately after the reference frequency-divided clock first falls after the ATIP data delay signal e becomes low level.

At this time, the correction data i is "1" as described above.
111 ”, the Q of the 4-bit binary counter 11
The three outputs become "1" and become "0" at the next reference clock a, that is, a reference frequency-divided clock k in which a short pulse is inserted immediately after a pulse obtained by dividing the reference clock a by 16 is obtained.
Since the short pulse is regarded as one of the reference divided clocks in the servo circuit, the reference divided clock and the wobble divided clock are not synchronized in the servo circuit.
Here, it is determined that the wobble divided clock is delayed,
The servo is operated in a direction to advance the phase of the wobble frequency-divided clock. As a result, the phase of the ATIP synchronization pulse d also advances, and the phase difference from the subcode synchronization pulse c decreases. The load signal 1 corresponding to the load signal j is supplied to the preset enable terminal PE of the 4-bit binary counter 41 of the phase difference correction circuit 40 from the D flip-flop 14 of the first frequency divider 10.
Since the ATIP data delay signal e is at a low level, it has nothing to do with the operation.

The above operation is repeated as long as the high-level ATIP data delay signal e is output from the phase difference detection circuit 30, whereby the phase delay of the ATIP synchronization pulse d with respect to the subcode synchronization pulse c is corrected, Match. When the phase difference between the ATIP synchronizing pulse d and the subcode synchronizing pulse c decreases, the correction data i output from the 4-bit binary counter 41
Becomes smaller than “1111”, and the insertion position of the above-described short pulse gradually approaches the next pulse immediately after the pulse divided by 16, so that the ATIP synchronization pulse d becomes There is no reverse progression for the code synchronization pulse c.

Also, when the phase of the ATIP synchronization pulse is ahead of the subcode synchronization pulse,
If a high level output appears in the data advance signal,
The 4-bit binary counter 42 of the phase difference correction circuit 40 counts the wobble clock to obtain correction data corresponding to the amount of advance of the phase, and loads the correction data into the 4-bit binary counter 21 of the second frequency dividing circuit 20. Then, a wobble frequency-divided clock in which a short pulse is inserted after a pulse obtained by dividing the wobble clock by 16 is obtained, and the servo system circuit operates the servo in a direction to advance the phase of the reference frequency-divided clock, thereby changing the phase of the ATIP synchronization pulse. Delay and match with subcode sync pulse.

As described above, according to the above circuit, when the ATIP synchronization pulse lags behind the subcode synchronization pulse, a short pulse is inserted into the reference frequency-divided clock to reduce the frequency division ratio with respect to the wobble clock. Because
The operation of the servo system circuit can be made to work in the direction to advance the phase of the wobble frequency-divided clock, that is, in the direction to advance the phase of the ATIP synchronization pulse with respect to the subcode synchronization pulse.
Further, when the ATIP synchronization pulse is ahead of the subcode synchronization pulse, the frequency division ratio with respect to the reference clock is reduced by inserting a short pulse into the wobble frequency division clock. The phase of the peripheral clock can be advanced, that is, the phase of the ATIP synchronization pulse can be delayed in relation to the subcode synchronization pulse, whereby the phase of the ATIP synchronization pulse matches the phase of the subcode synchronization pulse. Can be.

[0031]

As described above, according to the first aspect of the present invention, the first and second clock signal synchronizing with the clock signal of the signal generation circuit and the absolute time information have the function of varying the frequency division ratio. The frequency is divided by the frequency dividing circuit 2 and supplied to the servo system circuit, and the phase difference detecting circuit detects the delay or advance of the phase between the frame synchronization signal of the absolute time information and the frame synchronization signal of the control information. When the frame synchronization signal of the absolute time information is behind the frame synchronization signal of the control information by the phase difference correction circuit, the frequency dividing ratio in the second frequency dividing circuit is reduced. By reducing the frequency division ratio in the frequency division circuit of 1, the phase of the frame synchronization signal of the absolute time information is advanced or delayed by the operation of the servo system circuit with respect to the frame synchronization signal of the control information. Even if a signal generation circuit without the function of synchronizing the phase between frame synchronization signals is used except at the start of recording, the phase shift between the frame synchronization signals due to offset, scratches, dust, etc. of the optical disk is detected. Yes, you can fix this.

According to the second aspect of the present invention, when the amount of phase delay or advance is large, the amount of decrease in the frequency division ratio is not increased, and when the amount of phase delay or advance is small, the amount of minute delay is small. Since the amount of decrease in the circumference ratio is reduced, the time required for matching the phases can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a phase synchronization circuit of an information recording / reproducing apparatus according to the present invention.

FIG. 2 is a detailed circuit diagram of first and second frequency dividers in FIG. 1;

FIG. 3 is a detailed circuit diagram of a phase difference detection circuit in FIG. 1;

FIG. 4 is a detailed circuit diagram of a phase difference correction circuit in FIG. 1;

FIG. 5 is a signal waveform chart showing an example of the operation of the circuit of FIG. 1;

FIG. 6 is an enlarged view of a signal waveform showing an example of the operation of the circuit of FIG. 1;

[Explanation of Symbols] 10: first frequency dividing circuit, 20: second frequency dividing circuit, 30 ...
Phase difference detection circuit, 40... Phase difference correction circuit.

Claims (2)

(57) [Claims] 1. An absolute time information is recorded in advance in a recording area, in which one frame includes a fixed number of bits and a plurality of continuous frames composed of a bit string provided with a frame synchronization signal of a fixed pattern at a predetermined position. Recording media,
When recording control information composed of a number of frames including a bit string provided with a fixed pattern of frame synchronization signal at a predetermined position, one frame includes a fixed number of bits together with information such as audio and video. A servo system for controlling a relative movement of the recording medium and the recording head by using a clock signal synchronized with the absolute time information reproduced from the recording medium and a clock signal of a signal generation circuit for generating control information together with the information on the audio and the video. A phase synchronization circuit of an information recording / reproducing device that inputs a signal to a circuit and records it so that its phase is synchronized. The phase synchronization circuit has a function of varying the frequency division ratio. A first frequency divider circuit for dividing the clock signal synchronized with the absolute time information and supplying the frequency-divided clock signal to the servo circuit; A phase difference detection circuit that detects a delay or advance of the phase between the frame synchronization signal of the absolute time information and the frame synchronization signal of the control information, and the phase synchronization signal of the absolute time information is delayed with respect to the frame synchronization signal of the control information. If the frame synchronization signal of the absolute time information is ahead of the frame synchronization signal of the control information, the frequency division ratio of the first frequency division circuit is reduced. A phase synchronization circuit for an information recording / reproducing apparatus, comprising: a phase difference correction circuit for reducing a ratio. 2. When the amount of delay or advance of the phase is large, the amount of reduction of the frequency division ratio in the second or first frequency dividing circuit is not increased. 2
2. The phase synchronization circuit according to claim 1, wherein the amount of decrease of the frequency division ratio in the first frequency division circuit is reduced.