JPH0574147B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronization circuit that can detect a synchronization signal included in a digital input signal and perform appropriate synchronization protection when the synchronization signal is lost.

[Technical background of the invention]

Recently, digital audio systems have been developed because they enable high-quality audio reproduction. Digital audio systems include those that use magnetic tape and those that use disks. A compact disk (CD) system that uses a disk to optically read out digital information recorded on the disk using a laser beam has been developed and is about to be put into practical use.

In the case of a compact disc, as is well known, digital information is subjected to EF (eight to fourteen) modulation, arranged in a frame in a predetermined format, and recorded on the disc. One frame includes a frame synchronization signal placed at the beginning, multiple audio information words, and error correction bits, and as a whole.
Consists of 588 channel bits. The synchronization signal consists of 24 channel bits and has a specific variation pattern that allows it to be distinguished from other information.

The frame synchronization signal is used to generate a control signal for dividing frames and dividing data within a frame into predetermined units when reproducing audio information. For this reason, the playback device is provided with a synchronization signal detection circuit. Further, a synchronization protection circuit is provided which is used in combination with the synchronization signal detection circuit and has a function of interpolating the synchronization signal when the synchronization signal is lost due to dropout due to a scratch on the disk.

FIG. 1 shows a conventional synchronization circuit including a synchronization signal detection circuit and a synchronization protection circuit, and FIGS. 2A and 2B show timing diagrams for explaining its operation.

In FIG. 1, one frame of N-bit input signal including a synchronization signal applied to input terminal 1 is 1
A clock signal generated based on the output of a PLL circuit that detects the clock component included in the reproduced signal from the disk is applied to the clock terminal 2 for each frame, and is applied to the synchronization signal detection circuit 3 to detect the synchronization signal. do. Synchronous signal detection circuit 3
The output of is connected to the gate circuit 4. The output of the gate circuit 4 divides the frequency of the clock signal. Connected to the clear terminal of the 1/N frequency divider (N-ary counter) 5. The output of the 1/N frequency divider 5 is connected to a window generator 6, which output is connected to a counter 7 which is cleared by the output of the gate circuit 4. A selector 8 connects the output of the window generator 6 or counter 7 to the gate circuit 4.
Connect to the control terminal of The output of the 1/N frequency divider 5 is connected to an output terminal 9.

In the synchronization circuit configured as described above, the synchronization signal detection circuit 3 detects the synchronization signal included in the input signal for each frame and outputs it to the gate circuit 4. The gate circuit 4 controls the supply of the synchronization detection signal of the synchronization signal detection circuit 3 to the 1/N frequency divider 5 in accordance with the output of the selector 8 . 1/N frequency divider 5 is gate circuit 4
It is cleared every time the output of the clock signal becomes "H", and a frame synchronization control signal is output to the output terminal 9 every N bits of the clock signal. After the frequency divider 5 outputs the frame synchronization control signal, the window generator 6 sets its output to "H" for several bits before and after the Nth bit when the next frame synchronization control signal is supposed to be output. That is, a window is created and the gate circuit 4 is made conductive via the selector 8. When synchronization is established between the synchronization signal detection circuit 3 and the frequency divider 5, the selector 8 supplies the output of the window generator 6 to the gate circuit 4 so that the output of the synchronization signal of the previous frame is generated by the synchronization signal of the previous frame. The window supplies the output signal of the synchronization signal detection circuit 3 to the frequency divider 5.
This prevents malfunctions caused by noise other than the true synchronization signal.

If the frame synchronization signal cannot be detected due to dropout or the like, the output of the synchronization signal detection circuit 3 and the output of the gate circuit 4 are lost as shown in FIG. 2A. Even in such a case, as shown in FIG. 2A, an output signal appears at the output terminal 9 every N bits due to the frequency division operation of the frequency divider 5. That is, the synchronization signal is interpolated. If no synchronization signal is detected, the counter 7 is not cleared and is counted up every frame by the window output of the window generator 6. When the counter 7 reaches a preset count (for example, 4 frames), its output becomes "H". The selector 8 opens the gate circuit 4 when the output of the counter 7 becomes "H". In this state, the first signal output from the synchronization signal detection circuit 3 is output from the gate circuit 4 and is then output to the frequency divider 5.
and clears counter 7. In this case the frequency divider 5
is configured to output an output signal to the output terminal 9 when cleared.

However, as shown in FIG. 2B, if the output of the synchronization signal detection circuit after the output of the counter 7 becomes "H" is noise,
This noise clears the frequency divider 5 and counter 7. Therefore, the window generator 6 creates a window of several bits around the Nth bit from this noise. Therefore, even though the synchronization signal is detected correctly after the noise, the timing of the window output of the window generator 6 and the output of the synchronization signal detection circuit 3 do not match, so the output signal from the gate circuit 4 is No output.
After divider 5 is cleared by noise, 1/
Due to the N frequency division operation, an erroneous synchronization control signal is output to the output terminal 9 every N bits. Then, the frequency divider 5 and the counter 7 can be synchronized only after the output of the counter becomes "H" and a correct synchronization signal is detected.

[Problems with background technology]

As explained above, conventional synchronization circuits have the disadvantage that if a synchronization signal is lost for some reason, an erroneous synchronization control signal will be generated due to the influence of noise and the like.

[Purpose of the invention]

An object of the present invention is to provide a synchronous circuit configured to reduce the effects of noise and the like.

[Summary of the invention]

The synchronization circuit according to the present invention includes a synchronization signal detection circuit that receives a digital input signal including a synchronization signal for each frame and detects the synchronization signal, and a synchronization control circuit that counts clock pulses and is synchronously controlled by the output of the synchronization signal detection circuit to generate a synchronization control signal. a first counter that generates a synchronous signal, a first window generator that is controlled by this counter, and an output of a synchronization signal detection circuit that is controlled by a window output generated by this window generator to the first counter. In a conventional synchronization circuit having a first gate circuit to be connected and a second counter that counts the number of frames in which the first counter is not synchronized with the synchronization signal detection circuit, when the second counter changes its output state, A second circuit for deriving the output of the synchronization signal detection circuit.
a third gate circuit which takes the logical sum of the output of the second gate circuit and the output of the first gate circuit, and which counts clock pulses and is synchronously controlled by the output of the third gate circuit. and a second window generator that is controlled by the third counter and produces a window output, and when the second counter counts a predetermined number of frames, the second window generator generates a window output. The first gate circuit is controlled.

Therefore, according to the invention, the first counter is synchronized when the output signal from the synchronization signal detection circuit falls within the window created by the first window generator, while the first counter is synchronized for a predetermined number of frames. When the output signal of the synchronization signal detection circuit does not fall within the window of the first window generator, synchronization occurs when the output signal of the synchronization signal detection circuit falls within the window created by the second window generator. be done.

[Embodiments of the invention]

First, an overview of an optical digital audio disc playback device to which an embodiment of the present invention is directed will be described.

As shown in FIG.
The digital information recorded on the disk 113 mounted on the turntable 121 driven by the optical pickup device 114 is reproduced by the optical pickup device 114. The optical pickup device irradiates the recording surface of the disk 113 with a laser beam from a semiconductor laser 114a through a beam splitter 114b and an objective lens 114c, and generates an audio information signal in a form with predetermined modulation (EFM) and interleaving. The reflected light from the pit representing the PCM digital data including the objective lens 114c,
The beam is guided to a four-split photodetector 114d via a beam splitter 114b to obtain four reproduced signals. The pick-up device is feed motor 1
15 linearly drives the disk 113 in the radial direction.

The four output signals of the four-split photodetector 114d are supplied to the matrix circuit 116 and subjected to predetermined matrix calculation processing, thereby generating a focus error signal F, a tracking error signal T, and a high frequency signal (modulated digital information). Separated into RF.

The focus error signal F is supplied to the focus servo system FS of the optical pickup device 114 together with the focus search signal from the focus search circuit 110. Further, the tracking error signal T is supplied to the tracking servo system TS of the pick-up device 114 together with a search control signal given from a system controller 117, which will be described later, and is also supplied to the feed motor 115 to perform linear tracking control of the pick-up device. .

The high frequency signal RF is supplied to the reproduction processing system 118 as the main data component. In the reproduction processing system, the modulated digital information RF is guided to a waveform shaping circuit 120 controlled by a slice level (eye pattern) detector 119, and only digital data components from which analog components have been removed are extracted. The data component is
The signal is supplied to a PLL type synchronous clock regeneration circuit 121 and an edge detector 122a of the first signal processing system 122.

The synchronous clock signal from the synchronous clock regeneration circuit 121 is supplied to the synchronous signal separation clock generation circuit 122b of the first signal processing system 122 to generate a synchronous signal separation clock.

The edge detector 122a functions to detect edges (change points) of the high frequency signal RF in the form of NRZI modulated EFM data (NRZ) and convert it into the original EFM data. The output signal of the edge detector 122a is guided to a synchronization signal detection circuit 122c,
The synchronization signal is separated using the synchronization signal separation clock generated based on the synchronization clock extracted from the high frequency signal RF of NRZI by the synchronization clock regeneration circuit 121, and the demodulation circuit 122d
Each data is demodulated using the original number of bits.

The synchronization signal separated by the synchronization signal detection circuit 122c is supplied to the input data processing timing signal generation circuit 122f together with the synchronization signal separation clock via the synchronization signal protection circuit 122e.
The synchronous signal protection circuit 122e is the synchronous signal detection circuit 1
22c has a function of interpolating the synchronization signal in order to prevent malfunction when an erroneous detection occurs.

The demodulated signal output from the demodulation circuit 122d is sent to the input/output control circuit 12 of the second signal processing system 123, which will be described later, via the data bus input/output control circuit 122g.
3a, and the control signal and display signal components, which are subcodes, are supplied to the control display processing circuit 122h and the subcode processing circuit 122.
i. The subcode data subjected to necessary error detection and correction by the subcode processing circuit 122i is sent to the system controller 1 via the system controller interface circuit 122q.
17.

The system controller 117 is equipped with a microcomputer, an interface circuit, and a driver integrated circuit, and controls the playback device to a desired state according to commands given by the control switch 124, and also controls the above-mentioned subcodes (for example, the playback song). index information) is displayed on the display 125.

The timing signal from the timing signal generation circuit 122f controls the input/output control circuit 122g via the data selection circuit 122j, and is also applied to the frequency detector 122k and phase detector 122l to drive the disk motor 111 via the PWM modulator 122m. Performs automatic frequency control (AFC) and automatic phase control (APC) for constant linear velocity (CLV) driving. A system clock generated by a system clock generation circuit 122p driven by a crystal oscillator 122n is supplied to the phase detector 122l.

Input/output control circuit 12 of second signal processing system 123
The demodulated data passed through 3a is sent to a syndrome detector 123b for error detection and correction or correction, an error pointer control circuit 123c, and a correction circuit 123d.
The digital-to-analog (D/A) converter 1 receives necessary error correction, deinterleaving, error correction, etc. through the data output circuit 123e.
26. External memory control circuit 123f
controls the external memory 127 in which data necessary for correction is written in cooperation with the data selection circuit 122j, and takes in the data necessary for correction via the input/output control circuit 123a.

Timing control circuit 123g receives the system clock from system clock generation circuit 122p and generates timing control signals necessary for error correction and correction and D/A conversion.

The muting control circuit 123h controls the output circuit 123e to perform muting based on the output from the error pointer control circuit 123c or the control signal given via the system controller 117, at the time of error correction and at the start and end of operation of the playback device. conduct.

The audio signal converted into analog by the D/A converter 126 is passed through a low pass filter (LDF) 128,
A speaker 130 is driven via an amplifier 129.

Hereinafter, the synchronous circuit according to the present invention will be explained with reference to FIGS. 4 and 5A and 5B.

FIG. 4 shows a synchronous circuit according to an embodiment of the present invention, in which the same parts as in the conventional synchronous circuit shown in FIG. 1 are given the same reference numerals. This synchronous circuit includes a gate circuit 10 and an I/N frequency divider 1.
1, a window generator 12 and an OR gate 13.

The output of the synchronizing signal detection circuit 3 is connected to a gate circuit 10, and this gate circuit is configured to open when the output of the counter 7 becomes "H". The output of the gate circuit 10 is connected via an OR gate 13 to a clear terminal of an I/N frequency divider (N-ary counter) 11 that divides the frequency of the clock signal. In addition, the output of the gate circuit 4 is passed through the OR gate 13 to the frequency divider 1.
Connected to the clear terminal of 1. The output of the frequency divider 11 is connected to a window generator 12, which output is connected to the selector 8. The selector 8 supplies the output of the window generator 6 to the gate circuit 4 when the output of the counter 7 is "L", and supplies the output of the window generator 12 to the gate circuit 4 when the output of the counter 7 is "H". configured to supply.

In the synchronization circuit configured as described above, one frame of N-bit input signal including the synchronization signal is
When applied to the input terminal 1 for each frame, the synchronization signal detection circuit 3 detects the synchronization signal included in the input signal for each frame and outputs it to the gate circuits 4 and 10. The I/N frequency divider 5 is cleared each time the output of the gate circuit 4 becomes "H" and sends a frame synchronization signal to the output terminal 9. The output of the window generator 6 should be N after the I/N frequency divider 5 outputs the frame synchronization control signal and then outputs the next frame synchronization control signal.
It becomes "H" for several bits before and after the th bit, and this output is applied to the gate circuit 4 via the selector 8. When normal synchronization is established between the synchronization signal detection circuit 3 and the I/N frequency divider 5, only when the output signal of the synchronization signal detection circuit 3 falls within the window created by the window generator 6. Output of gate circuit 4 is “H”
This prevents errors caused by noise other than the synchronization signal.

If the frame synchronization signal cannot be detected due to dropout or the like, or if the synchronization is lost, the counter 7 is counted up by the window generator 6 for each frame. counter 7
is a preset number of frames (e.g. 4
When the number of frames) is counted, the output becomes "H" as shown in FIG. 5A. This allows window generator 1
The output of 2 is connected to gate circuit 4, and gate circuit 10 is opened. When normal synchronization is achieved (that is, when the output of the counter 7 is “L”), the frequency divider 11 is controlled by the output of the gate circuit 4.
Since it is cleared via the OR gate 13, it is synchronized with the frequency divider 5. However, counter 7
When the output of
Cleared via OR gate 13. Therefore, from this point on, the output of the window generator 12 for several bits before and after the Nth bit becomes "H" and the selector 8
The gate circuit 4 is opened via. Therefore, the fifth
As shown in Figure A, if the output signal that is first output from the synchronization signal detection circuit 3 and clears the divided period 11 while the output of the counter 7 is "H" is a synchronization signal, the synchronization signal detection circuit The next synchronizing signal output from 3 is taken out from gate circuit 4 and clears frequency divider 5 and counter 7. Therefore, the synchronizing signal outputted from the synchronizing signal detection circuit 3 from now on is taken out from the gate circuit 4 which is opened for each frame by the output of the window generator 6, and the synchronizing signal outputted from the synchronizing signal detecting circuit 3 and the frequency divider 5 is taken out from the gate circuit 4 which is opened for each frame by the output of the window generator 6. synchronization can be achieved.

As shown in FIG. 5B, when noise is first output from the synchronization signal detection circuit 3 after the output of the counter 7 becomes "H", the frequency divider 11 is cleared by this noise output. . However, from this point on, no output signal is output from the gate circuit 4 unless the output signal of the synchronization signal detection circuit 3 enters within several bits before and after the Nth bit, that is, within the window created by the window generator 12. When a synchronization signal is detected successively after the noise output, the second and subsequent synchronization signals are taken out from the gate circuit 5 and connected to the synchronization signal detection circuit 3 and the I/N portion, as in the case of FIG. 5A. Synchronization with the frequency generator 5 can be achieved.

〔Effect of the invention〕

Therefore, the synchronous circuit of the present invention can eliminate the disadvantage that, unlike the conventional synchronous circuit, synchronization cannot be achieved due to the influence of noise even though the synchronous signal is correctly detected.

[Brief explanation of the drawing]

Figure 1 shows the configuration of a conventional synchronous circuit, Figure 2 shows the configuration of a conventional synchronous circuit.
Figures A and B are timing diagrams for explaining the operation of the synchronization circuit shown in Figure 1, Figure 3 is a block diagram of an optical digital audio disc playback device in which the synchronization circuit of the present invention can be used, and Figure 4 is a A diagram showing the configuration of a synchronous circuit according to an embodiment of the present invention, and FIGS. 5A and 5B are timing charts for explaining the operation of the synchronous circuit shown in FIG. 4. 1...Input terminal, 2...Clock terminal, 3...
Synchronous signal detector, 4, 10...first and second gate circuits, 5...1/N frequency divider (first counter), 6...first window generator, 7...second counter, 8... selector, 9... output terminal, 11...
...1/N frequency divider (third counter), 12... second window generator.

Claims (1)

[Scope of Claims] A synchronizing signal detection circuit that receives a digital input signal containing a synchronizing signal for each frame and detects the synchronizing signal; and a synchronizing signal detecting circuit that counts clock pulses and is synchronously controlled by the output of the synchronizing signal detecting circuit. a first counter that generates a synchronization control signal; a first window generator that is controlled by the first counter and generates a window output; and a first window generator that generates a window output that is controlled by the first counter; a first gate circuit that connects the output of the signal detection circuit to the first counter, and only when the output signal of the synchronization signal detection circuit falls within the window created by the first window generator,
a first circuit means configured to synchronize the first counter with the synchronization signal detection circuit to generate the synchronization control signal; and a number of frames in which the synchronization signal detection circuit and the first counter are not synchronized. a second counter that changes its output state when a predetermined number of frames are counted; a second gate circuit that derives the output of the synchronization signal detection circuit when the second counter changes its output state; a third gate circuit that takes the logical sum of the output of the second gate circuit and the output of the first gate circuit; and a third gate circuit that counts the clock pulses and is synchronously controlled by the output of the third gate circuit. a counter, and a second window generator that is controlled by the third counter to generate a window output, and in a state where the synchronization signal detection circuit and the first counter are synchronized, the first second circuit means adapted to synchronize a counter and said third counter; and when said second circuit means changes its output state, said first A synchronous circuit comprising: a control means for controlling a gate circuit of the synchronous circuit.