JPS62121978A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speedily input and output data of plural bits in time division through a shared external terminal by selectively controlling the action of a two-way latch circuit based on an external selection signal. CONSTITUTION:When data is read out of a memory array MA1 to the two-way latch circuit 2A, the external selection signal phi is made at H, and only the circuit 2A is activated. When data is read out of an array MA2 to the two-way latch circuit 2B, the signal phi is made at L, and only the circuit 2B is activated. The data from the circuit 2A or 2B is outputted through terminals P0-P7. On the other hand, signals to the terminals P0-P7 are stored in the arrays MA1 and MA2 through the circuits 2A and 2B according as the signal is H or L.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory device, and for example, a semiconductor memory device in which data of a plurality of bits constituting one set of data can be input/output in several times in a time-sharing manner. It relates to techniques that are effective when applied to devices.

[Background technology]

A semiconductor memory device that inputs and outputs 8-bit data in parallel, for example, usually has at least eight data input and output terminals. Therefore, as the number of bits of input/output data increases, the number of data input/output terminals also increases, leading to an increase in the size of the chip.

Therefore, in order to reduce the number of data input/output terminals, the present inventor considered a semiconductor memory device that can time-divide and input/output multiple bits of data constituting one set of data in several batches. However, in that case, if an internal control signal formed based on the normal external No. 48 is used as a control signal for inputting and outputting data in a time-sharing manner, there will be a time delay and other controls for forming the control signal. It has been found that timing constraints on signal formation cause delays in access time and impede high-speed data input/output.

An example of a document describing a semiconductor memory device is rLSI published by Ohmsha on November 30, 1980.
There are Handbook J P2S5 to P2S5.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that can expand the number of input/output data bits without increasing the number of data input/output terminals and can achieve high-speed data input/output. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an external terminal is commonly connected to a plurality of bidirectional latch circuits that receive data from the memory array and also supply data to the memory array, and the control means directly receives an external selection signal for selecting the bidirectional latch circuit. By selectively controlling the IIJ operation of the bidirectional latch circuit based on the signal, multiple bits of data constituting one set of data can be input/output in a time-sharing manner and at high speed via a common external terminal. It is something.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. The semiconductor memory device shown in the figure is formed on one semiconductor substrate using known semiconductor integrated circuit technology. This semiconductor memory device is applicable to, but not limited to, a microcomputer system, and is capable of time-divisionally inputting and outputting 16-bit data by dividing it into lower 8 bits and upper 8 bits via a data bus (not shown). .

MAL and MA2 are memory arrays in which memory cells (not shown) are arranged in n rows and 8 columns, and memory cells in the same row are data lines corresponding to each row. memory cells in the same column are connected to word lines (not shown) corresponding to each column.

The data lines D0 to D1. are respectively coupled to an 8-bit parallel-in/parallel-out type bidirectional latch circuit 2A corresponding to memory array MA1 and an 8-bit parallel-in/parallel-out type bidirectional latch circuit 2B corresponding to memory array MA2. Both latch circuits 2A and 2B have eight data input/output terminals P0 to P7.
Commonly connected to. The configuration of the bidirectional latch circuits 2A and 2B is as follows.

Although not particularly limited, it may be of a dynamic type or a static type, and for example, its input/output stage can take a three-state state via a clocked inverter circuit (not shown). For example, input/output control lines L□, L2
When the input/output control line L2 is set to a high level, the input/output stage is set to an active state where data can be input/output, and when the input/output control line L2 is set to a low level, the input/output stage is set to a high impedance state and data cannot be input/output. It becomes impossible to output.

In the figure, 3 is a selection control circuit that activates either one of the bidirectional latch circuits 2A and 2B.

This selection control circuit 3 is a bidirectional latch circuit 2A or 2B.
Directly receives external selection signal φ for selecting from external terminal Ps, and based on that signal, bidirectional latch circuits 2A, 2
B input/output control line 0. Make L2 complementary level.

Although the external selection signal φ is not particularly limited,
It is formed of a PU, and various signals supplied from the CPU to the present semiconductor memory device are changed from a high level to a low level at a predetermined timing set in advance. For example, when the external selection signal φ is at a high level, the input/output control line L1 is set at a high level and the bidirectional latch circuit 2
Only A is activated. Conversely, external selection signal φ
When the input/output control line L2 is at a low level, the input/output control line L2 is set at a high level, and only the bidirectional latch circuit 2B is activated.

Although not shown in the drawings, the semiconductor memory device of this embodiment includes an address buffer circuit, a row decoder circuit, a column decoder circuit, a sense amplifier, and their operation modes, which are normally attached thereto, depending on its characteristics such as RAM or ROM. Other external devices (including a controller that controls based on No. 9).

In the semiconductor memory device configured as described above, in a read cycle, when the upper 8 bits of data are read from the memory array M1 to the bidirectional latch circuit 2A, the external selection signal φ first becomes high level at a preset timing. be done. As a result, only the bidirectional latch circuit 2A is activated, and the upper 8 bits of data are transferred to the data input/output terminal P. to output via P7. Next, when the lower 8-bit data is read from the memory array M2 to the bidirectional latch circuit 2B, only the bidirectional latch circuit 2B is activated by setting the external selection signal φ to a low level at a preset timing. ,
From there, the lower 8 bits of data go to the data input/output terminal P. to output via P7.

In the write cycle, first, the upper 8 bits of data are sent to the data input/output terminal P. External selection signal φ is set to high level at the timing when it is supplied to P7. This results in
Only the bidirectional latch circuit 2A is activated, and the upper 8 bits of data are stored in the memory array MAL through it. Next, the lower 8 bit data is sent to the data input/output terminal P. At the timing when the external selection signal φ is supplied to P7, the external selection signal φ is set to a low level. As a result, only the bidirectional latch circuit 2B is activated, and the lower 8-bit data is stored in the memory array MA2 via it.

In this way, the present semiconductor memory device has the bidirectional latch circuit 2.
Since data can be input/output in a time-division manner by controlling the selection of A and 2B, the number of data input/output terminals can be made smaller than the number of bits of input/output data. Furthermore, since the external selection signal φ is directly used as the control signal for selecting the two-way latch circuit or 2B, internal control signals formed based on external signals such as normal memory read signals and memory write signals can be used. Compared to the case where the data is used, there is no time delay for forming the control signal and there are no timing constraints on the formation of other internal control signals, and high-speed data input/output can be achieved without delay in access time. can.

〔Effect of the invention〕

As is clear from the above explanation, the invention disclosed in this application provides the following effects.

(1) By selectively controlling multiple data latch circuits commonly connected to external terminals, data can be input/output in a time-sharing manner, so the bits of input/output data can be input/output without increasing the number of data input/output terminals. The number can be expanded.

(2) High-speed data input/output can be achieved by directly using an external selection signal as a signal for selectively controlling the data latch circuit.

Although the invention made by the present inventor has been specifically explained based on examples, various changes can be made without departing from the gist thereof.

In the above embodiment, a configuration was explained in which the memory array is divided into two and the attendance data is multiplexed twice, but the configuration is not limited to this, and it is also possible to divide the memory array into more parts and multiplex the data. It is.

Furthermore, although the memory array of the above embodiment inputs and outputs data from all the data lines in parallel, the invention is not limited to this, and the data is input and output through the desired data line selected by the column decoder circuit. It may also be a format for inputting and outputting.

A device capable of inputting and outputting data in a time-division manner, such as in the above embodiment, can be used without time-division by constantly keeping one bidirectional latch circuit in the three-stit state based on an external selection signal. is also possible.

[Application field]

In the above description, the invention made by the present inventor was mainly explained in terms of a semiconductor memory device applicable to a 16-bit microcomputer system, which is the technical field behind the invention, but it is not limited to this, and various other types of devices may be used. It can be used for various semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing one embodiment of the present invention. MAL, MA2...Memory array, 2A, 2B...
Data latch circuit (bidirectional latch circuit), 3... Control means (selection control circuit), φ... External selection signal, PS/
・・External terminal, p, -p, ・・data input/output terminal, L
l. L2...Input/output control line. Figure 1

Claims (1)

[Scope of Claims] 1. A memory array, and a plurality of data latch circuits provided between the memory array and an external terminal to enable mutual data exchange between the external terminal and the memory array; 1. A semiconductor memory device comprising: an external terminal commonly connected to each data latch circuit; and a control means for directly selectively controlling the operation of the data latch circuit using an external selection signal. 2. The semiconductor memory device according to claim 1, wherein the data latch circuit is a bidirectional latch circuit. 3. The above external terminal is used to sequentially input a plurality of divided data constituting one set of data, and the data latch circuit is
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided according to the number of divisions of a set of data.