JPH0279294A - Data length variable memory - Google Patents

Abstract

PURPOSE:To double the bits of data by independently sending address signals to two memory array areas according to a signal to instruct the sending of the data at the number of the bits different from that of the data to be supplied. CONSTITUTION:A signal input terminal, to which a signal SEP to instruct the sending of the data at the number of the bits different from that of the data to be supplies is supplied, and a signal sending circuit 7', which can independently send the signals according to an address signal to two memory array areas 6a and 6b according to the signals SEP supplied from the said signal input terminal, are provided. Thus, when the signals are sent to the both memory array areas 6a and 6b, the number of the bits of the data sent from the memory can be doubled compared with a case in which the signals are sent to either one of the memory array area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data length variable memory that can change the number of bits of data supplied and the number of bits of data sent out.

[Prior Art] In a system that includes a central processing unit (hereinafter abbreviated as CPU) and a peripheral circuit that converts information via the CPU and memory, for example, the data processed by the CPU is
The length of the data used by the CPU and the peripheral circuits may be different, such as the data used by the peripheral circuits being 16 bits. In such a case, for example, as shown in FIG. 3, 8-bit data sent from a CPU that processes 8-bit signals is sent to one latch circuit 2a and 2 via a data bus that exchanges data with the CPU.
8 bits are held in each bit.

The latch circuits 2a and 2b send the data 8 bits at a time to the memory 3 which can store 16 bits of data, and from the memory 3 the data is sent to the peripheral circuit 4 as data consisting of 16 bits.

As another example, as shown in FIG. 4, the data consisting of 8 bits sent from the CPU 1 is sent to the memories 5a and 5 which store the data consisting of 8 bits via the data bus.
8 bits are stored in each bit. and memory 5
The data sent 8 bits each from a and 5b is 1
It is sent to the peripheral circuit 4 as 6-bit data.

If the data length used by the CPU and peripheral circuits is different,
Conventionally, processing has been performed by configuring as described above.

It should be noted that conventional memories that store data consisting of 8 bits or 16 bits as described above usually have memory arrays 6 arranged on the left and right sides for storing data, as shown in FIG. 5, because they can read and write data at high speed. A decoder 7 for converting the supplied address signal into a signal to be sent to the memory array 6 is provided at the center thereof. As shown in FIG. 6, among the address signals, the row address signal is NAN.
The signals supplied to the D circuit 8 and sent out from the NAND circuit 8 are sent out via inverters 9 to word lines 10 extending to the memory arrays 6 provided on the left and right sides, respectively.

[Problems to be Solved by the Invention] However, when using the memory 3 that can store data consisting of 16 bits as described above, the latch circuit 2a
and 2h, and when using memories 5a and 5b that can store 8-bit data, two decoders, etc. for address signals are required, resulting in an increase in the chip area of the integrated circuit. There was a point.

The present invention has been made in order to solve the above-mentioned problems.Even if the data length of the data to be processed differs between the CPU and the peripheral circuits, it is possible to solve the problem without increasing the number of new devices for processing the data. The purpose is to provide a data length changeable memory that can be accessed by circuits.

[Means for Solving the Problems] The present invention includes two memory array areas in which a plurality of memory elements are arranged side by side, and sends a signal according to a seven-dress signal to word lines extending in these memory array areas. a signal input terminal to which a signal instructing to send data with a number of bits different from the number of bits of the supplied data is supplied, and a signal is supplied from the signal input terminal. The present invention is characterized in that it includes a signal escape circuit that can independently send a signal corresponding to an address signal to two memory array areas according to the signal.

[Operation] The signal sending circuit sends out a signal corresponding to the head address signal to one or both of the two memory array areas by the signal supplied from the signal input terminal. Therefore, when a signal is sent to both memory array areas, the number of bits of data sent from the memory is twice as many bits as when a signal is sent to either one of the memory array areas.

[Embodiment] In FIG. 1 showing two embodiments of the present invention, a CPU 1 that processes 8-bit data is connected to a memory 20 in which the data length of the present invention can be changed via a data bus. Send to. The memory 20 sends out the supplied 8-bit data in parallel, for a total of 16 bits.
Bit data is sent to the peripheral circuit 4.

As shown in FIG.
Circuits 21a and 21b and NOR circuits 22a and 22
It is equipped with b. That is, the output side of the NAND circuit 8 to which the row address signal is supplied is the NOR circuit 21a and 21b.
connected to one of the input sides of the NOR circuits 21a and 21
The output sides of b are connected to word lines 10 extending to the left memory array 6a and the right memory array 6b, respectively.

Also, the other input terminal of the NOR circuit 21a has a NOR
The output side of circuit 22a is connected. The NOR circuit 22a is supplied with the SEP signal and the A signal supplied from outside the memory, and the NOR circuit 22a performs a logical operation. N
A NOR circuit 2 is connected to the other input side of the OR circuit 21b.
The output side of 2b is connected. The NOR circuit 22b has SE
The P signal and the A signal are supplied via the inverter 23,
NOR circuit 22b performs a logical operation.

With this configuration, H(
When a high) level SEP signal is supplied, the NOR circuits 22a and 22b output the high level or low (low) level of the A signal.
NOR the L level signal regardless of the level signal state.
The signal is sent to circuits 21a and 21b. Therefore, the signal state of the word line lO extending to the left and right memory arrays 6a and 6b corresponds to the change in the output signal of the NAND circuit 8 to which the row address signal is supplied. Therefore, if the left and right memory arrays 6a and 6b are made up of X bits, the data made up of The signal has twice the number of bits as X bits.

On the other hand, when the SEP signal at the low level is supplied, the NOR circuits 22a and 22b send out signals at different levels depending on the signal state of the A signal, and either the NOR circuit 22a or 22b outputs signals at the low level. Signal to NOR circuit 21
a or 21b.

Therefore, NOR circuit 2 to which the L1 novel signal is supplied
The word line 10 connected to 1a or 21b has a NAN
A signal corresponding to a change in the signal sent out by the D circuit 8 is sent out.

In other words, it is possible to select which of the left and right word lines 10 to operate depending on the signal level of the A signal. Therefore, data consisting of X bits can be supplied to this memory 2o.

By supplying the L level SEP signal from the outside in this way, the memory of the present invention can output an 8-bit signal to, for example, the second row of the left memory array row a specified by the row address. Similarly, the second row is specified by the row address, and the same 8-bit signal is written to the second row. After data is written to the following groups up to the nth row 0, the signal level of the A signal is changed. change the right memory array 6b
Data can be written in the same way sequentially from the first line. Also, the data consisting of 16 bits is stored in the CPU.
, the left and right memory arrays 6a and 6b
The A signal for selecting the 16-bit data is included in 8 bits of the 16-bit data, and for example, the upper 8 bits are for the left memory array 6.
The right memory array 6b is selected by the change in the A signal, and the lower 8 bits are written to the first row, which is the same row as the memory array 6a. In this way, the memory 20 of the present invention can take in data in 8-bit units.

By supplying the H level SEP signal, the memory 20 can send 8 bits of data from both the left and right memory arrays 6a and 6b, a total of 16 bits of data, to the peripheral circuits.

[Effects of the Invention] As detailed above, according to the present invention, when signals are simultaneously sent from the signal sending circuit to two memory array areas, the number of bits of data sent from the memory is equal to that of either one. This is twice the number of bits of the data when the signal is sent to the memory array area. Therefore, for example, in the CPU and peripheral circuits, 1. Even if the data lengths of the data to be processed are different, both can be accessed via the memory of the present invention. Furthermore, since no new device is added, the chip area does not increase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a system using the memory of the present invention, FIG. 2 is a circuit diagram of a row decoder section of the memory of the present invention, and FIGS. FIG. 5 is a block diagram of a circuit using a memory. FIG. 5 is a block diagram showing the configuration of a conventional memory and a memory of the present invention. FIG. 6 is a circuit diagram of a row decoder section of a conventional memory. Death...NAND circuit, 6a and 6b...memory array, IO...word line, 20...memory, 21a and 21b and 22a and 22b-N. 8 circuits, 23...inverters.

Claims (1)

[Claims] (1) Two memory array areas in which multiple memory elements are arranged.
and a row decoder that sends out a signal according to an address signal to word lines extending in these memory array areas, the memory sending out data with a different number of bits from the number of bits of the supplied data. a signal input terminal to which a signal instructing the address signal to be sent is supplied; and a signal sending circuit capable of independently sending signals corresponding to address signals to two memory array areas in accordance with the signals supplied from the signal input terminal. A data length changeable memory characterized by being equipped with.