JPH09218821A - Information processor and its memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit a data signal at high speed by providing plural of data signal lines in which the plural partial data signal lines connected with plural memory modules are integrated and inputting and outputting a data signal to be transmitted by a clock through a data signal line by a clock. SOLUTION: A data signal switching device 411 connects system data signal lines 300 to 331 with data signal lines 5100 to 5131 when a data switching signal line 40 is in a low level and connects the system data signal lines 300 to 331 with data signal lines 5200 to 5231 when the data switching signal line 40 is in a high level. A data signal switching device 421 connects system data signal lines 332 to 363 with data signal lines 5131 to 5163 when the data switching signal line 40 is in the low level and connects the system data signal lines 332 to 363 with data signal lines 5232 to 5263 when the data switching signal line 40 is in the high level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a personal computer, workstation, office computer or the like.

[0002]

2. Description of the Related Art In a memory system that improves the speed of memory access by simultaneously reading and writing a plurality of data, one data is divided into a plurality of multiplexers and input to a multiplexer for switching the plurality of data. The output memory system is the "82350DT EISA Chip Set" P issued by Intel.
504 to P674.

A general configuration of a conventional memory system using a dual inline memory module will be described below with reference to FIG. In the figure, a memory system 60 is a dual inline memory module.
e) A1 to An and B1 to Bn, memory control devices and data signal switching devices 411 and 421, system data signal lines 300 to 363, address signal lines 70 to 79, and RA
S signal lines 811 to 81n and CAS signal lines 821 to 82
n and data signal lines 5200 to 5263.

Dual in-line memory module A1
To An and B1 to Bn are dual inline memory modules (Dual Inline Memories) that constitute the memory system 60.
moryModule), which reads and writes data in units of 64 bits. The row address and the column address are each 10 bits. System data signal line 300
331 is a memory control device and a data signal switching device 411.
The system data signal lines 332 to 363 are connected to the memory control device and the data signal switching device 421. The data signal lines 5100 to 5163 connect the memory modules A1 to An and the data signal switching devices 411 and 421. The data signal lines 5200 to 5263 are connected to the memory modules B1 to Bn and the data signal switching devices 411 and 4 respectively.
21 is connected. The data signal switching device 411 connects the system data signal lines 300 to 331 to the data signal line 5100.
~ 5131 or data signal lines 5200 to 5231. The data signal switching device 421 connects the system data signal lines 332 to 363 to the data signal lines 5132 to 516.
3 or data signal lines 5232 to 5263.
The RAS signal lines 811 to 81n are connected to the memory modules A1 to An and B1 to Bn, respectively, and CAS
The signal lines 821 to 82n are respectively connected to the memory module A.
1-An and B1-Bn. The RAS signal line and the CAS signal line are connected to a total of two memory modules, one memory module A and one memory module B, respectively. Therefore, the memory system 60
Access two memory modules at the same time.
The address signal lines 70 to 79 are connected to the memory modules A1 to A1.
Connected to all of An and B1 to Bn.

As described above, in the memory system 60, the data signal lines 5100 to 5 are connected to the memory modules A1 to An.
163 is connected, data signal lines 5200 to 5263 are connected to the memory modules B1 to Bn, and one RAS signal line and one CAS signal line are connected to the memory module A, respectively.
1, B1 and memory modules A2 and B2 are connected to two memory modules. Therefore, the memory system 60 can read / write two data from / to two memory modules at the same time. However, since the data that can be read and written at one time by the memory control device remains at 64 bits, the memory system 60 uses the data signal switching devices 411 and 421 to determine the connection destination of the system data signal lines 300 to 363 as a data signal. Line 5100-51
63 and the data signal lines 5200 to 5263 are switched to communicate with the memory control device in units of 64 bits.

In the case of reading data from the memory module, the data signal switching device 411 inputs the lower 32 bits of the data output from the memory modules A1 to An from the data signal lines 5100 to 5131 and outputs the system data signal lines 300 to. 331, and then the lower 32 bits of the data output from the memory modules B1 to Bn.
Bits are input from the data signal lines 5200 to 5231 and output to the system data signal lines 300 to 331. Since the data signal switching device 421 also outputs the upper 32 bits of the outputs of the memory modules A1 to An and the upper 32 bits of the outputs of the memory modules B1 to Bn at the same timing, 64 bits are output to the system data signal lines 300 to 363.
The data of t is output twice in succession, and the memory controller reads the data of 64 bits from the memory system 60 for two consecutive times.

In the case of writing data to the memory module, the memory control device uses the system data signal line 300.
The data is continuously output twice to 363. The data signal switching device 411 uses the system data signal lines 300 to 331.
The first data output to the data signal lines 5100-5
131 to the system data signal line 300-
The second data output to 331 is transferred to the data signal line 520.
It outputs to 0-5231. The data signal switching device 421 also has the same timing as the system data signal lines 332 to 363.
Data input from the data signal lines 5132 to 5163
And 5232 to 5263 are output. In this way A1
The first data output from the memory control device is written in to An, and the second data is written in B1 to Bn.
Memory modules A1 to An and memory modules B1 to
A group of memory modules connected to the same data signal line like Bn is called a way in this specification. The memory system 60 has two ways of memory modules A1 to An and memory modules B1 to Bn.

FIG. 23 shows a general layout of the above memory system. The memories A1 to An are arranged in a line on the substrate, and the memories B1 to Bn are arranged in a line in parallel with the columns A1 to An on the same surface of the same substrate. The data signal switching devices 411 and 421 are arranged near the memories A1 and B1.

[0009]

The problems to be solved by the invention will be described below with reference to FIGS.
Problems to be solved by the memory system according to the present invention will be described with reference to FIGS. In the memory system 60 described above, as shown in FIG.
1, 421 are connected to both the memory modules A1 to An and the memory modules B1 to Bn. FIG.
Memory modules A1 to An and B1 to Bn
Memory modules A1 and B1, A2 and B perpendicular to the columns of
2, ..., An and Bn are arranged in a line. Therefore, in order to reduce the delay of the data signal, the data signal switching device 4
11 is arranged in the vicinity of the memory modules A1 to An and the data signal lines 5100 to 5131 are shortened, the wiring length of the data signal lines 5200 to 5231 is extended, and the data signal switching device 411 is arranged in the vicinity of the memory modules B1 to Bn. If the data signal lines 5200 to 5231 are shortened,
The wiring length of the data signal lines 5100 to 5131 extends. The data signal switching device 421 is also a memory module A1 to A
Since it is connected to both n and B1 to Bn, there is a similar problem. Therefore, in the memory system 60, it is difficult to shorten the data signal line. Further, unless the data signal switching devices 411 and 421 are arranged in the middle of the memory modules A1 to An and B1 to Bn, the data signal lines 5100 to 5131 are the data signal lines 5200 to 52.
The length of 31 is different, and the data signal lines 5232 to 5163 are different.
Since the lengths of the data signal lines 5132 to 5163 are different from each other, the timing of the data signal varies and causes a malfunction. Actually, the data signal switching device 411,
421 simultaneously with the memory modules A1 to An and B1 to B
Since it is impossible to dispose it in the middle of n, it is difficult for the memory system 60 to eliminate the variation in the timing of the data signal.

In order to solve the above problem, a method of arranging a data signal switching device and a memory module as shown in FIG. 24 has been proposed. In this arrangement, the memory system 62 has the same connection of signal lines other than the data signal line as the memory system 60, and the memory module and the data signal switching device are also the same as the memory system 60.
However, by connecting the data signal lines 5100 to 5131 and the data signal lines 5200 to 5231 to the memory modules A1 to An, and connecting the data signal lines 5132 to 5163 and the data signal lines 5232 to 5263 to the memory modules B1 to Bn, A memory area of the lower 32 bits of the first way and a memory area of the lower 32 bits of the second way are arranged in the memory modules A1 to An, and a memory area of the upper 32 bits of the first way and the second memory area are arranged in the memory modules B1 to Bn. The storage area of the upper 32 bits of the way is placed.

As a result, the memory modules A1 to An are
Only the data signal switching device 411 is connected to the data signal line 510. By bringing the data signal switching device 411 close to the memory modules A1 to An, the data signal line 510
0-5131 and the data signal lines 5200-5231 can be shortened at the same time. The data signal switching device 421 is connected to the memory modules B1 to Bn.
Since only the memory modules B1 to Bn are brought close to the data signal switching device 421, the data signal line 5132
˜5163 and data signal lines 5232-5263 can be shortened at the same time. In addition, the memory module A
1 to An and the memory modules B1 to Bn are arranged apart from each other, the data signal lines 5100 to 5163 and the data signal lines 5
It is possible to make the wiring lengths of 200 to 5263 equal. Further, by arranging the memory modules A1 to An and the memory modules B1 to Bn apart from each other, the wiring positions of the data signal lines are dispersed, and the wiring of the data signal lines can be performed by using less wiring layers. Substrate manufacturing costs are low. As described above, the memory system 62 is low in the manufacturing cost of the board, has a small delay of the data signal, and at the same time can avoid the variation in the timing of the data signal.
It is possible to provide an information processing device having

FIG. 25 shows a memory system 6 shown in FIG.
The wiring of the memory module of No. 2 is not changed, the memory module and the data signal switching device are arranged in the row of the memory modules A1 to An and the data signal switching device 411, and the memory modules B1 to Bn and the data are arranged on the back side. The signal switching devices 421 are arranged in a line.

The data signal switching device 4 is arranged on a line perpendicular to the substrate.
11 and 421, memory modules A1 and B1, A2 and B
2, ..., An and Bn are arranged in a line. As a result, the data signal switching device 411 is connected to the memory module A.
1 and B1 can be arranged near both of them, and the signal switching device 421 can be arranged near both of the memory modules A1 and B1. Further, the distances from both the memory modules A1 and B1 to the data signal switching device 411 are equal, and the distances from both the memory modules A1 and B1 to the data signal switching device 421 are also equal. Furthermore, since the memory module is placed on the back and front of the board,
The space required for arranging memory modules is reduced. As described above, the wiring lengths of the data signal lines 5100 to 5163 and the data signal lines 5200 to 5263 are shortened, and the timing delay of the data signal is reduced, so that the data signal lines 5100 to 5163 and the data signal lines 5200 to 5263 are reduced.
The inventor has proposed an information processing device having a memory system in which the wiring lengths of the memory cells are the same, the variation in the timing of the data signal is small, and the board space required for arranging the memory module is small, and the manufacturing cost of the board is low. .

[0014]

According to an embodiment of the present invention, 32 upper partial system data signal lines and a lower level system data signal line respectively connecting a first and a second data signal switching device to a memory control device are provided. Partial system data signal line,
It has a system data signal line composed of the upper part system data signal line and the lower part system data signal line, and has a storage area of 64 bits for each address, and they are arranged in a straight line at equal intervals on the same surface of the substrate. An n-th (n is an arbitrary positive integer) first memory module and a n-th second memory module having a 64-bit storage area for each address and arranged side by side at the same interval as the first memory module. A memory module; a first lower data signal line connecting the first data signal switching device to the first memory module; a second lower data signal line connecting the first data signal switching device to the first memory module; A first upper data signal line connecting the data signal switching device with the second memory module, and a first upper data signal line connecting the second data signal switching device with the second memory module A first data signal switching device that connects the upper data signal line and the lower partial system data signal line to the first lower data signal line or the second lower data signal line and is arranged on an extension line of the column of the first memory module; A second data signal switching device that connects the higher system data signal line to the first higher data signal line or the second higher data signal line and is arranged on an extension line of the column of the second memory module, and a second data signal switching device, respectively. N memory banks each including one memory module and one second memory module, a first way including first and second memory modules, and first and second memory modules Second way, address signal lines connected to all memory modules, write signal lines connected to all memory modules, and memory banks. N RAS signal lines connected to the first memory module and the second memory module, and n CAS signal lines connected to the first memory module and the second memory module of each memory bank. And a data switching signal for controlling the data signal switching device, wherein the distance between the second data signal switching device and the second memory module closest to the second data signal switching device is the first data signal switching device. There is provided an information processing device and a memory system in which the distance between the first memory module and the first memory module closest to the first data signal switching device is made equal.

According to an embodiment of the present invention, 32 upper partial system data signal lines and 32 lower partial system data signal lines respectively connecting the first and second data signal switching devices with the memory control device are provided. , A system data signal line composed of the upper part system data signal line and the lower part system data signal line, and k (k is an arbitrary positive integer) storage area of 64 bits for each address, etc. N first (n is a positive integer where n = 2k) firsts arranged on the same surface of the substrate arranged in line at intervals
A column of the second memory module, which has a memory module and a storage area of 64 bits for each address, is arranged in a line with k number of the first memory modules and arranged in a straight line, and each of which includes k second memory modules The second data signal switching device is connected to the n second memory modules and the first data signal switching device is arranged such that the distance between them is equal to the distance between the columns of the first memory module each including k first memory modules. A first lower data signal line, a second lower data signal line connecting the first data signal switching device to the first memory module, and a first upper data signal connecting the second data signal switching device to the second memory module Line, a second upper data signal line connecting the second data signal switching device with the second memory module, and a lower partial system data A first data signal switch arranged on a column of the first memory module between two columns of the first memory modules which are connected to the first lower data signal line or the second lower data signal line and are arranged in k rows. The device and the upper partial system data signal line connected to the first upper data signal line or the second upper data signal line, and between the two columns of the second memory modules arranged in k rows on the column of the second memory module. A second data signal switching device to be arranged, n first memory modules, and n memory banks each composed of a second memory module;
First way composed of the memory modules, a second way composed of the first and second memory modules, an address signal line connected to all the memory modules, and a connection to all the memory modules Write signal lines, n RAS signal lines connected to the first memory module and the second memory module of each memory bank, and the first memory module and the second memory module of each memory bank. N CAS signal lines connected,
A data switching signal for controlling the data signal switching device, and a distance between the second data signal switching device and the second memory module closest to the second data signal switching device is equal to the first data signal switching device. There is provided an information processing device and a memory system in which the distance to the first memory module closest to the first data signal switching device is made equal.

According to one embodiment of the present invention, 16 first partial system data signal lines each connecting the first, second, third and fourth data signal switching devices with the memory control device. And a second partial system data signal line, a third partial system data signal line, and a fourth partial system data signal line, and a system data signal line composed of the first, second, third, and fourth partial system data signal lines, Each of the n and n (n is an arbitrary positive integer) first and third memory modules having a 64-bit storage area for each address and arranged alternately at equal intervals, and a 64-bit storage area for each address And n second and fourth memory modules, which are alternately arranged in a row at the same intervals as the first and third memory modules, and all the first memory modules and the first memory module. A first memory group including all the memory modules, a second memory group including all the second memory modules and all the fourth memory modules, and a first data signal switching device including the first memory module. An eleventh data signal line connected to the first data signal switching device, a twelfth data signal line connecting the first data signal switching device to the first memory module, and a thirteenth data signal line connecting the first data signal switching device to the third memory module A fourteenth data signal line connecting the first data signal switching device to the third memory module, a twenty-first data signal line connecting the second data signal switching device to the first memory module, and a second data signal switching device Connecting the first memory module with the 22nd
A data signal line, a 23rd data signal line connecting the second data signal switching device to the third memory module, and a second connecting the second data signal switching device to the third memory module
Four data signal lines, a thirty-first data signal line connecting the third data signal switching device to the second memory module, a thirty-second data signal line connecting the third data signal switching device to the second memory module, and a third data signal line A 33rd data signal line for connecting the data signal switching device to the 4th memory module;
The 34th data signal line connecting the data signal switching device to the fourth memory module, and the fourth data signal switching device to the second
Forty-first data signal line connected to the memory module, 42nd data signal line connecting the fourth data signal switching device to the second memory module, and 43rd data connecting the fourth data signal switching device to the fourth memory module Signal line,
The 44th data signal line connecting the fourth data signal switching device to the fourth memory module, and the first partial system data signal line are connected to any one of the 11th, 12th, 13th, and 14th data signal lines. A first data signal switching device arranged on an extension line of a column of memory modules and a second partial system data signal line are connected to any of the 21, 22, 23, and 24 data signal lines to provide first, third memory modules. Of the second data signal switching device and the third partial system data signal line arranged on the extension line of the column
A third data signal switching device connected to one of the four data signal lines and arranged on an extension line of the columns of the second and fourth memory modules, and a fourth partial system data signal line to the 41st and 4th system data signal lines.
2, 43, 44 connected to any of the data signal lines,
A fourth data signal switching device arranged on an extension of a column of four memory modules, n memory banks each composed of one first, second, third, and fourth memory module, and a first data signal switching device, , 2, 3, 4, a first way composed of memory modules, a second way composed of first, second, third, fourth memory modules, first, second,
A third way composed of 3, 4 memory modules, a fourth way composed of 1, 2, 3, 4 memory modules, and an address signal line connected to all the memory modules, Write signal lines connected to all memory modules, n RAS signal lines connected to the first to fourth memory modules of each memory bank, and first to fourth memory modules of each memory bank. It is composed of n CAS signal lines connected to each other and a data switching signal line for controlling the data signal switching device, and the second data signal switching device and the first and third data signals closest to the second data signal switching device.
Of the first data signal switching device and the first and third memory modules closest to the first data signal switching device, and the third data signal switching device and the third data signal switching device. The distance between the second and fourth memory modules closest to the data signal switching device is made equal to the distance between the first data signal switching device and the first and third memory modules closest to the first data signal switching device. , 4th
The distance between the data signal switching device and the second and fourth memory modules closest to the fourth data signal switching device is the first data signal switching device and the first and third memory modules closest to the first data signal switching device. Provided is an information processing device and a memory system whose distance from a memory module is made equal.

According to one embodiment of the present invention, 16 first partial system data signal lines each connecting the first, second, third and fourth data signal switching devices with the memory control device. And a second partial system data signal line, a third partial system data signal line, and a fourth partial system data signal line, and a system data signal line composed of the first, second, third, and fourth partial system data signal lines, N first (n is an arbitrary positive integer) first array having a 64-bit storage area for each address and arranged in a row at equal intervals
A memory module, n third memory modules having a storage area of 64 bits for each address and arranged in a row at an equal interval with the first memory module on an extension line of the row of the first memory module, and for each address N second memory modules having a 64-bit storage area and arranged in a row at the same intervals as the first memory module, and a second memory module having a 64-bit storage area for each address and equally spaced from the first memory module N fourth memory modules arranged in a line on the extension of the column, a first memory group composed of all the first memory modules and all the third memory modules, and all second memory modules And a second memory module consisting of all the fourth memory modules
Memory group, an eleventh data signal line connecting the first data signal switching device to the first memory module, and a twelfth data signal switching device connecting to the first memory module.
A data signal line, a thirteenth data signal line connecting the first data signal switching device to the third memory module, and a first data signal switching device connecting the first data signal switching device to the third memory module
Four data signal lines, a twenty-first data signal line connecting the second data signal switching device to the first memory module, a twenty-second data signal line connecting the second data signal switching device to the first memory module, and a second data signal line A twenty-third data signal line connecting the data signal switching device with the third memory module;
The 24th data signal line connecting the data signal switching device to the third memory module, and the third data signal switching device to the second
A 31st data signal line connecting to the memory module, a 32nd data signal line connecting the third data signal switching device to the second memory module, and a 33rd data connecting the third data signal switching device to the 4th memory module Signal line,
The 34th data signal line connecting the third data signal switching device to the fourth memory module, the 41st data signal line connecting the fourth data signal switching device to the second memory module, and the 4th data signal switching device A 42nd data signal line connected to the 2nd memory module, a 43rd data signal line connecting the 4th data signal switching device to the 4th memory module, and a 44th data signal line connected to the 4th memory module The data signal line and the first partial system data signal line are connected to any of the 11, 12, 13, and 14 data signal lines, and the columns of the first and third memory modules are arranged on the extension lines of the columns of the first and third memory modules. The first data signal switching device arranged between the first and second data signal lines and the second partial system data signal line are connected to one of the 21, 22, 23, and 24 data signal lines. The second data signal switching device arranged between the columns of the first and third memory modules on the extension line of the columns of the memory modules, and the third partial system data signal lines as the 31, 32, 33, 34 data signal lines. A third data signal switching device which is connected to any one of the above and is arranged between the columns of the second and fourth memory modules on the extension line of the columns of the second and fourth memory modules, and the fourth partial system data signal line. 41, 42, 43, 44 connected to any one of the data signal lines and connected to any one of the second and fourth memory module columns on the extension line of the second and fourth memory modules.
A fourth data signal switching device arranged between columns of four memory modules, n memory banks each composed of one first, second, third and fourth memory module respectively, A first way composed of 2, 3, 4 memory modules, a second way composed of 1, 2, 3, 4 memory modules, and 1, 2, 3, 4 memory modules And a fourth way composed of the first, second, third, and fourth memory modules.
Way, address signal lines connected to all memory modules, write signal lines connected to all memory modules, and n RAS connected to the first to fourth memory modules of each memory bank. N connected to the signal line and the first to fourth memory modules of each memory bank
Distance between the second data signal switching device and the first and third memory modules closest to the second data signal switching device. The distance is between the second data signal switching device and the second data signal switching device. Is equal to the distance between the first data signal switching device and the first and third memory modules closest to the first data signal switching device, and the distance between the third data signal switching device and the third data signal switching device is the most. The distance between the second and fourth memory modules, which are close to each other, is made equal to the distance between the first data signal switching device and the first and third memory modules closest to the first data signal switching device. The distance between the switching device and the second and fourth memory modules closest to the fourth data signal switching device is the first data signal switching device and the first and third memory modules closest to the first data signal switching device. The information processing apparatus and a memory system is equal to the distance between Le is provided.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The configuration of a computer system according to all the embodiments of the present invention described below is as shown in FIG. FIG. 1 is a schematic diagram of the configuration of a computer system according to an embodiment of the present invention. The system according to the present invention comprises a central processing unit S1, an input / output control device S2, a memory control device S3, a memory system S4, and input / output devices SD1 to SDx such as an external storage device, a display device and a keyboard. It The central processing unit S1 reads / writes data from / to the memory system S4 via the memory control unit S3, and inputs / outputs to / from the input / output units SD1 to SDx (x is an arbitrary integer of 0 or more) via the input / output control unit S2. I do. The input / output control device S2 controls the input / output devices SD1 to SDx, the memory control device S3, and the like according to an instruction from the central processing unit S1. The input / output devices SD1 to SDx read / write data from / to the memory system S4 via the input / output control device S2 and the memory control device S3. The memory control device S3 reads / writes data from / to the memory system S4 in accordance with instructions from the central processing unit S1 and the input / output control device S2. The input / output devices SD1 to SDx include an external storage device, a display device,
There are key input devices. The central processing unit S1 and the input / output control unit S2 are connected by a bus SB1. Central processing unit S
1 and the memory control device S3 are connected by a bus SB2. The input / output control device S2 and the memory control device S3 are connected by a bus SB3. Input / output control device S2 and input / output devices SD1 to SD1
SDx is connected by a bus SB4. Memory control device S3
The memory system S4 and the memory system S4 are connected by a bus SB5.

A first embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a configuration diagram of the memory system S4 according to the first embodiment of the present invention. In FIG. 2, memory modules E1 to E of the memory system S4 according to the first embodiment of the present invention are shown.
For n, F1 to Fn (n is any integer of 1 or more), Du
al Inline Memory Module (hereinafter referred to as DIMM) and Single Inline
Memory Module (hereafter called SIMM)
Use

Memory modules E1 to En, F1 to Fn
Have m + 1 storage areas (m is an integer of 1 or more), and the size of each storage area is 64 bits. S with a data length of 32 bits in the memory module
When using the IMM, the upper 32 bits and the lower 32 bits of the storage area of one memory module are different SIMMs.
Assign one by one.

The system data signal lines 300 to 363 are
Connecting the memory system S4 with the memory controller S3 6
It is composed of four data lines. The memory control device S3 is
Data is exchanged with the memory system S4 via the system data signal lines 300 to 363. The system data signal lines 300 to 331 are connected to the data signal switching device 41.
1 and connected to the system data signal lines 332 to 363.
Are connected to the data signal switching device 421. The data signal lines 5100 to 5163 form a first way of the memory system S4, and the data signal lines 5200 to 5263 form a second way of the memory system S4. The memory system of the embodiment of the first invention has two ways. The data signal lines 5100 to 5131 connect the data signal switching device 411 and the lower 32 bits of the storage areas of the memory modules E1 to En, and the data signal lines 5200 to 5131 are connected.
231 connects the data signal switching device 411 and the upper 32 bits of the storage areas of the memory modules E1 to En, and the data signal lines 5132 to 5163 connect the data signal switching device 4 to the data signal lines 5132 to 5163.
21 and lower three storage areas of the memory modules F1 to Fn
2 bit is connected, and data signal lines 5232 to 5263 are connected.
Is a data signal switching device 421 and a memory module F1.
Connect the upper 32 bits of the storage area of ~ Fn.

The data switching signal line 40 is connected to the data signal switching devices 411 and 421 and controlled by the memory control device S3.

The data signal switching device 411 is a device for switching the data signal of the memory system S4 according to the present invention. When the data switching signal line 40 is at the low level, the system data signal lines 300 to 331 are connected to the data signal line 510.
When the data switching signal line 40 is at a high level, the system data signal lines 300 to 331 are connected to the data signal lines 5200 to 5231.

The data signal switching device 421 is a device for switching the data signal of the memory system S4 according to the present invention.
2 to 5163 and the data switching signal line 40 is at a high level, the system data signal lines 332 to 363 are connected to the data signal lines 5232 to 5263.

The data signal switching devices 411 and 421 have data signal lines 5100 to 5163 and a data signal line 5200.
Input / output to ~ 5263 is always performed simultaneously.

The RAS signal lines 811 to 81n are connected to the memory modules E1 to En and F1 to Fn. CAS
The signal lines 821 to 82n are connected to the memory modules E1 to En.
And F1 to Fn. The RAS signal line and the CAS signal line are controlled by the memory control device S3. The RAS signal line 811 and the CAS signal line 821 are connected to the memory modules E1 and F1. Similarly, for any positive integer i less than or equal to n, the memory modules Ei and Fi have RAS
The signal line 81i and the CAS 82i are connected.

The address signal lines 70 to 79 are connected to all the memory modules E1 to En and F1 to Fn. The memory control device S3 divides the address of the storage area to be accessed into upper 10 bits and lower 10 bits, and outputs the addresses to the address signal lines 70 to 79. Memory controller S
3 sets the RAS signal line to the low level when outputting the upper address to the address signal lines 70 to 79, and sets the CAS signal line to the low level when outputting the lower address to the address signal lines 70 to 79.

The write signal line 83 is connected to the memory module E.
1 to En and F1 to Fn, and is controlled by the memory control device S3. Memory control device S3
Is the write signal line 8 when writing data to the memory system S4 of the first embodiment of the present invention.
When setting 3 to low level and reading data,
The write signal line 83 is set to high level.

FIG. 3 is a diagram of storage areas of the memory modules E1 and F1 of the memory system S4 according to the first embodiment of the present invention. The areas E101 to E1m1 are the lower 32bi of the storage areas 0 to m of the memory module E1.
represents t. Areas E102 to E1m2 represent the upper 32 bits of the storage areas 0 to m of the memory module E1.
Areas F101 to F1m1 represent the lower 32 bits of the storage areas 0 to m of the memory module F1. Area F10
2 to F1m2 are storage areas 0 of the memory module F1
It represents the upper 32 bits of the address m. Memory module E2
To En and F2 to Fn have the same configuration.

FIG. 4 is a diagram showing correspondence between storage areas and ways according to the first embodiment of the present invention. The memory banks 11 to 1n are respectively composed of memory modules Ey and Fy for an arbitrary integer y of n or less, and the memory modules Ey and Fy have the same R.
The AS signal line and the CAS signal line are connected. As shown in FIG. 4, the data signal line of the data signal switching device 411 is connected only to the memory modules E1 to En, and the data signal line of the data signal switching device 421 is the memory module F1.
To Fn only.

FIG. 5 is a diagram showing a logical configuration of ways of the memory bank 11 of the memory system S4 according to the first embodiment of the present invention. The first way 91 is the first
2 is a way for the bank 11 according to the embodiment of the present invention. Each storage area of the first way 91 is 64b
It has a size of it and is composed of the lower 32 bits of the storage area of the memory module E1 and the lower 32 bits of the storage area of the memory module F1. The way 91 becomes a storage area of the banks 11 at addresses 0, 2, ..., 2 m.

The second way 92 is a way for the bank 11 according to the first embodiment of the present invention. Each storage area of the second way 92 has a size of 64 bits, and the upper 32 bits of the storage area of the memory module E1.
And the upper 32 bits of the storage area of the memory module F1. The way 92 serves as a storage area for the addresses 1, 3, ..., 2m + 1 of the bank 11. The logical configuration of ways of the memory banks 12 to 1n is also the memory bank 11.
It has the same configuration as.

FIG. 6, FIG. 7 and FIG. 8 are layout diagrams of the memory system according to the first embodiment of the present invention. The following description is common to FIGS. 6 to 8 unless otherwise specified. The data signal switching device 411 and the memory modules E1 to En include the data signal switching device 411 and the memory modules E1, E2.
, En are arranged in a row in this order (hereinafter, this row is referred to as an E row), and the memory modules E1, E2, ..., En are arranged at equal intervals. Similarly, the data signal switching device 421 and the memory modules F1 to Fn are connected to the data signal switching device 42.
1. The memory modules F1, F2, ..., Fn are arranged in a row in order (hereinafter, this row is referred to as an F row), and the memory modules F1, F2 ,. It is assumed that the distance from the memory module Ey to the data signal switching device 411 is equal to the distance from the memory module Fy to the data signal switching device 421 for any positive integer y equal to or smaller than n. The memory modules E1 to En are arranged such that the substrate surface of the memory modules E1 to En (hereinafter referred to as the first surface) is perpendicular to the E column. Memory modules F1 to F
n is arranged such that the first surface of the memory modules F1 to Fn is perpendicular to the F column. The data signal switching device 411 is arranged in the vicinity of the memory module E1 on a straight line connecting the centers of the first surfaces of the memory modules E1 to En. Memory modules F1 to F near the memory module F1
The data signal switching device 4 is arranged on a straight line connecting the centers of the first surfaces of n.
21 is arranged.

As shown in FIG. 4, the data signal lines from the data signal switching device 411 are connected to the memory modules E1 to E.
n, and the data signal line from the data signal switching device 421 is connected only to the memory modules F1 to Fn. Therefore, when the data signal switching device 411 is arranged near the memory module E1 as shown in FIGS. 6 to 8, the length of the data signal line connected to the memory in the E column is shortened. The same effect can be obtained by disposing the data signal switching device 421 near the memory module F1. In this way, it is possible to reduce the timing delay of the data signal and realize a high-speed memory system.

Further, according to the connection method, the distance from the memory module Ey to the data signal switching device 411 is set to the memory module F for an arbitrary positive integer y of n or less.
When it is equal to the distance of the data signal switching device 421 from y,
The data signal line length from the memory module Ey to the data signal switching device 411 is equal to the data signal line length from the memory module Fy to the data signal switching device 421. Since the memory module Ey and the memory module Fy are memory modules that are accessed at the same time, variations in timing at the time of data access are reduced, and a high-speed memory system can be realized.

Further, since the data signal line between the E column and the F column is eliminated by the connection method, the E column and the F column are shown in FIG.
7 and the columns E and F are separated from each other on the same substrate surface of the memory system S4 as shown in FIG.
By arranging the data signal lines in series on the same substrate surface, it is possible to disperse the data signal lines, reduce the wiring layers for the data signal lines, and reduce the manufacturing cost of the substrate of the memory system S4. Further, the E column and the F column are arranged on different substrate surfaces as shown in FIG. 8, and the memory modules Ey and Fy are S
4 is arranged on a line vertical to the board surface, and the data signal switching device 411 and the data signal switching device 412 are also arranged on a line vertical to the board surface S4, the memory system S4 can be arranged in a small range. And memory system S4
It is possible to reduce the manufacturing cost of the substrate.

The storage system of the first embodiment of the present invention will be described below with reference to FIGS. Address 0 (memory area of way 91) and address 1 (way 92) of bank 11 of memory system S4 according to the first embodiment of the invention.
Access to the storage area) is performed simultaneously. As shown in FIG. 4, the data signal lines 5100 to 5131 are connected to the storage area memory modules E101 to E1m1 and the data signal lines 5132 to 5163 are connected to the storage area memory module F.
102 to F1m2, the lower 32 bits of the data of the way 91 are written to the storage area memory module E101 and the upper 32 bits are connected, as shown in FIG.
Is written in the storage area F101. Similarly, way 9
The lower 32 bits of the second data are written in the storage area E102, and the upper 32 bits are written in the storage area F102. Data is stored in other memories in the same manner.

The operation of the first embodiment of the present invention will be described below with reference to FIG. When writing data to the ways 91 and 92 of the bank 11 of the memory system S4, the memory control device S3 first sets the write signal line 83 to the low level. Subsequently, the memory control device S3 sets the data switching signal line 40 to the low level, outputs the data for the way 91 to the system data signal lines 300 to 363, and subsequently sets the data switching signal line 40 to the high level.
The data for the way 92 is output to the system data signal lines 300 to 363. Further, the memory control device S3
Is the upper 10b of the address of the storage area to which the data is written
After outputting it to the address signal lines 70 to 79, RAS
The signal line 811 is set to low level, and the memory module E1
Then, the memory module F1 is made to read the upper 10 bits of the address. Subsequently, the memory control device S3 outputs the lower 10 bits of the address to the address signal lines 70 to 79, sets the CAS signal line 821 to the low level, and reads the lower 10 bits of the address into the memory module memory module E1 and the memory module F1. Let

The data signal switching device 411 has a way 91
Lower 32 bits of the data of line 92 and lower 32 bits of the data of way 92 are respectively set to data signal lines 5100 to 513.
1, 5200 to 5231. At the same time, the data signal switching device 421 determines the upper 32 b of the data of the way 91.
It and the upper 32 bits of the data of way 92 are respectively data signal lines 5132 to 5163, 5232 to 5263.
Output to The memory module E1 has a data signal line 5
The data output to 100-5131 and 5200-5231 is recorded, and the memory module F1 records the data output to the data signal lines 5132-5163, 5232-5263.

When reading data from the bank 11 of the memory system S4, first, the memory control device S3 sets the write signal line 83 to the high level. Next, the memory control device S3 outputs the upper 10 bits of the address of the storage area for accessing the address signal lines 70 to 79, and then outputs RA
The S signal line 811 is set to low level, and the upper 10 bits of the address are stored in the memory module E1 and the memory module F1.
Read t. Subsequently, the memory control device S3 outputs the lower 10 bits of the address to the address signal lines 70 to 79, and then sets the CAS signal line 821 to the low level to cause the memory module E1 and the memory module F1 to read the lower 10 bits of the address. Memory module E
1 is data signal lines 5100-5
131, 5200 to 5232, and the memory module F1 outputs the data of the address to the data signal line 5132.
To 5163, 5232 to 5263.

When the memory control device S3 sets the data signal switching line 40 to the low level, the data signal switching device 411.
Outputs the data read from the data signal lines 5100 to 5131 to the system data signal lines 300 to 331,
The data signal switching device 421 uses the data signal lines 5132-5
The data read from 163 is output to the system data signal lines 332 to 363. Then, the memory control device S
3 sets the data signal switching line 40 to the high level, the data signal switching device 411 determines that the data signal lines 5200 to 5231.
The data read from the system data signal line 300
To 331 to output the data signal data signal switching device 42
1 outputs the data read from the data signal lines 5232 to 5263 to the system data signal lines 332 to 363.

A second embodiment of the present invention will be described below with reference to FIGS. 1 to 5 and 9 to 11. The embodiment of the second invention is a modification of only the arrangement of the memory module and the data signal data signal switching device of the memory system S4 of the embodiment of the first invention. Therefore, in the embodiment of the present invention, only the arrangement of the memory modules of the memory system S4 will be described.

9 to 11 are diagrams showing the arrangement of the memory system according to the second embodiment of the present invention. The following description is common to FIGS. 9 to 11 unless otherwise noted. Memory modules E1 to Ek (k is a positive integer such that 2 × k = n)
, Ek are arranged in one row in the order of memory modules E1, E2, ..., Ek (this row is called the memory module E1 row) at equal intervals. The memory modules Ek + 1 to En are arranged at regular intervals in one row (referred to as the E2 row) in the order of the memory modules Ek + 1, Ek + 2, ..., En. The memory modules F1 to Fk are the memory modules F1 and F
2, ..., Fk are arranged in one line (this line is called F1 line) at equal intervals. Memory modules Fk + 1 to Fn
Are arranged in one row in the order of Fk + 1, Fk + 2, ..., Fn (this row is called the F2 row) at equal intervals. The memory modules E1 row and E2 row are arranged in a row with the data signal switching device 411 interposed therebetween. The F1 row and the F2 row are arranged in one row with the data signal switching device 421 interposed therebetween.

The distance from each of the memory modules Ey and Ek + y to the data signal switching device 411 is equal to an arbitrary positive integer y of k or less, and each of the memory modules Fy and Fy + 1 to the data signal switching device 421. Is also equal to. Memory module E
1 to En are memory modules E1 to En whose substrate surface is E.
Arrange them so that they are perpendicular to the first and second columns. The memory modules F1 to Fn are arranged such that the first surfaces of the memory modules F1 to Fn are perpendicular to the columns F1 and F2. The data signal switching device 411 is arranged in the vicinity of the memory module E1 on a straight line connecting the centers of the first surfaces of the memory modules E1 to En. The data signal switching device 421 is arranged in the vicinity of the memory module F1 on a straight line connecting the centers of the first surfaces of the memory modules F1 to Fn.

As shown in FIG. 4, the data signal lines from the data signal switching device 411 are connected to the memory modules E1 to E1.
The data signal line from the data signal switching device 421 is connected only to En and is connected only to the memory modules F1 to Fn. Therefore, when the data signal switching device 411 is arranged near the memory modules E1 and Ek as shown in FIGS. 9 to 11, the length of the data signal line connected to the memory in the E column is shortened. The same effect can be obtained by disposing the data signal switching device 421 near the memory modules F1 and Fk. In this way, it is possible to reduce the timing delay of the data signal and realize a high-speed memory system.

Further, according to the connection method, the distance from the memory module Ey to the data signal switching device 411 is set to the memory module F for any positive integer y of n or less.
When the distance from y to the data signal switching device 421 is equal to the distance from the memory module Ey to the data signal switching device 41.
The data signal line length to 1 becomes equal to the data signal line length from the memory module Fy to the data signal switching device 421. Since the memory module Ey and the memory module Fy are memory modules that are accessed at the same time, variations in timing at the time of data access are reduced, and a high-speed memory system can be realized.

Further, the data signal switching device 411 is set to E1.
By arranging it between the column and the E2 column, the maximum length of the data signal line from the data signal switching device 411 is half that of the first embodiment of the invention. Similarly, the data signal switching device 4
The maximum length of the data signal line from 21 is also half that of the first embodiment of the invention. As a result, the delay in the timing of data access is reduced, and a high-speed memory system can be realized.

Further, since the data signal line between the E column and the F column is eliminated by the connection method, the E column and the F column are shown in FIG.
As shown in FIG. 10, the columns E and F are arranged separately from each other on the same substrate surface of the memory system S4 as shown in FIG.
4 are arranged in series on the same substrate surface, the data signal lines can be dispersed, the wiring layer for the data signal lines can be reduced, and the manufacturing cost of the substrate of the memory system S4 can be reduced. Further, the row E and the row F are arranged on different board surfaces as shown in FIG. 11, and the memory module Ey and the memory module Fy are arranged on a line perpendicular to the board surface of S4 with respect to an arbitrary positive integer y of n or less. If the data signal switching devices 411 and 412 are also arranged on a line perpendicular to the substrate surface of the memory system S4, it is possible to arrange the memory system S4 in a small area, and the manufacturing cost of the substrate of the memory system S4 is reduced. It can be lowered.

The third embodiment of the present invention will be described below with reference to FIGS. 1 and 12 to 18. FIG. 12 is a configuration diagram of the memory system S4 according to the third embodiment of the present invention. In FIG. 12, memory modules A1 to An, B1 to Bn, C1 to Cn, D1 to Dn of the memory system S4 according to the third embodiment of the present invention.
(N is an arbitrary integer of 1 or more) includes Dual Inli
ne Memory Module (hereinafter referred to as DIMM) and Single Inline MemoryM
The module (hereinafter referred to as SIMM) is used. Memory modules E1 to En, memory modules F1 to Fn
Have m + 1 storage areas (m is an integer of 1 or more), and the size of each storage area is 64 bits.
SIM with data length of 32 bits in memory module
When M is used, another S is assigned to each of upper 32 bits and lower 32 bits of the storage area of one memory module.
Assign IMMs one by one.

The system data signal lines 300 to 363 are
Memory system S4 and memory controller S3 according to the present invention
It is composed of 64 signal lines that connect to each other. The memory control device S3 uses the system data signal lines 300 to 363 to exchange data with the memory system S4 of the embodiment of the third invention. System data signal line 30
0 to 315 are connected to the data signal switching device 411, system data signal lines 316 to 331 are connected to the data signal switching device 412, and system data signal lines 332 to 3
47 is connected to the data signal switching device 421, and the system data signal lines 348 to 363 are connected to the data signal switching device 42.
2 is connected.

Data signal lines 5100 to 5163, 520
0-5263, 5300-5363, 5400-546
3 is memory modules A1 to An, B1 to Bn, C1
Cn, D1 to Dn and data signal switching devices 411, 41
2, 421 and 422 are connected. Data signal line 5100
5115 connect the data signal switching device 411 and 0 to 15 bits of the storage areas of the memory modules A1 to An,
5200 to 5215 are 16 to 31 bits of storage areas of the data signal switching device 411 and the memory modules A1 to An.
The data signal lines 5300 to 5315 connect the data signal switching device 411 to the storage areas of the memory modules C1 to Cn, 0 to 15 bits, and the data signal lines 5400 to 5400.
˜5415 connect the data signal switching device 411 and 16 to 31 bits of the storage areas of the memory modules C1 to Cn. The data signal lines 5116 to 5131 connect the data signal switching device 412 to the storage areas 32 to 47 bits of the memory modules A1 to An.
231 connects the data signal switching device 412 to the storage areas 48 to 63 bits of the memory modules A1 to An, and the data signal lines 5316 to 5331 connect the data signal switching device 412.
12 and 32 of the storage areas of the memory modules C1 to Cn
47 bit is connected, and data signal lines 5416 to 5431 are connected.
Is a data signal switching device 412 and memory modules C1 to C1.
Connect 48 to 63 bits of the storage area of Cn. The data signal lines 5132 to 5147 are data signal switching devices 421.
And 0 to 15b of the storage areas of the memory modules B1 to Bn
It is connected and 5232 to 5247 are one of the storage areas of the data signal switching device 421 and the memory modules B1 to Bn.
6 to 31 bits are connected, and data signal lines 5332 to 53
47 is a data signal switching device 421 and a memory module D
The data signal lines 5432 to 5447 are connected to the data signal switching device 421 by connecting 0 to 15 bits of the storage areas 1 to Dn.
And 16 to 31 of the storage areas of the memory modules D1 to Dn
Connect the bit. The data signal lines 5148 to 5163 are 422 and 32 of the storage areas of the memory modules B1 to Bn.
~ 47 bits are connected, and data signal lines 5248 to 526 are connected.
3 is a data signal switching device 422 and a memory module B1
48 to 63 bits of the storage area of Bn to Bn, the data signal lines 5348 to 5363 are connected to the data signal switching device 422.
And 32 to 47 of the storage areas of the memory modules D1 to Dn
Bits 5448 to 5463 connect the data signal switching device 422 to the storage areas 48 to 63 bits of the memory modules D1 to Dn. Data signal line 5100-
5163 is a data signal line of the first way, data signal lines 5200 to 5263 are data signal lines of the second way, data signal lines 5300 to 5363 are data signal lines of the third way, and Signal lines 5400-5
Reference numeral 463 is a data signal line of the fourth way. As described above, the memory system according to the third embodiment of the present invention has four ways.

The data switching signal lines 41 to 42 are connected to the data signal switching devices 411, 412, 421 and 422 and controlled by the memory control device S3. The data signal switching devices 411, 412, 421, 422 are devices for switching the data signal of the memory system S4 according to the present invention, and the system data signal lines 300 to 363 are the data signals when the data signal switching lines 41, 42 are low level. When the data signal switching line 41 is connected to the signal lines 5100 to 5163, the data signal switching line 41 is at the high level and the data signal switching line 42 is at the low level, the data signal lines 5200 to 5263 are connected,
When the data signal switching line 41 is low level and the data signal switching line 42 is high level, the data signal lines 5300 to 5300
When the data signal switching lines 41 and 42 are connected to the 363 and are at a high level, the data signal switching lines 41 and 42 are connected to the data signal lines 5400 to 5463. When the data signal switching lines 41 and 42 are low level, the data signal switching device 411 connects the system data signal lines 300 to 315 to the data signal lines 5100 to 5115, and the data signal switching device 412 connects the system data signal lines 316 to 331. The data signal switching device 421 is connected to the data signal lines 5116 to 5131, and the system data signal lines 332 to 347 are connected to the data signal lines 5132 to 5147.
The data signal switching device 422 connects the system data signal lines 348 to 363 to the data signal lines 5148 to 516.
Connect to 3.

When the data signal switching line 41 is at a high level and the data signal switching line 42 is at a low level, the data signal switching device 411 connects the system data signal lines 300 to 315 to the data signal lines 5200 to 5215, and the data signal switching device is connected. 412 connects the system data signal lines 316 to 331 to 5216 to 5231, and the data signal switching device 42.
1 connects the system data signal lines 332 to 347 to the data signal lines 5232 to 5247, and the data signal switching device 4
Reference numeral 22 connects the system data signal lines 348 to 363 to the data signal lines 5248 to 5263. When the data signal switching line 41 is at the low level and the data signal switching line 42 is at the high level, the data signal switching device 411 sets the system data signal lines 300 to 315 to the data signal lines 5300 to 5315.
The data signal switching device 412 connects the system data signal lines 316 to 331 to the data signal lines 5316 to 533.
1, the data signal switching device 421 connects the system data signal lines 332 to 347 to the data signal lines 5332 to 53.
47, the data signal switching device 422 connects the system data signal lines 348-363 to the data signal lines 5348-5.
Connect to 363. When the data signal switching lines 41 and 42 are at the high level, the data signal switching device 411 sets the system data signal lines 300 to 315 to the data signal lines 5400 to 5400.
The data signal switching device 412 connects the system data signal lines 316 to 331 to the data signal lines 5416 to 415.
5431, the data signal switching device 421 connects the system data signal lines 332 to 347 to the data signal line 5432.
To 5447, the data signal switching device 422 connects the system data signal lines 348 to 363 to the data signal line 544.
8 to 5463.

However, the data signal switching devices 411, 41
2, 421 and 422 are data signal lines 5100 to 516.
3,5200-5263, 5300-5363, 540
Input and output are always performed simultaneously with respect to 0 to 5463.

The RAS signal lines 811 to 81n are connected to the memory modules A1 to An, B1 to Bn, C1 to Cn and D1.
Connected to Dn. The CAS signal lines 821 to 82n are connected to the memory modules A1 to An, B1 to Bn, C1 to Cn,
It is connected to D1 to Dn. The RAS signal line and the CAS signal line are controlled by the memory control device S3. For any positive integer y less than or equal to n, memory modules Ay, By, C
y and Dy are connected to the RAS signal line 81y and the CAS signal line 82y.

The address signal lines 70 to 79 are connected to the memory modules A1 to An, B1 to Bn, C1 to Cn and D1 to D, respectively.
connected to all n. The memory control device S3 sets the addresses of the storage areas to be accessed to the upper 10 bits and the lower 10 bits.
The data is output to the address signal lines 70 to 79 in two divided bits. The memory control device S3 includes the address signal lines 70-
At 79, the RAS signal line is set to low level when outputting the upper address, and the CAS signal line is set to low level when outputting the lower address.

The write signal line 83 is connected to the memory module A.
1 to An, B1 to Bn, C1 to Cn, and D1 to Dn are connected and controlled by the memory control device S3. The memory control device S3 sets the write signal line 83 to the low level when writing data to the memory system S4 according to the third embodiment of the present invention, and sets the write signal line 83 when reading data. To high level.

FIG. 13 shows the memory modules A1 and B of the memory system S4 according to the third embodiment of the present invention.
It is a figure of the storage area of 1, C1, D1.

Areas A101 to A1m1, Areas A102 to
A1m2, areas A103 to A1m3, areas A104 to A
1m4 represents a storage area of the memory module A1. Areas A101 to A1m1 are 0 to 1 of the storage areas at addresses 0 to m.
It is 5 bits and is connected to the data signal lines 5100 to 5115. Areas A102 to A1m2 are 16 to 31 bits of the storage area at addresses 0 to m, and the data signal line 5200
˜5215. Areas A103 to A1m3 are 0
32 to 47 bits of the storage area at address m, and are connected to the data signal lines 5116 to 5131. Area A104
~ A1m4 is 48 to 63 bits of the storage area of addresses 0 to m
And are connected to the data signal lines 5216-5231.

Areas B101 to B1m1, B102 to B1
m2, B103 to B1m3, B104 to B1m4 represent storage areas of the memory module B1. Area B101-
B1m1 represents 0 to 15 bits of the storage area of addresses 0 to m, and is connected to the data signal lines 5132 to 5147. Areas B102 to B1m2 are 16 to 16 in the storage area at addresses 0 to m.
It represents 31 bits and is connected to the data signal lines 5232 to 5247. Areas B103 to B1m3 represent 32-47 bits of the storage area at addresses 0 to m, and the data signal line 514
8-5163. Areas B104 to B1m4 represent 48 to 63 bits of the storage area at addresses 0 to m, and are connected to the data signal lines 5248 to 5263.

Areas C101 to C1m1, C102 to C1
m2, C103 to C1m3, C104 to C1m4 represent storage areas of the memory module C1. Area C101-
C1m1 represents 0 to 15 bits of the storage area of addresses 0 to m, and is connected to the data signal lines 5300 to 5315. Areas C102 to C1m2 are 16 to 16 in the storage area at addresses 0 to m.
It represents 31 bits and is connected to the data signal lines 5400 to 5415. Areas C103 to C1m3 represent 32-47 bits of the storage area at addresses 0 to m, and the data signal line 531
6 to 5331. Areas C104 to C1m4 represent 48 to 63 bits of the storage area at addresses 0 to m, and are connected to the data signal lines 5416 to 5431.

Areas D101 to D1m1, D102 to D1
m2, D103 to D1m3, D104 to D1m4 represent storage areas of the memory module D1. Area D101
D1m1 represents 0 to 15 bits of the storage area of addresses 0 to m, and is connected to the data signal lines 5332 to 5347. Areas D102 to D1m2 are 16 to 16 in the storage area at addresses 0 to m.
It represents 31 bits and is connected to the data signal lines 5432 to 5447. Areas D103 to D1m3 represent 32-47 bits of the storage area at addresses 0 to m, and the data signal line 534
8-5363. Areas D104 to D1m4 represent 48 to 63 bits of the storage area at addresses 0 to m, and are connected to the data signal lines 5448 to 5463. Memory modules A2-An, B2-B, C2-Cn, D2-Dn
The storage area has the same structure.

FIG. 14 is a diagram showing the correspondence between storage areas and ways according to the third embodiment of the present invention. For the memory banks 11 to 1n, for example, the memory bank 1y has memory modules Ay, By, and
It is composed of Cy and Dy. Memory module A
The same RAS signal line and CAS are provided for y, By, Cy, and Dy.
The signal line is connected. Regions An01 to Anm1, An0
2-Anm2, An03-Anm3, An04-Anm
Reference numerals 4 to 0, 15, 16 to 31, 32 to 47, and 48 to 4 of the storage areas of addresses 0 to m of the memory module An, respectively.
It represents 63 bits. The same applies to the regions Bn, Cn, and Dn. The memory group 21 includes memory modules A1 to A
n and memory modules C1 to Cn. The memory group 22 includes memory modules B1 to Bn and memory modules D1 to Dn.

FIG. 15 is a diagram showing a logical configuration of ways of the memory bank 11 of the memory system S4 according to the third embodiment of the present invention. The way 91 constitutes the first way of the bank 11 according to the embodiment of the third invention.
The way 92 constitutes the second way of the bank 11. The way 93 constitutes the third way of the bank 11. The way 94 constitutes the fourth way of the bank 11. Each way has m + 1 storage areas of 64 bits. The first way 91 is composed of 0 to 15 and 32 to 47 bits of the respective storage areas of the memory modules A1 and B1 and serves as storage areas of addresses 0, 4, ..., 4m. The second way 92 is composed of 16 to 31, 48 to 63 bits of the respective storage areas of the memory modules A1 and B1 and becomes a storage area of addresses 1, 5, ..., 4m + 1. The third way 93 is composed of 0 to 15 and 32 to 47 bits of the storage areas of the memory modules C1 and D1, respectively, and serves as a storage area of addresses 2, 6, ..., 4m + 2. The fourth way 94 is composed of 16 to 31, 48 to 63 bits of the respective storage areas of the memory modules C1 and D1 and serves as a storage area of addresses 3, 7, ..., 4m + 3.
The ways of the memory banks 12 to 1n have the same configuration as that of the memory bank 11.

16 to 18 are views showing the arrangement of the memory modules according to the third embodiment of the invention. Unless otherwise noted, the following description is common to FIGS. Memory modules A1 to An and memory modules C1 to Cn
Alternate memory modules A1, C1, A2, C2
, An, Cn are arranged in one row (hereinafter, this row is referred to as a first row) at equal intervals. Memory modules B1 to Bn
, And the memory modules D1 to Dn are alternately arranged in one row in the order of the memory modules B1, D1, B2, D2 ,.

The data signal switching devices 411 and 412 are arranged near the memory module A1 in a line perpendicular to the first column. Data signal switching devices 421 and 422
Are arranged near the memory module B1 in a line perpendicular to the second column. Memory modules A1 to An,
In C1 to Cn, the substrate surface of each memory module (hereinafter referred to as the first surface) has data signal switching devices 411, 41.
Arrange them in parallel in row 2. The memory modules B1 to Bn and D1 to Dn are arranged such that the substrate surface of each memory module is parallel to the row of the data signal switching devices 421 and 422. Memory modules A1 to An,
The straight line connecting the centers of the first surfaces of C1 to Cn passes on the midpoint of the straight line connecting the data signal switching devices 411 and 412. The straight line connecting the centers of the first surfaces of the memory modules B1 to Bn and D1 to Dn passes on the midpoint of the straight line connecting the data signal switching devices 421 and 422. For any positive integer y less than or equal to n, the data signal switching device 41 from the memory module Ay
The distance to 1 is equal to the distance from the memory module By to the data signal switching device 421. Similarly, the distance from the memory module Cy to the data signal switching device 411 is equal to the distance from the memory module Dy to the data signal switching device 421.

As shown in FIG. 14, the data signal lines from the data signal switching devices 411 and 412 are connected only to the memory modules A1 to An and C1 to Cn, and the data signal switching devices data signal switching devices 421 and 422 are connected. Data signal lines from the memory modules B1 to Bn, D1 to D
It is connected only to n. Therefore, when the data signal switching devices 411 and 412 are arranged near the memory module A1 as shown in FIGS. 16 to 18, the data signal line length connected to the memory in the first column is shortened. The same effect can be obtained by disposing the data signal switching devices 421 and 422 near the memory module B1. In this way, it is possible to reduce the timing delay of the data signal and realize a high-speed memory system.

Further, according to the connection method, the distance from the memory module Ay to the data signal switching device 411 is set to the memory module B for any positive integer y of n or less.
When it is equal to the distance of the data signal switching device 421 from y,
The data signal line length from the memory module Ay to the data signal switching device 411 is equal to the data signal line length from the memory module By to the data signal switching device 421. Similarly, from the memory module Cy to the data signal switching device 4
The data signal line length to 11 is equal to the data signal line length from the memory module Dy to the data signal switching device 421. The memory modules Ay, By, Cy, Dy are memory modules that are accessed at the same time.
Since the variation of the data signal line length for the four memories is about the distance between the memory module Ay and the memory module Cy, the variation of the timing at the time of data access is reduced, and a high-speed memory system can be realized.

Furthermore, since the data signal lines between the first column and the second column are eliminated by the connection method, the first column and the second column are eliminated.
The rows may be arranged separately on the same substrate surface of the memory system S4 as shown in FIG. 16, or may be arranged as shown in FIG.
By arranging the data signal lines in series on the same substrate surface, it is possible to disperse the data signal lines, reduce the wiring layers for the data signal lines, and reduce the manufacturing cost of the substrate of the memory system S4. Further, the first column and the second column are arranged on different substrate surfaces as shown in FIG. 18, and a positive integer y less than or equal to n is set.
For memory module Ay and memory module B
y is arranged on a line perpendicular to the substrate surface of the memory system S4, and the memory modules Cy and Dy are arranged on a line perpendicular to the substrate surface of the memory system S4.
12 and the data signal switching devices 421 and 422 are respectively arranged on the lines perpendicular to the substrate surface of the memory system S4, the memory system S4 can be arranged in a small range, and the manufacturing cost of the substrate of the memory system S4 can be reduced. It can be lowered.

The third aspect of the present invention will now be described with reference to FIGS. 14 and 15.
The storage system of the embodiment of the invention will be described. Address 0 (memory area of way 91), address 1 (memory area of way 92), address 2 (memory area of way 93), address 3 (way) of bank 11 of memory system S4 according to the third embodiment of the invention. The data signal lines 5100 to 5115 are stored in the storage area A101, the data signal lines 5116 to 5131 are stored in the storage area A103, and the data signal lines 5116 to 5131 are stored in the storage area A101, as shown in FIG. Since the data signal lines 5148 to 5163 are connected to the storage area B103 in the area B101, the data of the way 91 is written in the storage areas A101, A103, B101, B103 as shown in FIG. Similarly, the data signal lines 5200 to 526
The data of the way 92 output to the memory 3 is stored in the storage area A10.
2, A104, B102, B104, the data of the way 93 is stored in the storage areas C101, C103, D101, D10.
3, the data in the way 94 is stored in the storage areas C102, C10.
4, D102, D104.

Similarly, in the access to the address 4 and thereafter, the ways 91 and 92 are divided and stored in the memory module A1 and the memory module B1 by 16 × 2 bits, and the ways 93 and 94 are stored in 16 × 2 bits and the memory module C1, respectively. It is divided into C1 and stored. Further, the storage system of the memory banks 12 to 1n is the same as that of the memory bank 11.

The operation of the third embodiment of the present invention will be described below with reference to FIG. When writing data to the ways 91 to 94 of the bank 11 of the memory system S4 according to the third embodiment of the present invention, first, the memory control device S3 sets the write signal line 83 to the low level. Subsequently, the memory control device S3 causes the system data signal line 30
When outputting data to 0-363, the memory controller S3
Outputs the data to the way 91 by setting the data switching signal lines 41 and 42 to the low level, subsequently sets the data switching signal line 41 to the high level and the data switching signal line 42 to the low level, and outputs the data to the way 92, Then, the data switching signal line 41 is set to low level, the data switching signal line 42 is set to high level, data for the way 93 is output, and finally the data switching signal line 41 is set to high level,
The data switching signal line 42 is set to the high level, and the data for the way 94 is output.

Further, the memory control device S3 sets the upper 10 bits of the address to write the data to the address signal line 7
After outputting to 0 to 79, the RAS signal line 811 is set to low level, and the memory modules A1, B1, C1, and D1 are read with the upper 10 bits of the address. Subsequently, the memory control device S3 outputs the lower 10 bits of the address to the address signal lines 70 to 79, and then sets the CAS signal line 821 to the low level to cause the memory module to read the lower 10 bits of the address.

At this time, the data signal switching devices 411, 41
2, 421 and 422 are data signal lines 5100 to 5163.
To the data signal lines 5200 to 526
Data of way 2 to 3 and data signal lines 5300 to 53
Data of way 3 to 63 and data signal lines 5400-5
The data of way 4 is output to 463. As a result, 0 to 31 bits of ways 1 and 2 are written to the memory module A1, 32 to 63 bits of ways 1 and 2 are written to the memory module B1, and 0 to 31 of ways 3 and 4 are written.
Bits are written in the memory module C1, and 32-63 bits of ways 3 and 4 are written in the memory module D1.

When reading data from the bank 11 of the memory system S4 according to the third embodiment of the present invention,
First, the memory control device S3 sets the write signal line 83 to the high level. Next, the memory control device S3 outputs the upper 10 bits of the address of the storage area from which the data is read, and then sets the RAS signal line 811 to the low level to set the upper 10 addresses of the memory modules A1, B1, C1, D1.
Read the bit. Then, the memory control device S3 applies the lower 10 bits of the address to the address signal lines 70 to 79.
After that, the CAS signal line 821 is set to low level and the lower 10 bits of the address are written to the memory module.
To read.

Memory modules A1, B1, C1, D1
Indicates the data stored at the address, and the memory module A1 indicates the data signal lines 5100-5131, 5200-
5231, the memory module B1 outputs to the data signal lines 5132 to 5163, 5232 to 5263,
The memory module C1 has data signal lines 5300 to 533.
Output to 1,5400 to 5431, and memory module D
1 is the data signal lines 5332 to 5363, 5432 to 54
63.

The memory control device S3 uses the data signal switching line 4
The data signal switching devices 411, 412, 421, 422 output the data switching signals to
For the system data signal lines 300 to 363, when the data signal switching lines 41 and 42 are at high level, the data signal line 5
The data read from 100 to 5163 is output, the data signal switching line 41 is at high level, and the data signal switching line 42 is
Is low level, the data read from the data signal lines 5200 to 5263 is output, and when the data signal switching line 41 is low level and the data signal switching line 42 is high level,
The data read from the data signal lines 5300 to 5363 is output, and when the data signal switching lines 41 and 42 are at the high level, the data read from the data signal lines 5200 to 5263 is output.

The fourth embodiment of the present invention will be described below with reference to FIGS. 1, 12 to 15 and 19 to 21. The embodiment of the fourth invention is a modification of only the arrangement of the memory module and the data signal switching device of the memory system S4 of the embodiment of the third invention. Therefore, in the embodiment of the present invention, only the arrangement of the memory modules of the memory system S4 will be described. 19 to 21 are views showing the arrangement of the memory modules according to the embodiment of the fourth invention. Unless otherwise specified, the following description will be given with reference to FIGS.
It is common to 1. The memory modules A1 to An are arranged in one row in the order of the memory modules A1, A2, ..., An (this row is called the A1 row) at equal intervals. The memory modules C1 to Cn include the memory modules C1, C2, ...
They are arranged in one row in the order of Cn (this row is called the A2 row) at equal intervals. The memory modules B1 to Bn are arranged in a row in the order of the memory modules B1, B2, ..., Bn.
(Equal to a column) are arranged at equal intervals. Memory module D
The memory modules D1, D2, ..., Dn are arranged in one row (this row is called the B2 row) at equal intervals in the order of the memory modules D1, D2 ,.

The data signal switching devices 411 and 412 are arranged near the memory module A1 in a line perpendicular to the A1 line. Data signal switching devices 421 and 422
Are arranged near the memory module B1 in a line perpendicular to the column B1. The A1 row and the A2 row are arranged in one row (this row is referred to as a first row) with the data signal switching devices 411 and 412 interposed therebetween. The B1 row and the B2 row are arranged in one row (this row is referred to as a second row) with the data signal switching devices 421 and 422 interposed therebetween.

It is assumed that the distances from the memory modules Ay and Cy to the data signal switching devices 411 and 412 are equal to an arbitrary positive integer y of n or less, and that the data signal switching devices are connected from the memory modules By and Dy, respectively. The distances to 421 and 422 are also equal.

Memory modules A1 to An, C1 to Cn
Are arranged so that the substrate surface of each memory module (hereinafter referred to as the first surface) is parallel to the row of the data signal switching devices 411 and 412. Memory modules B1 to Bn,
D1 to Dn are arranged such that the first surface of each memory module is parallel to the row of the data signal switching devices 421 and 422. The straight line connecting the centers of the first surfaces of the memory modules A1 to An and C1 to Cn is the data signal switching device 41.
Pass on the midpoint of the straight line connecting 1,412. The straight line connecting the centers of the first surfaces of the memory modules B1 to Bn and D1 to Dn passes on the midpoint of the straight line connecting the data signal switching devices 421 and 422.

As shown in FIG. 14, the data signal lines from the data signal switching devices 411 and 412 are connected only to the memory modules A1 to An and C1 to Cn, and the data signal lines from the data signal switching devices 421 and 422 are connected. Are connected only to the memory modules B1 to Bn and D1 to Dn. Therefore, when the data signal switching devices 411 and 412 are arranged near the memory module A1 as shown in FIGS. 19 to 21, the length of the data signal line connected to the memory in the first column is shortened. The same effect can be obtained by disposing the data signal switching devices 421 and 422 near the memory module B1. In this way, it is possible to reduce the timing delay of the data signal and realize a high-speed memory system.

Further, according to the connection method, the distance from the memory module Ay to the data signal switching device 411 is set to the memory module B for an arbitrary positive integer y of n or less.
When it is equal to the distance of the data signal switching device 421 from y,
The data signal line length from the memory module Ay to the data signal switching device 411 is equal to the data signal line length from the memory module By to the data signal switching device 421. Similarly, from the memory module Cy to the data signal switching device 4
The data signal line length to 11 is equal to the data signal line length from the memory module Dy to the data signal switching device 421. The memory modules Ay, By, Cy, Dy are memory modules that are accessed at the same time.
Since there is no variation in the length of the data signal lines for the four memories, variation in the timing of data access is reduced, and a high-speed memory system can be realized.

Further, the data signal switching devices 411, 41
By arranging 2 between the A1 column and the A2 column, the maximum length of the data signal lines from the data signal switching devices 411 and 412 becomes half of that of the third embodiment. Similarly, the maximum length of the data signal lines from the data signal switching devices 421 and 422 is half that of the third embodiment. As a result, the delay in the timing of data access is reduced, and a high-speed memory system can be realized.

Further, since the data signal lines between the first and second columns are eliminated by the connection method, columns A1, A2 and columns B1, B2 are separated as shown in FIG. 19 and the same substrate of the memory system S4. 20. The data signal lines are dispersed by arranging the same on the same substrate surface of the memory system S4 as shown in FIG. It is possible to reduce the manufacturing cost of the. Also, the A1 and A2 rows and the B1 and B2 rows are arranged on different substrate surfaces as shown in FIG.
For an arbitrary positive integer y equal to or less than n, the memory modules Ay and By are arranged on a line perpendicular to the board surface of the memory system S4, and the memory modules Cy and Dy are arranged perpendicular to the board surface of the memory system S4. Data signal switching devices 411, 41 are arranged on the respective lines.
2 and the data signal switching devices 421 and 422 are also arranged on a line perpendicular to the substrate surface of the memory system S4, the memory system S4 can be arranged in a small area.
It is possible to reduce the manufacturing cost of the substrate of the memory system S4.

[0086]

According to the present invention, the data signal line is shortened to enable high speed transmission of the data signal.

Further, according to the present invention, for each memory module, variation in the length of the data signal line from the memory module to the data signal switching device is reduced, and high-speed data signal transmission is enabled.

Further, according to the present invention, the variation in the length of the data signal line from each memory module to the data signal switching device can be reduced among a plurality of memories that are simultaneously read and written, and high-speed data signal transmission is possible. To

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an information processing apparatus according to the present invention.

FIG. 2 is a schematic block diagram of the first embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 3 is a configuration diagram of a storage area of the memory according to the first embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 4 is a configuration diagram of ways according to the first embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 5 is a configuration diagram of a storage area of a way according to the first embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 6 is a first layout diagram of the embodiment of the first invention of the memory system of the information processing apparatus according to the present invention.

FIG. 7 is a second layout diagram of the embodiment of the first invention of the memory system of the information processing apparatus according to the present invention.

FIG. 8 is a third layout diagram of the embodiment of the first invention of the memory system of the information processing apparatus according to the present invention.

FIG. 9 is a first layout diagram of the second invention embodiment of the memory system of the information processing apparatus according to the present invention;

FIG. 10 is a second layout diagram of the embodiment of the second invention of the memory system of the information processing apparatus according to the present invention.

FIG. 11 is a third layout diagram of the embodiment of the second invention of the memory system of the information processing apparatus according to the present invention.

FIG. 12 is a schematic block diagram of an embodiment of the third invention of the memory system of the information processing apparatus according to the present invention.

FIG. 13 is a configuration diagram of a storage area of a memory according to the third embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 14 is a configuration diagram of ways according to the third embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 15 is a configuration diagram of a storage area of a way according to the third embodiment of the memory system of the information processing apparatus according to the present invention.

FIG. 16 is a first layout diagram of the embodiment of the third invention of the memory system of the information processing apparatus according to the present invention.

FIG. 17 is a second layout diagram of the embodiment of the third invention of the memory system of the information processing apparatus according to the present invention.

FIG. 18 is a third layout diagram of the embodiment of the third invention of the memory system of the information processing apparatus according to the present invention.

FIG. 19 is a first layout diagram of the embodiment of the fourth invention of the memory system of the information processing apparatus according to the present invention.

FIG. 20 is a second layout diagram of the embodiment of the fourth invention of the memory system of the information processing apparatus according to the present invention.

FIG. 21 is a third layout diagram of the embodiment of the fourth invention of the memory system of the information processing apparatus according to the present invention.

FIG. 22 is a schematic block diagram of a memory system of a conventional information processing apparatus.

FIG. 23 is a layout diagram of a memory system of a conventional information processing apparatus.

FIG. 24 is a schematic block diagram of a memory system of an information processing device according to the present invention.

FIG. 25 is a layout diagram of the memory system of the information processing apparatus according to the present invention.

[Explanation of symbols]

E1 to En memory F1 to Fn memory A1 to An memory module B1 to Bn memory module C1 to Cn memory module D1 to Dn memory module E101 to E1m1 Lower 32 bits of memory area of address 0 to address m of memory E1 E102 to E1m2 memory E1 32 bits En01 to Enm1 of the storage area of the address 0 to m of the address, lower 32 bits En02 to Enm2 of the storage area of the address of memory 0 of the memory En, and upper 32 bits of the storage area of address 0 to address m of the memory En F101 to F1m1 memory of F1 address 0 to address m storage area lower 32 bits F102 to F1m2 memory F1 address 0 to address m storage area upper 32 bits Fn01 to Fnm1 memory Fn address 0 to add Lower 32 bits Fn02 to Fnm2 of storage area of memory m Upper 32 bits A101 to A1m1 of storage area of address 0 to address m of memory Fn 0 to 15 bits of storage area 0 to address m of memory module A1 A102 to A1m2 Memory module A1 16-31 bits of the storage area of address 0 to address m A103 to A1m3 32 to 47 bits of the storage area of address 0 to address m of the memory module A1 A104 to A1m4 48 of storage area of the address 0 to address m of the memory module 63 bit An01 to Anm1 0 to 15 bit An02 of storage area of address 0 to address m of memory module An02 to Anm2 16 to 31 bit An03 of storage area of memory module An from address 0 to address m nm3 memory module An address 0 to address m storage area 32-47 bit An04 to Anm4 memory module An address 0 to address m storage area 48 to 63 bit B101 to B1m1 memory module B1 address 0 to address m storage Area 0 to 15 bits B102 to B1m2 Memory module B1 address 0 to address m storage area 16 to 31 bits B103 to B1m3 Memory module B1 address 0 to address m storage area 32 to 47 bits B104 to B1m4 Memory module B1 48 to 63 bits Bn01 to Bnm1 of the storage area of address 0 to address m 0 to 15 bits Bn02 to Bnm2 of the storage area of address 0 to address m of memory module Bn Address 0 to address m storage area 16 to 31 bits Bn03 to Bnm3 memory module Bn address 0 to address m storage area 32 to 47 bit Bn04 to Bnm4 memory module Bn address 0 to address m storage area 48 to 63 bit C101 to C1m1 0 to 15 bits of storage area of address 0 to address m of the memory module C1 0 to 15 bits C102 to C1m2 Address of 0 to address of memory module C1 16 to 31 bits of storage area of the memory m C103 to C1m3 Address 0 to address m of memory module C1 32 to 47 bits C104 to C1m4 of the memory area of the memory module 48 to 63 bits Cn01 to Cnm1 of the memory area of the memory module C1 from address 0 to address m 0 to 15 bits Cn02 to Cnm2 16 to 31 bits of memory area of address 0 to address m of memory module Cn Cn03 to Cnm3 Address of memory module Cn 0 to 32 bits of memory area of address m Cn04 to Cnm4 Address of memory module Cn 0-address m storage area 48-63 bits D101-D1m1 memory module D1 address 0-address m storage area 0-15bit D102-D1m2 memory module D1 address 0-address m storage area 16-31bit D103 -D1m3 32-0 bit D104 of storage area of address 0-m of memory module D1 D104-D1m4 48-63 bit Dn01-of storage area of address 0-m of memory module D1 nm1 0 to 15 bits of the memory area of the memory module Dn 0 to address m Dn02 to Dnm2 16 to 31 bits of the memory area of the memory module Dn 0 to address m Dn03 to Dnm3 Storage of the memory module Dn address 0 to address m 32 to 47 bits of area Dn04 to Dnm4 48 to 63 bits of storage area of address 0 to address m of memory module Dn 48 to 63 bits S1 Central processing unit S2 Input / output control device S3 Memory control device S4 Memory system SD1 to SDk Input / output device SB1 to SB5 bus G0 to G4m Storage area of memory bank 11 11 to 1n Memory bank 21 First memory group 22 Second memory group 300 to 363 System data signal line 40 to 42 Data switching signal line 411 Data signal switching device 4 2 data signal switching device 421 data signal switching device 422 data signal switching device 5100 to 5163 data signal line 5200 to 5263 data signal line 5300 to 5363 data signal line 5400 to 5463 data signal line 60 schematic block diagram of conventional memory system 62 Memory system according to the invention 63 Memory system according to the invention 70 to 79 Address signal lines 811 to 81n RAS signal lines 821 to 82n CAS signal lines 83 Write signal lines 91 First way 92 Second way 93 Third way 94 Fourth The way

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Norihiro Tobita 1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture Information Technology Development Division, Hitachi, Ltd.

Claims (15)

[Claims] 1. A plurality of memories, a plurality of memory modules that combine the plurality of memories, a plurality of partial data signal lines connected to the memory modules, and the one memory module is different. A plurality of partial data signal lines are connected, and a plurality of data signal lines that combine the plurality of partial data signal lines connected to the different plurality of memory modules are provided, and one data signal line is used for one clock. An information processing device comprising the memory control device for inputting / outputting a transmitted data signal in one clock. 2. A partial data signal line forming one data signal line is connected to a plurality of different memory modules,
The information processing apparatus according to claim 1, wherein the chip select signal lines of the plurality of memory modules are connected to one signal line. 3. A plurality of data signal switching devices connected to partial data signal lines, wherein partial data signal lines forming the same data signal line are connected to different data signal switching devices, and each partial data signal line is connected. Are connected to one data signal switching device, have partial system data signal lines connected to the data signal switching device, different partial system data signal lines are connected to different data signal switching device, one of the data The signal switching device is connected to only one of the partial system data signal lines, a system data signal line that is a combination of all the partial system data signal lines is connected to a memory control device, and the data signal switching device is Connect the partial system data signal line connected to the signal switching device to an arbitrary partial data line connected to the data signal switching device. The information processing apparatus according to claim 2, which is connectable to a data signal line. 4. The memory modules connected to the data signal switching device by the partial data signal lines are continuously arranged in a row, and the data signal switching device is arranged on an extension line at one end of the row of the memory modules. The information processing device according to claim 3, wherein the number of memory modules connected to each of the data signal switching devices is equal. 5. A difference in length of partial data signal lines connected to one memory module from the memory module to a data signal switching device to which the partial data signal line is connected is set to the memory module. The information processing apparatus according to claim 4, wherein the length of the memory module including the memory module is equal to or less than the length of the memory module in the vertical direction. 6. From a memory module connected to partial data signal lines constituting the same data signal line and having a common chip select signal line to a data signal switching device to which the partial data signal line is connected, The information processing apparatus according to claim 5, wherein a difference in length of the partial data signal lines is equal to or less than a length of the memory module in a vertical direction in a column of memory modules including the memory module. 7. The information processing system according to claim 6, wherein the rows of the memory modules are continuously arranged in parallel on the same substrate surface, and the data signal switching device is continuously arranged in a row perpendicular to the rows of the memory modules. apparatus. 8. The information processing apparatus according to claim 6, wherein all the memory modules are arranged in a line on the same substrate surface. 9. Z columns of memory modules, x
A row of (x is an arbitrary positive integer less than or equal to z−x) memory modules is continuously arranged in parallel and arranged on the same substrate surface (hereinafter, this substrate surface is referred to as a first substrate surface). A row of x memory modules is continuously arranged in parallel and is arranged on a substrate surface other than the first substrate surface (hereinafter, this substrate surface is referred to as a second substrate surface), and is arranged on the first substrate surface. 7. A line perpendicular to a substrate passing through one row of the memory modules passes through one row of the memory modules arranged on the second substrate surface.
The information processing device described. 10. An n (n is an arbitrary positive integer) memory module is connected to each data signal switching device according to claim 3 by the partial data signal line, and the n memory modules are the same. Among the n memory modules, k memory modules (k is an arbitrary positive integer less than n) of the n memory modules are arranged on a substrate surface and are arranged in a row at equal intervals. The data signal switching device connected to the n memories is arranged on the extension line of the column of the memory modules, and n−k memory modules other than the k memory modules among the n memory modules are arranged. The memory modules are adjacent to each other in the row of the k memory modules in a row continuously on an extension line of the row of the k memory modules with the data signal switching device interposed therebetween. The information processing apparatus according to claim 3, wherein the information processing apparatus is arranged at the same intervals as the intervals. 11. A partial data signal line connected to one memory module, from the memory module,
11. The information processing according to claim 10, wherein a difference in length up to a data signal switching device to which the partial data signal line is connected is less than or equal to a length of the memory module in a vertical direction in a column of memory modules including the memory module. apparatus. 12. From a memory module connected to partial data signal lines forming the same data signal line and having a common chip select signal line to a data signal switching device to which the partial data signal lines are connected, The information processing apparatus according to claim 11, wherein a difference in length of the partial data signal lines is equal to or less than a length of the memory module in a vertical direction in a column of memory modules including the memory module. 13. The information processing system according to claim 12, wherein the rows of the memory modules are continuously arranged in parallel on the same substrate surface, and the data signal switching device is continuously arranged in a row perpendicular to the rows of the memory modules. apparatus. 14. The information processing apparatus according to claim 12, wherein all the memory modules are arranged in a line on the same substrate surface. 15. Z columns of memory modules, x
A row of (x is an arbitrary positive integer less than or equal to z−x) memory modules is continuously arranged in parallel and arranged on the same substrate surface (hereinafter, this substrate surface is referred to as a first substrate surface). A row of x memory modules is continuously arranged in parallel and is arranged on a substrate surface other than the first substrate surface (hereinafter, this substrate surface is referred to as a second substrate surface), and one of the memory cells is arranged on the first substrate surface. The line perpendicular to the substrate passing through the row of memory modules passes through one row of the memory modules disposed on the second substrate surface.
The information processing device described.