JPS61856A - Real time data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to data processing systems that include two or more processing units, each having access to the same data. Each data processing device may be configured as a substantially independent computer, or
It may also be configured to be able to interact with one or more other processing devices.

Data processing devices of either type are referred to hereinafter as "nodes", and data that is accessible by two or more nodes is referred to as "shared data" in the following description.

BACKGROUND OF THE INVENTION In one example of a known system used, for example, in a flight simulator, shared data is stored in a common data storage device that is accessible to two or more nodes. Each node may also be provided with its own local storage that holds data that is accessible only to that node. The problem with this type of system is that two or more nodes must compete for access to the shared storage, each attempting to access the same item of shared data in the common storage at the same time. This means that there is a possibility of conflict occurring between nodes.

Furthermore, between the shared storage device and relatively distant nodes,
There is a considerable transmission delay. As a result, access to shared data may be very slow.

U.S. Pat. No. 3,889,237 discloses a two-node system in which each node is configured to accept duplicate copies of shared data in its local storage. To ensure that both copies match, each node has direct access to the other node's local storage so that new values of the shared data can be written to both storage devices simultaneously. 2. The problem with conventional systems is that if both nodes try to access the same item of shared data at the same time, it will create a conflict between the nodes, so each node must It is necessary to wait until all writing to the shared data section of the device is completed. This greatly reduces the efficiency of the system and makes it extremely difficult to expand the system beyond two nodes.

On the other hand, European Patent Specification No. 0.092,895 has 1,
Another system is disclosed in which each node has its own local storage storing shared data therein. The nodes are interconnected with data transmission links such that whenever one node writes to address-containing shared data in its local storage, it generates a message containing the write data and the address. The message is added to the link and other nodes use the write data to update the appropriate shared data addresses in their local storage. After each node writes to a shared data address, it continues processing and does not wait for write data messages to reach other nodes. The link is formed as a token ring, and since there is only one token, only one message can be on the ring at a time.

In this way, each mode receives messages at the same node, providing temporal ordering to the messages even though individual nodes may be operating asynchronously. However, if a first node receives a write data message from a second node, while the first node still has pending write data to transmit, the received message is , overrides the data address already written by the second node (o
verwrite). The data address is further overridden by a value earlier in chronological order, and the data stored in each node's shared data storage becomes inconsistent. To prevent such inconvenience, the processing equipment of the second node is shut down pending resolution of one or more pending messages.

This processing equipment outage obviously slows down the system and becomes a serious problem when handling a large number of messages.

In real-time computing systems, such as flight training simulators, the operating speed of the system is of fundamental importance.

In this regard, real-time systems are known in which a series of nodes each perform a special function, but that function is limited within a time framework imposed by a system control computer. Examples of these systems are U.S. Pat.
It is disclosed in No. 25.

In US Pat. No. 4,414,624, the operation of the nodes is preset by a control computer depending on the required processing. At the beginning of each frame, a time control word is communicated to each node to set the time available for processing.

Each node has local storage for shared data and can write to any or all of the other nodes' local storage simultaneously. All data is first written to the common storage and then the required data is read from the common storage to the local storage. Thus, updating each data item in local storage requires both a write step to the common storage and a read step to the local storage. This reduces the operating speed of the system.

On the other hand, in U.S. Pat. distributed between time segments. ”The second composition is
Although relatively easy to implement, the operating speed is relatively low because the two parts of the system operate alternately rather than sequentially.

As mentioned above, conventional systems, including real-time systems, have strict operational standards in place to maintain the consistency of shared data in separate local storage devices, which inevitably results in The speed and flexibility of the system will be limited.

OBJECTS OF THE INVENTION The present invention has been made in view of the drawbacks of the conventional systems described above, and an object of the present invention is to provide a real-time data processing system that eliminates or alleviates the problems described above. be.

The real-time data processing device according to the present invention includes at least the following:
two nodes and a data storage device for each node, partitioning each data storage device into sections, a first section of which is reserved for storage of data local to each node; reserved for the storage of data shared between nodes, and further includes a data link connecting the nodes to each other and a data link that writes to the second section of the data storage whenever that node writes an address to the second section of the data storage. means at each node for generating a write message consisting of an address and data to be sent;
means for transmitting each generated message to each node via a data link; means for assigning to each address of the second section of the data storage each node which becomes the principal node of that address; and means for assigning each node to be the principal node of that address; and means for preventing any address within the second section of the data storage device from being written to by anyone other than the node. Each address of a data storage device containing shared data between nodes is written by only one node processing unit, so that the shared data
There is no need to strictly control the priority assigned to message writes so that they do not become unavailable. For this reason,
The operating speed of the system may be increased, but it also allows a relatively large number of nodes to operate in parallel using standard processing equipment without complex operating procedures. Thus, the requirements of a wide variety of different real-time systems can be met with relative ease. For example, the present invention can be applied to flight and other simulators, route control systems, firefighting systems, and the like.

Compare the address of the data write message generated from that node with a preset address range,
Preferably, an address range comparator is provided for each node to forward the data write message to the data link only if the compared address is within a predetermined range. In this way, the address comparator is
Effectively determines which addresses within the shared data are writable by each node. Furthermore, for each node, another address comparator is provided to compare the address of the data write message received from the data link with a preset address range, and if the compared address is within the preset address range. A received write data message may be forwarded to the local data storage device only if it is within the local data storage device.

Thus, a further provided address comparator determines the address within the local storage device to which data can be written from the data link.

Nodes can be connected in parallel by a single data link or multiple data links. Furthermore, it is also possible to provide more complex system configurations. For example, it is also possible to arrange nodes into multiple groups, connect the nodes in each group in parallel with each data link, and configure at least one of the nodes to belong to two of the groups. It is. In this arrangement, the section of the data storage device that receives the shared data of the nodes belonging to the two groups is divided into a plurality of subsections, each of which receives the data that is shared with the nodes of each group. When data is shared between two groups of nodes, software is provided to control the transfer of data from one subsection to another.

It is also desirable to further provide a memory connected to the data link and into which input/output data can be written by the node. Addresses for this purpose are provided in the node's local data storage from which data can be read and from which data can be written via the data link.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings.

The system shown in FIG. 1 is a conventionally known system, which is a 32/27-inch computer manufactured and sold by the Gould Computer Systems Division.
computer systems division
It operates based on the N32/27 Computer.

The central processing unit (CPU) 1 in this system is a high-speed communication main bus, and is a "SELBUS" bus.
) is connected to a 26.6 MB/s computer bus 2, known as J. "Integrated Memory Module (IntegratedMemo)"
A data storage device using the ry Module T MM) J3 includes an IMB memory and corresponding memory control logic. “I.O.P.
top)j device 4 is a controller that supports a system console 5 and is an IMB/See Multipurpose bus (IMB/See Multipurpose bus).
This is the main controller of Bus (MPBUS) J6.

A high-speed device such as a disk or tape controller 7 or a high-speed device interface (H8DI) 8 is a 5ELB.
is connected to US2, and on the other hand, the CRT terminal controller 9
(8 line asynchronous operation), low speed peripherals such as line printer/floppy disk controller IO etc.
Connected to BUS6. Furthermore, rsELBUsJ, r
IMMJ, rl OPJ, rMPBUSJ, rIPUJ
, rl-ISDIj refers to the above-mentioned Gould 3
An abbreviation of the name given by the manufacturer to the component parts of a 2/27-inch computer, even if the components are the same.
Different manufacturers may use different names.

However, in the description of the present invention, the names (abbreviations) used by Gould will be used.

A system according to the invention is shown in FIG. The system in the illustrated embodiment includes a series of computing units 11 based on Pooled 32/27 type computers, each computing unit 11 having its own 5ELBUS 12 and separate from other computing units. Works asynchronously. This computing unit jl does not drive any peripherals, but is connected to another computing unit 13 which is provided with all supporting peripherals. In addition, each calculation unit 11 is designed to perform processing related to a specific aspect of the system. For example, in the case of a flight simulator, one calculation unit 11 inputs operational parameters such as altitude to another calculation unit. 11 is another calculation unit 1 which calculates parameters of the aircraft engine such as propulsion force.
1 is assigned to calculate parameters for autopilot. This computing unit 11 and the further computing unit 13 and associated devices such as data storage devices constitute the nodes of the simulator according to the invention.

Since the computing node including the computing unit 11 does not drive peripheral devices, the required input/output capacity of this node is limited, and therefore all input/output operations are performed by the computing unit 13 at low speed. be done. This results in
The real-time computing power obtained by each computing node can be maximized.

Secondary R-varnish 232 channel (multiple R-varnish 232 lines) (secondary RS2
32 channels (multiple RS 2
32 L 1nes)) is for initialization (initial settings) and control functions, and is also used for fault diagnosis when the system stops functioning.

Each CPU II consists of multiple physically similar parallel processor units.
(Ocessor Unit PPU) 14.

Each PPUI4 is 32/67 type, 3.2/77 type, 32
The Gould Internal Processor Unit (Gould
ULD Internal Processes
sorUnit IPU) but with two or more 32/27 for each 5ELBUS 12
It has been extended using conventional techniques so that it can be used with type computers.

Unattended Operator's Console (Una)
ttended 0 perators Con5o
le UOC) 15 is linked to each calculation unit 11. This UOCI 5 is identical to OP (see FIG. 1) except that it includes extra logic to eliminate the need for an MPBUS normally required when driving peripherals.

The 5ELBUS 12 of each arithmetic unit 11.13 is connected to the 26°6
Connected to a MB/s data link 18 or reflective memory bus. The DPIMM 16 is sold by Gould and typically includes a second port for connection with peripheral devices for input/output control, for example. However, in the illustrated embodiment, the present invention provides a
active memory) system has been established! This DPIMM 16 is used so that -1 can be obtained.

To explain the principle of the reflective memory system shown in the figure, 2M
Each DPIMM data storage device 16 having a memory of B
is logically isolated in a predetermined location, and all data and programs on one side of this predetermined location are
Arithmetic unit 11 or 13 provided with MM16
within the area of 5ELBUS12 (local to
5ELBUS 12), but all data and programs on the other side are shared with other arithmetic units 11, 13 via bus 18. The read/write sense hardware 17 determines the use of the DPIMM 16 in a specific/shared system (local/5hared).
5ysten). This sense of reading and writing/
Logic unit 17 is connected to the second port of each DPIMMI6. If CPU13, 11 (or
When the PPU 14) writes to an address in the shared portion of the corresponding DPIMM 16, this write operation is detected by the read/write sense (read/write sense) 17 and the address, so that the data is transferred to the reflective memory bus 18.
is output to. All DPIMM+6's will then automatically accept this data and store it in their memory. Therefore, the memory of all DPIMMs 16 will contain a copy of all shared data. Therefore, each arithmetic unit has its data storage device (DPIMM+6)
You can access the data you need directly. This access can never be delayed since another processor is also accessing the same data storage device.

Note that since two or more processors attempt to process the same data item at the same time, it is fundamentally important to avoid "collisions" caused by this. The avoidance of this collision is achieved by using the read/write sense logic as described above.
This can be accomplished by using its read/write sense logic unit 7 to issue a single write command from unit 17 to each of the other nodes of the system. Since each node has its own unique address partition, only one node can write data to each address in the shared data portion of the data storage device, and only one node can write data to each address in the shared data portion of the data storage device 16. The address is the same as the address of the same item of data in all remaining data storage devices 16. Therefore, although all nodes can write to the shared data section of all data storage devices 16, the transaction in which this is actually performed depends on the address to which the data is written, making the system the "master". A transaction within a memory segment. For example, in the case of a flight simulator consisting of a flight processor,
Only that processor can actually modify the stored value for altitude. This is because the altitude is within the address range of the processor and outside of the address range of other processors. In other words, other processors can read the stored value for altitude, but cannot modify it. Therefore, numerical discrepancies can be avoided without requiring complicated procedures to maintain the same chronological order in preparation for updating shared data in different data storage devices.

Another feature is that read/write sense hardware 17 can detect input/output read/write requests for addresses assigned to input/output data in memory 16 of the DPIMM. The address indicates a location in RAM+9 connected to a user high speed human output device, such as a flight simulator input/output link.

This allows high-speed data acquisition. (Previously, DP
The IMM+6 was used for input/output functions, but it was also used in block mode transmission rather than the transmission of individual data elements. ) This kind of input/output is called Memory Mat input/output (Memory Mat) ped
tnputoutput).

The exchange of signals between the 5ELBUS 12 of each node and the reflective memory bus 18 will be explained with reference to FIGS. 3 and 4.

Each bus 12, 113 carries parallel data and addresses.

bus organization signal
signals), and the bus control signals are 26.6
It is transmitted at a speed of MB/s. This data rate is
It can be maintained over a bus length of 40 feet, but for bus lengths or longer, for example, if the bus length is 80 feet, it must be slowed down to 13.3 MB/sec. FIG. 3 schematically illustrates the bus 18, with 32 data lines, 24 address lines, 9 bus request lines, and 9 bus reception lines (bus gr).
ant 1ines) and four node identification lines (no
de 1dentity 1ines) and a control line. However, only two control lines are shown as they are suitable for data communication via the bus 18. There are nine nodes, and a bus request line and a bus reception line are assigned to each node, and one node consists of a CPU 13, and each other node consists of a CPU 11. .

FIG. 4 is a detailed illustration of the main parts in FIG. 2, and shows the DPIMM connected between bus 12 and bus 18.
+6 and the details of the read/write sense logic 17. When a node processor associated with the configuration shown in FIG. 4 writes to the data storage device 16, the data to be written and its address are sent to the latch circuit 20, and the address to be written is sent to the address comparator 21. are loaded respectively. Thus, assuming data has been successfully written to the storage device 6, a "write success" signal is sent to the detector 22. This "write success" signal is sent over any one of the control lines of bus 12 in exactly the same manner as in the prior art.

If the address is not within the predetermined range set by comparator 21, it means that it is local and will not be shared with other nodes. On the other hand, if the address is within the predetermined range, the comparator outputs an output to the AND gate 23. Since the detector 22 also outputs an output to the gate 23, the latch circuit 20 is controlled by the detector 22, and the address and data in the latch circuit 20 are determined to be within the set range and if the address is "write". first-in-first-out register 24 only when a "success" signal is detected.
t register (FIFO)).

FIFO 24 can queue up to 64 messages for transmission, although normally there are only one or two messages in the queue. If a queue of 60 or more messages is created, the message is "busy".
A signal is issued to the system to increase the priority weight of each node in making bus access requests. Suitable circuitry, not shown, is also provided to interrupt the associated node processor when the FIFO becomes full with messages awaiting transmission.

When the FIFO 24 stores a message for transmission, this is detected by the bus request logic circuit 25, which then outputs a bus request signal to each line of the bus 18. This bus request signal is sent to CPU 13 (FIG. 2) to control the operation of bus 18. CPU13
allows access to nodes that have messages to be transmitted one by one in a predetermined order, so that the first message in the queue at each node is one of the operations on bus 18.
The message is transmitted during the cycle, and thereafter messages are transmitted sequentially in the same way. Accordingly, the bus request logic receives a "bus accept" signal from bus 18 and accordingly causes the message in FIFO 24 to be sent to bus 18 via transmitter 26.

If the configuration shown in FIG. 4 is a node that receives a transmitted message, the transmitted message is handled as follows. That is, the CPU 13 accepts a bus request, and a clock signal is output to one of the control lines of the bus 18 accordingly. This clock signal is used to initiate a message transmission/reception cycle, and when a message is transmitted, its validity is determined by CPU 13 using conventional routines such as parity checking. That is, when the data sent to the bus is determined to be valid, a "data valid" signal is transmitted to the other control lines of bus I8. Thus, the transmitted message is bracketed by the clock signal and the "data valid" signal.

Thus, the transmitted data and address are transferred to the receiver 28.
At the same time, the address is loaded into the address comparator 29. The “data valid” signal is detected by a “data valid” signal detector 30. The outputs of the comparator 29 and the detector 30 are connected to an AND gate 31, and the comparator 29 is connected to the memory device 1.
A predetermined range of addresses are set that correspond to portions of the data storage device 16 that are written by nodes other than the node for which node 6 is local. Therefore, if the received address is within this range and at the same time the "data valid" signal is detected, the FI
The message data in the latch circuit 27 is transferred to the FO 32. FIF03,. 2, a queue of up to 64 messages, including data to be written, is stored in the storage device 16.

When the F I FO 32 has a message to be written to the storage device 16, a memory contents transfer request is made to the request logic circuit 33, so that the circuit 33 writes the message to the storage device 16.
and receives a request acceptance signal from the storage device 16. As a result, the first message in the queue stored in the FIFO 32 is released, and the corresponding address in the storage device 16 is thus updated.

The chronological order in which data items are output (chronology
A valid number of messages may be stored in the FIFO 24, 32 containing the data items to be written to storage accordingly in a different order than the messages (calordes). but,
Each address of shared data is written by its own "master" node, and after the messages output by that node are collected in FIF024,
Since data is transmitted from the FIFO 24 in time order, each memory address is updated in the correct order. It is possible that the data at different addresses may be somewhat out of chronological order, but this also depends on the rate of change of the stored parameters in a real time interaction system.
1interactive systems), the response speed of the system (interaction
rate of the system), so this is not a problem. Therefore, the system designer does not need to impose the precise procedures required to maintain time order, but only needs to set the address comparators 21,29 correctly. Thus, the system according to the invention is very flexible and can be implemented relatively easily, even for very complex real-time tasks such as flight simulations.

The four node identification lines (FIG. 3) on bus 18 are used to identify the node that originated the message transmitted on the bus. This information is stored in read/write sense logic 17 (
It is not necessary for the data to be processed (FIG. 4), but is used to monitor the traffic on the bus 18. Therefore, failures or bolt necks on the bus 18 can be easily detected, and with this extra information available, such troubles can be handled.

5 to 7 are schematic diagrams of three types of system configurations, all of which are related to the present invention.

FIG. 5 is a system configuration diagram of FIG. 2, with a series of nodes N
are connected by a single reflective memory bus RMI. FIG. 6 is similar to the system configuration of FIG. 5, but is connected by parallel reflective memory buses RMI and RM2. In such a configuration, the system is normally operated using bus RMI only, with bus RM2 idle;
As soon as a failure occurs on bus RM, the system
You can switch to 2. If the status of these buses is monitored and RM1, RM2 are configured independently, a fail-safe self-correction device can be realized. Furthermore, two sets of processing nodes are provided, and both have buses RMI,
By connecting it to RM2 and leaving one in normal operation and the other in standby mode, system security can be ensured even if one fails.

In the configuration of Figures 5 and 6, each reflective memory bus is connected to each node so that even between the most distant nodes the transmission range of the bus, typically 40 feet at 26°6 MB/sec, is maintained. It cannot be surpassed. In some cases, for example,
In a shipboard fire control system, if you want the system to continue operating even if one node is completely damaged, or if you want the nodes to be spread out, the nodes should be separated by a wider distance than the above distance. It is preferable.

That way, even if there is local damage, the majority of nodes will not be damaged. FIG. 7 shows an arrangement according to the invention, which makes it possible to make the distance between the closest nodes equal to the maximum transmission range of the reflective memory bus.

In the configuration of FIG. 7, the series of six nodes N1 to N6 effectively consists of five sets of bears Nl, N2 . N2°N3. N1.
N4. N2. N5 and N3. Each pair operates in the order described in FIG. The pairs of nodes are linked by respective reflective memory buses RMI to RM5. The storage of each node is divided into a local data section and a shared data section, and the shared data section is further subdivided into subsections dedicated to each reflective memory bus. Therefore, all nodes have a shared data section, but in node Nl it is subdivided into two subsections, in node N2 it is subdivided into three subsections, while in node N4 it is not subdivided at all. do not have. Each subdivided subsection of the shared memory is provided with successive sense circuits corresponding to circuits 27 to 33 of FIG.

Assuming that node Nl outputs data to be shared, that data will have a special address throughout the entire system that only node N1 can write to it. Node N1 attempts to write its data to each subsection of shared memory only if the address assigned to the data is within the range set by the address comparator of the successive sense logic. success.

If the data is written to all subsections, it is transmitted to nodes N2 and N4. Then, node N2 transmits the data newly written in its own shared memory to nodes N3 and N5, but in this case, the data in the allocated subsection is transferred to the memory bus for RMI. The data is copied to the respective subsections allocated for RM2 and RM4, and data transmission is performed under software control. Data is then transmitted from node N3 to node N6. Since each memory location can only be written to by a single node, data transmission between nodes can be accomplished in a fairly simple manner. In the illustrated configuration, there is only one data transmission path between any two nodes, but it is not necessarily limited to this. For example, the memory bus RM6 as shown by the dotted line is connected to the node N4.
It may be added between N5 and N5. If data generated at node N1 is to be written to the shared memory of node N5, the data is transmitted via buses RMI and RM4, and if that is not successful, another route is taken to route bus R.
It is also possible to program the software to transmit via M3 and RM6. A software routine that controls the subsection of the shared data memory into which data is written is sufficient.

The configuration not shown in Figure 8 is similar to that shown in Figure 7, but
The nodes are interconnected in groups of nine nodes by pairs of single nodes interconnected by individual reflective memory buses.

The groups are interconnected in pairs with another reflective memory bus connected to one node selected from each group. As shown in Figure 8, each group is
It has a front end processor node PEN similar to the one containing the processor unit 13 shown in FIG. The nodes Nl to N8 are interconnected. Nodes N8 are coupled together in pairs by reflective memory buses RMI to RMn and operate as a "software exchange" in the same way as node N2 in FIG.

"Software swapping" between different reflective memory buses introduces some delay in data transmission between the buses. FIG. 9 shows a "repeater J" replacing the "software exchange", whereby an automatic hardware connection can be achieved and speeding up data transmission.

In FIG. 9, the illustrated repeater is connected to bus RM2. R
It replaces the node N8 between Ma and is constructed using three sets of read/write sense hardware similar to the read/write sense hardware 17 shown in FIGS. 2 and 4. Each set has a successive sense circuit R8C and a write sense circuit WSC, and each port thereof is connected to a reflective memory bus, and the output of each successive sense circuit is connected to the input of the other two write sense circuits. be done. Each boat has its own isolated address, the range of which limits data transmission between the buses as desired. Therefore, a repeater behaves exactly like any other node connected to the bus, and the data transmitted by the repeater to the reflective memory bus is the data output by all other nodes on that bus. are treated exactly the same. Data is,
Buffered by a repeater using a FIFO circuit,
As with normal nodes, bus access is restricted.

There is no need for extra software associated with data transmission between buses, and the amount of data transmitted on the bus is limited to that required by selecting the range of addresses for data transmitted from each read/write sense circuit. Therefore, the system can operate at high speeds and easily utilize buses with long transmission distances and relatively low data rates.

Using repeaters makes it easy to introduce a standby system. Additionally, the system is always fully updated, so it can be operated at any time if there is a malfunction in the main unit.

Note that the repeater itself can also be duplicated.

As described in detail above, the present invention achieves the intended purpose and is significant.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the configuration of a conventional data processing system, FIG. 2 is a schematic block diagram showing the configuration of a real-time data processing system according to the present invention, and FIG. 3 is the same as that shown in FIG. FIG. 4 is a schematic block diagram showing the configuration of the read/write hardware used in the system of FIG. 2; FIGS. FIG. 3 is a schematic block diagram showing the configuration of a modified example of the system according to the invention. l...CPU, 2, 6, 12.18...Bus 3...
IMM, 4...I/O device N1. N2. N3...Node. Patent Applicant Lidifugeon Nmikoreinyon Limited Patent Attorney Aoyama Baka 2 Engravings of famous gardens (no changes in content) Procedural amendments June 11, 1985 Director General of the Patent Office Toshiro 1, Case Description Showa 1960 Patent Application No. 49190 2. Name of the invention: Real-time data processing device 3. Relationship with the person making the amendment Patent applicant nationality: United Kingdom 4. Address of agent: 2 Honmachi, Higashi-ku, Osaka-shi, Osaka Prefecture -] O Honmachi Building Attachment As of.

Claims (1)

[Scope of Claims] 1) At least two nodes and a data storage device for each node are provided, each data storage device is partitioned into sections, and the first section is used for storing data local to each node. a second section for the storage of data to be shared between the nodes, and a second section for data links connecting the nodes to each other and a second section of the data storage that the nodes address. to each node via the data link, with means at each node generating a write message consisting of the address and data to be written to that address whenever the address is written.
means for transmitting each generated message; and means for assigning, to each address in the second section of the data storage, each node that becomes the primary node for that address; 1. A real-time data processing device, comprising means for preventing writing to any address within the section. 2) What is described in claim (1),
The allocation means and the prevention means are provided for each node, and compare the address of a data write message generated from that node with a set address range, and only when the address is within the set range, the data write message is A real-time data processing device consisting of an address range comparator that forwards write messages to a data link. 3) What is described in claim (2),
a latch circuit into which each data write message is loaded; a first-come, first-served register connected to the output of the latch circuit; and a detector to detect a successful write of data to a data storage device local to the node. is connected to the detector and the comparator, and when it is detected that the compared address is within the set address range and data writing has been successfully performed, the contents of the latch circuit are transferred to the Each node is provided with an AND gate that controls the latch circuit and a transmitter that is connected to the register and that transmits the message stored in the register via a data link. Real-time data processing equipment. 4) What is described in claim (2),
The allocation means and the prevention means compare the address of the data write message received from the data link with a set address range, and locally assign the received data write message only if the compared address is within the set address range. A real-time data processing device that includes an address comparator for each node that transmits to a data storage device. 5) What is described in claim (4),
One of the nodes controls the amount of communication on the data link, while each of the remaining nodes is configured with an access request logic circuit, and the one node that controls the amount of communication is configured to control the amount of communication on the data link. means for individually allocating access to said remaining nodes to a data link in response to an access request from an access request logic circuit; means for supplying a clock signal to said data link each time said access is granted to a node; means for verifying the validity of the message being transmitted; and means for providing a valid signal to the data link if the verified message is valid; before a valid signal is received,
A real-time data processing device consisting of blocking means provided for each node. 6) What is described in claim (1),
A real-time data processing device with two data links connected in parallel to the nodes. 7) What is described in claim (1),
arranging the nodes in a plurality of groups, connecting the nodes in each group in parallel by respective data links, and configuring at least one of the nodes to belong to two of the groups; The section of data storage that receives data shared by the nodes is divided into a plurality of subsections, each receiving data shared with each group of nodes, and the section of data storage that receives data shared between the nodes is If shared, a real-time data processing device provided with software to control the transfer of data from one subsection to another. 8) What is described in claim (1),
providing two groups of nodes and connecting them to each other by a respective data link and a repeater connected to each data link, while causing said repeaters to receive, for each data link, a message having an address in a first selection range; real-time data processing comprising read/write sense hardware for transferring a message having a second selected range of addresses from a first data link to a second data link and from the second data link to the first data link; Device.