GB2096369A

GB2096369A - Decentralized data processing system of modular construction

Info

Publication number: GB2096369A
Application number: GB8137049A
Authority: GB
Original assignee: Stollman & Co GmbH; TA Triumph Adler AG
Current assignee: Stollman & Co GmbH; TA Triumph Adler AG
Priority date: 1981-03-31
Filing date: 1981-12-09
Publication date: 1982-10-13
Also published as: SE8200314L; IT8124991A0; JPS57209561A; DE3112693A1; IT1140489B; NL8104891A; FR2503420A1

Abstract

The system consists of any desired number of independent computer modules (2) with equal priority and independent periphery modules (3) with equal priority, wherein a processor (5) with a local bus and store is contained in each module (2, 3). The computer modules (2) which can work out user and service programs independently by interpreting at least one program language and the periphery modules (3) which can execute independently input-output instructions, or instruction chains are operated together with a general store (4) on common asynchronous bus (1). Operations are divided between the modules (2, 3) so that each module (2, 3) contains only that instruction which it needs to fulfil its special function. Tasks which one module (2, 3) cannot perform itself are passed on via the bus, to a module (2, 3) which is specialized for the purpose. Thus both in the hardware construction and in the operating system, a modular data processing system is afforded which can be extended as desired without alteration or adaptation of the operating system. <IMAGE>

Description

SPECIFICATION Decentralized data processing system of modular construction The invention relates to a decentralized data processing system of modular construction which contains a plurality of computer modules, a plurality of periphery modules and a general store, wherein the computer modules and periphery modules may be complex systems.

In data processing, problems often have to be solved which are very input-output intensive or are dialogue-orientated. For such applications, data processing systems are often used which are composed of a plurality of processors which are operated, together with general stores, on a bus system. Such data processing systems have operating systems which are wholly or partially centralized and are hierarchical in structure, that is to say there are masterslave correlations in a fixed framework. Thus associated with the modular hardware construction is a relatively rigid operating system in which the extensibility of the data processing system within a predetermined scope up to a maximum size is possible but which has to be altered with relatively great expense in the event of extensions beyond this.

Because of their complexity, such operating systems are liable to faults and often contain unwanted dependence of their components on one another so that the alteration of one component has an effect on the other components. Apart from this considerable disadvantage, a further disadvantage is to be seen in the fact that in order to render it possible to extend the system, a correspondingly prepared operating system has to be used, as a result of which unnecessarily high costs result for small systems. It is a further disadvantage if the extension of a data processing system makes it necessary to alter the operating system, because high costs can likewise result from this. The fact that the said multi processor systems can only be extended within a predetermined fixed scope up to a maximum size must likewise be regarded as a disadvantage.

It is therefore the object of the invention to provide a data processing system which has a modular hardware construction, and which has an operating system of modular construction, so that the system can be extended without the operating system having to be changed when the system becomes larger than a given size.

According to the present invention there is provided a decentralized data processing system of modular construction, comprising a number of independent modules which are each specialized either as a computer module or as a periphery module, a general store, said general store and said modules being connected to a common, asynchronous, bidirectional bus-system the operating system of the data processing system being distributed between the individual computer and periphery modules in such a manner that the or each computer module can independently work out user and service programs by interpreting at least one program language, while the or each periphery module can independently execute input and output instructions and/or instruction chains all the modules being able to communicate with one another.

The advantages which result from the data processing system according to the invention are to be seen in particular in that as a result of the division of the operating system between independent computer modules with equal priority and independent periphery modules with equal priority, which are operated together with general stores on a common, asynchronous, bidirectional bus system and can communicate with one another, a modular extensibility is afforded without adaptation of the operating system.

The computer and periphery modules and the general store can be connected to the common bus by connection units which are alike in their hardware concept. Thus in conjunction with the features characterised in sub-claims 4, 8 and 9, logical cutting points between the local buses of the computer and periphery modules and the common bus system result which render possible a uniform communication on at relatively high logical level.

Access to the common bus is preferably determined by a bus granting strategy which operates in a decentralized manner and is controlled by the individual computer and periphery modules themselves, on the basis of giving equal priority to requests for access to the common bus by the individual modules.

Preferably the operating system is distributed between the modules so that each module contains only parts of the operating system for causing a specialised predetermined operation of the module and for communicating with the other modules. As a result of this division of the operating system between specialized modules the individual modules are less complex and so less liable to faults, and form a well-structured homogeneous system. This distribution of the operating system permits the computer and periphery modules to be structurally alike in their construction, apart from their specially allocated functions. Preferably, the modules are configured to transfer a problem that one module cannot solve by itself to another module which is specialized for the purpose, in a simple manner, that is to say at high logical level.

One example of an embodiment of the data processing system according to the invention is explained in more detail below with reference to the drawings, wherein Figure 1 shows a basic configuration of the data processing system; Figure 2 shows the bus system with the connections to a module and to a general store; Figure 3 shows a module connection unit; Figure 4 shows the connections of an active module connection control unit to the bus system; Figure 5 shows the connections of a passive module connection control unit to the bus system; Figure 6 shows a store connection unit; Figure 7 shows the connections of a store connection control unit to the bus system; Figure 8 shows a bus termination; Figure 9 shows two systems connected via bus couplers;; Figure 10 shows two bus couplers with the associated bus connections and Figure 11 shows part of a system with the central tables distributed in general stores.

Basic configuration Figure 1 shows a possible basic configuration of a data processing system of modular construction. Computer modules 2, periphery modules 3 and general stores 4 are connected to one another via a common bus system 1. The computer modules 2 and the periphery modules 3 each contain a processor 5 and a module connection unit 6 and in addition the periphery modules 3 comprise cutting points 7 for peripheral devices 8, and the cutting points 7 and peripheral devices 8 can be different in the various periphery modules 3.

Bus system The bus system 1 shown in Figure 2 consists of an address bus 12, a data bus 13, a bus for answer-back signals 14 and a control bus 1 5.

Connected to this bus system 1, as Figure 1 shows, are computer modules 2, periphery modules 3 and general stores 4. In the case of computer modules 2 and periphery modules 3, the connection is effected in the same manner through a module connection unit 6 in each case.

Connected to the active portion 6a of the module connection unit 6 via lines A are the address bus 12, via lines B the bus for answer-back signals 14 and via lines C the control bus 15. The passive portion 6b of the module connection unit 6 is connected via lines E to the address bus 12, via lines F to the bus for answer-back signals 14 and via lines G to the control bus 15. The connection of the module connection unit 6 to the data bus 1 3 via the lines D is associated both with the active portion 6a and the passive portion 6b.

The general stores 4 are each connected to the bus system 1 via a store connection unit 11 which only contains a passive portion. The connection to the data bus 13 is effected via lines H, to the address bus 12 via lines I, to the bus for answer-back signals 14 via lines J and to the control bus 15 via lines K.

The passive portions 6b of the module connection units 6 contain module registers 18 which, together with the store 19, form a common address area.

All the module connection units 6 and store connection units 11 are alike in construction for all the modules 2, 3 and for all the general stores 4 and will be described in more detail below with reference to Figures 3, 4, 5, 6 and 7.

Module connection unit In Figure 3, the bus system 1, consisting of address bus 12, data bus 13, bus for answer-back signals 14 and control bus 15, as well as a module 2 consisting of module connection unit 6 and processor 5 are illustrated.

The most important components of the module connection unit 6, their connections to one another and to the bus system 1 and to a processor bus 20 are explained in more detail below.

An address register 21 belonging to the active portion 6a of the module connection unit 6 is connected via lines A to the address bus 12 and via lines 22 to the processor bus 20. An active module connection control unit 23 is connected via lines B to the bus for answer-back signals 14, via lines C to the control bus 15 and via lines 24 to the processor bus 20 and in addition comprises, via lines 25, a connection to a status register 26 which in turn is interconnected to the processor bus 20 via lines 27 and to the passive module connection control unit 29 via lines 28.

From the data bus 13, lines D lead to a data direction control 30 which is connected via lines 31 to a data output register 32, via lines 33 to a data input register 34 and via lines 35 to the module registers 36. Lines 37 connect the data output register 32 and lines 38 connect the data input register 34 to the processor bus 20. The address bus 12 is connected via lines E to an address buffer 39 which belongs to the passive portion 6b of the module connection unit 6. A first portion 40 of the store locations of the address buffer 39 is taken via lines 41 to a comparator 42 which has a connection, via lines 43, to a switch array 44 with which the module address is set and which is connected via lines 60 to the processor bus 20.A second portion 45 of the store locations of the address buffer 39 is connected via lines 46 to an AND-gate 47, the output of which is connected via a line 48 to the comparator 42. The comparator 42 controls the passive module connection control unit 29 via a line 49. A third portion 50 of the store locations of the address buffer 39 is taken by lines 51 and the processor bus 20 is taken via lines 52 to a direction control 53 which is connected via lines 54 to the module registers 36. The passive module connection control unit 29 has a connection, via lines F, to the bus for answer-back signals and a connection via lines G to the control bus 15, furthermore, the direction control 53 is controlled via lines 56 and the module register 36 is controlled via lines 55.

The bus for answer-back signals 14 as well as the control bus 15 and its connections C, B to the active module connection control unit 23 of a module connection unit 6 are shown in Figure 4.

The lines 57, 58, 59 form the bus for answer-back signals 14 over which the answer-back signals are transmitted from an addressed passive module connection control unit. The control bus 15 is formed by the lines 61-67. The purpose of the lines 61, 62, 63 and 67 is to control the bus granting in conjunction with the active module connection control units 23. The requesting of the bus is effected through lines 62. The access to the bus is reached via lines 61,61 no2 and given up again via lines 61 n-1. The connection can be prevented from being cut off after a transfer has been effected, via the line 67. Further purposes of the line 67 will be explained later. The lines 64 and 65 are synchronizing signal lines.Line 64 transmits the master synchronizing signal, line 65 the slave synchronizing signal. The information as to whether reading or writing is to be effected is passed on by the line 66.

As can be seen from Figure 4, with the exception of the line 63, the lines 57-59 and 61-67 are connected via lines 57a-59a and 61 a-67a respectively to the active module connection. control unit 23. The function of the line 63 will be described later.

Figure 5 shows the lines 57-59 and 61-67 which form the bus for answer-back signals 14 and the control bus 15 respectively, as well as their connections to a passive module connection control unit 29. As can be seen from the drawing, only the lines 57-59 and 63-67 are taken via lines 57b-59b and 63b-67b to the passive module connection control unit 29.

In Figure 6, the bus system 1 with the address bus 12, the data bus 13, the bus for answer-back signals 14 and the control bus 15 as well as a general store 4 with a store connection unit 11, a store 9 and a store controller 10 are illustrated.

The store connection unit 11 contains a data input register 68, a data output register 69, a circuit 70 for the parity formation and error correction, an address register 71, a passive store connection control unit 73, an address changing and comparator circuit 72. The data bus 13 is connected, via lines H, to the data output register 68 and the data input register 69, from which lines 74 and lines 75 lead to the circuit 70 for the parity formation and error correction which in turn is connected, via lines 76, to the store 9 and is interconnected with the store connection control unit 73 via lines 81.

The address is applied from the address bus 12, via lines I to the address register 71 which is connected via lines 77 to an address changing and comparator circuit 72 which passes on addresses to the store 9 via lines 78 or controls the store connection control unit 73 via line 79.

The store connection unit 73 has connections via lines J to the bus for answer-back signals 14, via lines K to the control bus 15 and via lines 80 to the store 9.

Figure 7 shows the connection of the store connection control unit 73 to the bus for answerback signals 14 (lines 57, 58, 59) and to the control bus 15 (lines 61-67) via the lines 57c, 58c, 59c and 63c-66c respectively. The lines 61, 62 and 67 of the control bus remain free.

A bus termination circuit 85 for the bus system 1 is illustrated in Figure 8. It contains a circuit 82 for producing answer-back signals, a time stage 83 and a circuit 84 for passing on the bus access pulse arriving via line 61 n to the line 63. Apart from a connection to the line 61 of the first active module connection control unit 23, the line 63 comprises a connection to all the passive module connection control units 29 and store connection control units 73.

Communication With the drawings Figures 1 to 8 and with the associated descriptions, it will be shown below how the individual elements of the data processing system communicate with one another.

Looking ahead, it should be noted that a communication can only be initiated by active elements, that is to say by computer modules 2 or periphery modules 3. Thus there are 3 possibilities for the transfer of data: a) Writing in the general store; b) Reading out of the general store; c) communication between one module and another.

a) Writing in the general store In order to be able to write in the general store 4 from a computer module 2 or periphery module 3, a bus transfer is initiated by the internal processor 5 of the module 2,3. This can be effected by the fact that flags BF, WR and possibly HI are set in the active module connection control unit 23 by the processor bus 20 (Figure 3) via lines 24. The BF flag causes the active module connection control unit 23 to obtain access to the bus. This is effected by the fact that a signal is given on line 62 (Figure 4) which causes a module 2, 3, which has access to the bus, to give up the bus after termination of its transfer and sets a signal on line 61.If, between the module 2, 3 which wants access to the bus and the module 2, 3 which is giving up access to the bus, there are further modules 2, 3 which want access to the bus, then these are served first in turn ("round Robin" strategy). When the signal which is passed on by each module 2, 3 via input RRI and output RRO, finally reaches the module 2, 3 which wants the access to the bus, via the input RRI, this does not apply any signal to the output RRO as a result of which it obtains access to the bus.

Already with the initiation of the bus transfer, the addresses are loaded via lines 22 (Figure 3) and the data via lines 37 from the processor bus 20 into the address register 21 and into the data register 32 respectively. When access to the bus is achieved, the address register 21 switches the addresses via lines A to the address bus 12, the data output register 32 switches the data via lines 31, the data direction control 30 and lines D to the data bus 13, and the active module connection control unit 23 switches the status information WR and possibly HL via lines 66a, 67a (Figure 4) to the control bus 15. When all the necessary information is present in the bus system 1, a master synchronisation signal is given by the active module connection control unit 23 (Figure 3) via lines 64a (Figure 4) to the line 64 of the control bus 15.

From this point on, it is necessary to consider the operations in the module connection control unit 6 and in the addressed general store 4 separately.

General store 4 As soon as the address is on the address bus 12 (Figure 6), this is applied to the address changing and comparator circuit 72 via lines I, address buffer 71 and lines 77. This circuit translates the addresses and determines, in a comparison, whether the new address resulting from the translation corresponds to an address present in the address area of the store 9. If this is the case, the calculated address is switched to the store 9 via the line 78 and a signal is given to the store connection control unit 73 via line 79.If the line 63 (Figure 7) of the control bus 15 is not carrying any signal and the master synchronisation signal appears via line 64c and the writing signal WR via line 66c, the store connection control unit 73 then causes, in a first step, by a control signal on the lines 81 (Figure 6) the reading in of the data appearing at the data input register 69 via lines H to be effected into the circuit 70 via lines 75. The circuit 70 adds checking bits to the data and writes this, in a second step, the beginning of which is reported by the store connection control unit 73 to the circuit 70, likewise by a signal on the lines 81, in the store 9. The store connection control unit 73 gives the writing instruction for writing in the store 9 to the store 9 via lines 80. The extraction from the store is effected in the usual manner by means of the store controller 10.When the data and checking bits have been read into the store 9, the store connection control unit 73 sets a return code via lines 57c, 58c, 59c (Figure 7) on the bus for answer-back signals 14 and delivers the slave synchronisation signal to line 65c.

Module connection unit 6 After the module connection unit 6 has applied all the information to the bus system 1, it waits for a slave synchronisation signal and, on its arrival, transfers the information present on the bus for answer-back signals 14 through the lines 57a, 58a, 59a (Figure 4) into the active store connection control unit, evaluates it and writes a status information in the status register 26 via line 25 (Figure 3), where it is read by the processor 5 via lines 27 and processor bus 20 and evaluated accordingly.

The evaluation of the status information will not be considered in more detail because this may differ according to the construction of the processor 5 or according to the user program.

On the arrival of the slave synchronisation signal, the master synchronisation signal is reset, and, if the line 62 (Figure 4) is carrying a signal, the access to the bus is given up by resetting the BF flag or by a signal on line 61 no1 after the slave synchronisation signal has been cancelled. The surrender of the access to the bus is not effected, however, if the HL flag is set in the active module connection control unit 23 (Figure 3). This means that a locking of the bus is effected by the set HL flag and so the possibility of an exclusive access to the general store 4 is afforded for more than one access cycle ("Read-Modify-Write" access).

b) Reading out of the general store In order that a computer module 2 or a periphery module 3 may be able to read information deposited in the general store 4, it is first necessary for the module 2, 3 in question to have access to the bus. The steps for obtaining access to the bus are the same as described under point a) with the exception that the WR flag is not set.

When the module 2, 3, which is to read out of the general store, receives access to the bus, the addresses which have been in the address register 21 (Figure 3) since the initiation of the bus transfer, are switched via lines A and the status information WR and possibly HL is switched from the active module connection control unit 23 via lines 66a and 67a (Figure 4) to the bus system 1.

From this point on, the operations in the general store 4 and in the module connection unit 6 will be considered separately.

General store 4 Here too, the first steps up to the point where the address translating and comparator circuit 72 has recognized the fact that it is a question of an address which is present in the store 9, are the same as described under point a).

The store connection control 73 (Figure 6), on arrival of the signal from the address translating and comparator circuit 72 via line 79, checks via the lines 63c and 64c (Figure 7) whether there is no signal on line 63 of the control bus 15 and line 64 is carrying a signal. If this is the case, and if it is recognized, via line 66c, that reading is to be effected from the general store, then the store connection control unit 73 (Figure 6), via lines 80, 81, in a first step, causes the store contents addressed by the address translating and comparator circuit 72, via lines 78, in the store 9, to be read out to the circuit 70 via lines 76. In a second step, the circuit 70 checks whether there is an error in the data read out. If this is the case, an error correction is carried out, if possible, by the circuit 70. The corrected data are also written back into the store 9. If the error cannot be corrected, this is reported to the store connection control unit 73 via lines 81.

After termination of the error correction operation, in a third step, the beginning of which, like the beginning of the first two steps, is controlled by the store connection control unit 73 via lines 81 , the data is passed out of the circuit 70 via lines 74 into the data output register 68 and so via lines H to the data bus 13. At the same time, the store connection control unit 73 applies the return code to the bus for answer-back signals and then delivers the slave synchronisation signal via line 65c (Figure 7) to line 65.

Module connection unit 6 From the moment when the module connection unit 6 has switched all the information (addresses, status information) to the bus system 1, the active module connection control unit 23 waits for a slave synchronisation pulse. When this arrives via line 65, 65a (Figure 4), the status information, which is present on the bus for answer-back signals 14, is transferred via lines B into the active module connection control unit 23, evaluated and the result is written, via lines 25 (Figure 3) in the status register 26 where it is read by the processor 5 via lines 27 and the processor bus 20.

At the same time, a transfer of the data on the data bus 13 is effected via lines D, data direction control 30 and lines 33 into the data input register 34 and from there via lines 38 to the processor bus 20.

The surrender of access to the bus is effected as described under point a) in the last paragraph.

c) Communication between one module and another For the communication between two modules 2, 3, it is necessary for each processor 5 to know its own module address, which can be selected freely by the switch array 44. If necessary, this can be called up via lines 60 and processor bus 20.

If a bus transfer, which generally comprises a plurality of writing operations, is initiated from a processor 5 to a receiver module 2, 3, access to the bus must be obtained by the module connection control unit 23. This is effected in the same manner as already described under point a).

During a transfer from a transmitter module 2, 3 to a receiver module 2, 3, the HL flag is always set in the active module connection control unit 23.

If there is access to the bus, the addresses and data already written in the address register 21 or in the data register 32 of the transmitter module 2, 3 on the initiation of the transfer are applied, together with the status information WR, HL and the somewhat delayed master synchronisation signal from the active module connection control unit 23, via lines A, D, C, (Figure 2), to the bus system 1. From there, the addresses arrive via address bus 12 and line E at the address buffers 39 (Figure 3) of all the modules 2, 3. These conduct a portion 45 of the address bit via lines 46 to a gate circuit 47 which, if it is a case of a module address, via line 48 impulses a comparator 42 which then takes over a portion 40 of the address bit via line 41 and compares it with the address which it receives via lines 43 from the switch array 44.If the comparison shows coincidence, a signal is transmitted via line 49 to the passive module connection control unit 29 of the receiver module 2,3 which has the effect that, if the status information WR, HL is present via lines 66b, 67b (Figure 5), the status register 26 is interrogated by the passive module connection control unit 29 (Figure 3) via lines 28 to find out whether the module registers 36 are empty. If this is not the case, the return code "module not ready" is applied by the passive module connection control unit 29 of the receiver module 2, 3 to the bus for answer-back signals 14 and the slave synchronisation signal is applied via line 65b to line 65 of the control bus 15. If the module registers 36 are empty, the passive module connection control unit 29 sets a P-flag.

By means of the set P-flag, the direction control 53, which normally connects the lines 52 to the lines 54, is switched over via line 56 so that the lines 51 are connected to the lines 54. In a next control step, the passive module connection control unit 29, via line 55, causes the data on the data bus 13 to be taken via lines D, data direction control 30 and lines 35, into a module register 36a of the module registers 36, which is addressed via the address bus 12, the portion 50 of the address buffer 39, lines 51, direction control 53 and lines 54. After the data have been taken into the module register 36a, the passive module connection control unit 29 sets the return code via lines F on the bus for answer-back signals 14 and delivers the slave synchronisation signal via line 65b (Figure 5) to the line 65 of the control bus 15.As soon as the slave synchronisation signal appears via line 65a (Figure 4) at the active module connection control unit 23 of the transmitter module 2, 3, this takes over the return code present on the bus for answer-back signals 14 via lines B, evaluates it, writes the result in the status register 26 via line 25 (Figure 3) and resets the master synchronisation signal. The access to the bus is not given up, through the set HL-flag, even on inquiry by another module 2. 3 (Figure 2) via line 62 (Figure 4). The reason for this is that the information deposited in the status register must first be read by the processor 5 (Figure 3) so that this receives an answer back concerning the course of the transfer attempt. As already mentioned, a communication from the transmitter module 2, 3 to the receiver module 2, 3 consists of a plurality of writing operations.If the processor 5 of the transmitter module 2,3 has obtained the information, through the data in the status register, that no error has occurred during the first writing attempt, it increases the address and transmits this via the processor bus 20 and line 22 into the address register 21 of the active module connection control unit 6a. New data are transmitted to the data output register 32 via the processor bus 20 and line 37 and a fresh writing operation is carried out as already described above. As a result of the increasing of the address, the next module register is addressed in the passive module connection unit 6b of the receiver module 2, 3. Further writing operations can follow.

In the event that an error has occurred during the transfer attempt or that no more data are to be transmitted, the transfer is ended as a result of the fact that the active module connection control unit 23 of the transmitter module 2, 3 resets the HL-flag. As a result, the bus system 1 is freed for access by another module 2, 3.

As soon as the HL flag is reset, that is to say as soon as no signal is any longer applied via line 67a (Figure 4), lines 67 and lines 67b (Figure 5) to the passive module connection control unit 26 of the receiver module 2, 3 (Figure 2), the P flag in the passive module connection unit 29 (Figure 3) is-reset, as a result of which the direction control 53 is switched over, via line 56, so that the module registers 36 can be interrogated by the processor 5 via lines 54, lines 52 and processor bus 20.

With the resetting of the P flag in the passive module connection unit 29, an item of information is deposited in the status register 26, via lines 28, which ensures that the module 2, 3 does not receive a transfer inquiry from another module 2, 3 until the contents of the module registers 36 have been interrogated by the processor 5 via the processor bus 20, lines 52, direction control 53 and lines 54. After the processor 5 has read all the module registers 36, it erases the information stored in the status register 26, via the processor bus 20 and lines 27, so that the module registers 36 and hence the modules 2, 3 can be addressed again.

Operation of the bus termination circuit 85 Every time an active module connection control unit 23 delivers a master synchronisation signal to the line 64 of the control bus 15, a time stage 83 is started in the bus termination circuit 85 (Figure 8) and is reset as soon as a slave synchronisation signal from any passive module connection control unit 29 or store connection unit 73 appears on the line 65. If the slave synchronisation signal remains absent for a predetermined period of time, the time stage 83 controls, via line 86, a circuit 82 for producing a return code which delivers a return code "address error" to the lines 57, 58, 59 of the bus for answer-back signals 14. At the same time, the time stage 83 is reset via line 87.

The purpose of the circuit 84 contained in the bus termination circuit 85 is to produce the bus access pulse when the system is switched on and to apply it to the lines 63 and 61 or, during operation, to switch on the bus access pulse from line 61 n via line 63 to line 61. Whenever a signal appears on line 63, all the passive module connection control units 29 or store connection units 73 ignore an inquiry.

Bus couplers In order to extend a data processing system of the kind described above, there is the possibility of connecting this to one or more further data processing systems via bus couplers. Such a coupling of two systems is shown in Figure 9. A first system 88, consisting of bus system 1 a, computer modules 2, periphery modules 3, general stores 4 and a bus termination circuit 85, is connected, via a bus coupler 90, to a second system 89, consisting of a bus system 1 b, computer modules 2, periphery modules 3, general stores 4 and a bus termination circuit 85, which in turn is connected, via a bus coupler 91, to the first system 88.

In Figure 10, two bus couplers 90, 91 are illustrated which each consist of a store 92a, 92b, a passive bus-coupler control unit 931, 93b and an active bus-coupler control unit 94a, 94b. The passive bus-coupler control unit 93a is connected, via lines 95 to the address bus 12a and via lines 96 to the control bus 15a of a bus system 1 a. The active bus-coupler control unit 94a, which is connected to the passive buscoupler control unit 93a, comprises a connection to a bus switch 98 via control line 97 and is connected via line 99 to the control bus 15b and via lines 114 to the bus for answer-back signals 14b of a bus system 1 b.

Lines 100 connect the passive bus-coupler control unit 93b to the address bus 12b and lines 101 connect it to the control bus 15b of a bus system 1 b. The active bus-coupler control unit 94b, which is interconnected with the passive bus-coupler control unit 93b, comprises connecting lines 102 to the control bus 15a and connecting lines 11 5 to the bus for answer-back signals 14a of the bus system 1 a and is connected to the bus switch 98 via lines 103.

Lines 104 connect the address bus 12a, lines 105 connect the data bus 13a and lines 106 connect the bus for answer-back signals 14a to the bus switch 98, which is connected via lines 107 to the address bus 12b, via lines 108 to the data bus 13b and via lines 109 to a bus for answer-back signals 14b.

The store 92a contains a copy of all the addresses in the data processing system 89 (Figure 9) which can be reached via the bus system 1 b, conversely, in the store 92b, a copy of all the addresses is stored which can be addressed via the bus system 1 a in the data processing system 88 (Figure 9).

A transfer from a module 2. 3 of the data processing system 88 (Figure 9) via the bus coupler 90 to a module 2, 3 or general store 4 of the data processing system 89 will be described briefly below with reference to Figures 9 and 10.

If a transfer request is effected by a module 2, 3 of the data processing system 88 (Figure 9) by applying the addresses, the data and the status information WR and WR and possibly HL to the bus system 1 a, to an address which is in the store 92a of the passive bus-coupler control unit 93a, this immediately sets a slave synchronisation signal on line 65 and causes the active buscoupler control unit 94a to procure access to the bus system 1 b via lines 99. If the active buscoupler control unit 94a has access to the bus, it causes the bus switch 98 to switch through via lines 97. In this manner, the address bus 12a, the data bus 13a and the bus for answer-back signals 14a are inter-connected via lines 104,105,106 with the bus switch 98 and via lines 107, 108, 109 with the address bus 12b, the data bus 13b and the bus for answer-back signals 14b. The control bus 15a is connected via lines 96, the passive bus-coupler control unit 93a, the active bus-coupler control unit 94a and lines 99 to the control bus 1 Sb.

After all the connections have been established, the passive bus-coupler control unit 93a cooperates with the bus switch 98 in relation to the bus system 1 a and the active bus-coupler control unit 94a cooperates with the bus switch 98 in relation to the bus system 1 b, in each case as an extension of the bus 1 a or 1 b, so that the further transfer can take place as described under a), b) or c).

The surrender of the connection between bus system 1 a and bus system 1 b is effected as a result of the fact that the slave synchronisation signal on the control bus 15b is cancelled, as a result of which the passive bus-coupler control unit 93a likewise resets the slave synchronisation signal on the control bus 1 5a. (Cancellation of the slave synchronisation signal with no HL flag set, means that access to the bus is made available).

A transfer from a module 2, 3 connected to the bus system 1 b to a module 2, 3 or general store 4 which is operated on the bus system 1 a is effected as described above, via the bus coupler 91.

In order to avoid a jamming of the system in the event of a simultaneous transfer request by both bus couplers to the other bus, a different priority must be assigned to the bus couplers 90, 91 or to the data processing systems 88, 89, so that the bus coupler with the lower priority gives up the transfer request so that the other transfer can be carried out. In order to recognize a conflict, the two bus couplers 90, 91 have a connection (not illustrated) and are connected to the buses for answer-back signals 1 4b, 1 4a by lines 114 and 11 5 for the purpose of putting an end to the conflict. A plurality of bus couplers on one bus are possible, likewise the coupling beyond a plurality of buses.

Method of operating the data processing system Before going in more detail into a method of operating the data processing system described above, in an example, some preliminary remarks are necessary.

As already mentioned, the present data processing system is a flexible system of modular construction, consisting of a plurality of computer modules 2, periphery modules 3, general stores 4, a bus termination circuit 85 and possibly one or more bus couplers 90, 91 which are connected to one another via a common bus system 1. Within this system there is no hierarchical structure. Thus there are no master-slave functions. Apart from the fact that they use common general stores 4, all the active units, that is to say computer modules 2 and periphery modules 3, are completely autonomous computer units which mutually assign tasks to one another according to the requirements of the user program. The general stores 4 can be regarded as passive elements and do not have their own processors.

In principle, the number of modules 2, 3 or of general stores 4 can be extended as desired because the operating system is divided between the computer modules 2 and periphery modules 3 so that each module 2, 3 only contains the parts which are necessary for its operation and to secure a uniform communication. In extensive devices, however, it is logical to split up the bus system into smaller component systems by bus couplers 90, 91 in order to obtain tolerable bus access times.The component systems consist of a plurality of computer modules 2, periphery modules 3, general stores 4, bus couplers 90. 91 and a bus termination 85 and work substantially autonomously, that is to say they only encroach relatively seldom on other component systems via bus couplers 90, 91, as a result of which the bus sections are almost completely decoupled.

Furthermore there is the possibility of overall addressing, that is to say each store location in the general stores 4 and each module register can be addressed via each active element (computer module 2, periphery module 3), and this, of course, also applies beyond the bus couplers into other component systems.

If bus couplers 90, 91 are used it is necessary for a different priority to be allocated to the individual component systems, in order to avoid jamming of the system.

In order to make the system operable, it is necessary for a preliminary start first to be carried out to define the whole system because at the moment of switching on, the individual modules 2, 3 do not have any information as to which computer modules 2, periphery modules 3 and general stores 4 are connected to the bus system 1.

The course of the preliminary start will be described below with reference to Figures 1-10 and in particular Figure 11.

When the data processing system is switched on, a resetting of the bus and all the modules 2, 3, general stores 4, bus couplers 90, 91 and the bus termination 85 connected thereto is first effected.

As soon as the individual modules 2, 3 are in an electrically defined initial state, they begin with a self test in the course of which the internal stores and the periphery cutting points are checked for operational efficiency.

After the self tests have been concluded, a module 3X, which has identified itself with the aid of its address, temporarily takes over the control.

First it seeks the initial address of the general store 4 by trial addressing in suitable steps. In the case of addresses not present in the store, the bus termination 85 delivers the return code "address error" to the bus system 1 after a preselected delay time, after which a fresh attempt is made with an altered address. As soon as the initial address of the general store 4 has been found, the module 3X, beginning with the initial address, plots a first central system table 110 and then a second central table 111 , the initial address of which is stored in the first central system table 110.

After the plotting of the tables 110, 111, the module 3X begins to search systematically through the address area of the general store 4 to find out under which addresses store locations are actually available. As soon as the first available store location has been found, its address is deposited in the central system table 11 0. Since gaps may occur in the address area of the general store 4, for example through unoccupied stores, each address of the generalstore address area is interrogated.If the module 3X comes to a gap during this operation, the length of the preceding store block 112 is stored and the initial address of the next following store block 11 3 is stored below the first address of the preceding store block 11 2. Thus a reference chain results which is anchored in the first central system table 110.

After termination of this operation, that is to say after the address area of the general store has been searched through completely, the module 3X begins to send information to all possible module addresses, including its own, which information contains the initial address of the first central system table 110 and the instruction to enter itself in the second central table 111. If a receiver is not present, the transfer attempt is broken off by the bus termination 85.

The modules 2, 3, 3X addressed by the module 3X store the initial address of the first central system table 110 and begin to enter their own addresses and information relating to the modules, for example whether they are a computer module 2 or a periphery module 3 and which peripheral equipment 8 they serve, in the second central table 111. In this manner a complete reproduction of the whole device results in the first central system table 110 and in the second central table 111.

The preliminary start is terminated with the entry of the modules 2, 3 3X in the second central table 111. From this moment on, the modules 2, 3, 3X await requests by the operator or by a user program.

With the preliminary start routine or autoconfiguration described above, the possibility is afforded of starting any desired system device automatically, without operator intervention, by depositing a configuration description accessible to all active elements in the form of interlinked system tables in the general store. At the same time a kind of diagnosis of the whole system is effected because all the store locations of the general store 4 and all the modules 2, 3 are addressed. In this manner, any store locations or modules which are not present or defective can be excluded from the system from the beginning.

The autoconfiguration is, of course, also possible in systems which contain bus couplers.

In this case, however, the configuration description of the system coupled up must be stored in the bus couplers.

Working out a user program By means of a preliminary start routine, the data processing system is brought into a state in which it can work out user programs.

An instruction to work out a user program is given to the proper periphery module 3 which contains the logical operator cutting point, via an input-output device which is capable of dialogue.

In the next step, the addressed periphery module 3 deposits the process guide block in the general store 4 and by means of an order language causes a computer module 2 to prepare an interpreter.

The interpreter orders a certain periphery module 3, named by the operator, to load the user program deposited in a specific peripheral device, for example a floppy unit, into the general store.

During this operation, the control blocks already plotted are amplified.

When all the information necessary for working out a user program is present in the general store, the computer module 2 begins to interpret the program independently. If, in the course of the program, tasks arise which the interpreter cannot perform itself, such as input-output operations or changing the program language, then the interpreting computer module 2 independently commisions another module 2, 3, which is specialized in the task in question, to take this over or to continue with the interpretation of the program.

In order to pass a task from one module 2, 3 to another module 2, 3, an order language is used, as already mentioned, by means of which a transmitter module 2,3 passes on an order to a receiver module and at the same time informs this where the data structures necessary for working out the task are to be found.

As can be seen from the above, great importance is attached to the passing of orders from one module 2, 3 to another in the present data processing system, because the individual modules 2, 3 represent relatively small specialized units. It is therefore necessary, as the description shows, for the system to form a homogeneous unit both in the hardware and in the software, which unit can, however, as likewise shown, be extended as desired, without adaptation, while retaining the homogeneous construction.

Claims

1. A decentralized data processing system of modular construction, comprising a number of independent modules which are each specialized either as a computer module or as a periphery module, a general store, said general store and said modules being connected to a common, asynchronous, bidirectional bus-system, the operating system of the data processing system being distributed between the individual computer and periphery modules in such a manner that the or each computer module can independently work out user and service programs by interpreting at least one program language, while the or each periphery module can independently execute input and output instructions and/or instruction chains, all the modules being able to communicate with one another.

2. A data processing system as claimed in claim 1 , wherein each of the modules includes a local processor bus which is connected to the common, asynchronous, bidirectional bus system, via a respective module-connection unit including an active portion and a passive portion so arranged that the common bus system and the local buses of the computer and periphery modules form a hierarchy wherein the modules work substantially simultaneously and asynchronously.

3. A data processing system as claimed in claim 2, wherein all the module connection units are alike in construction.

4. A data processing system as claimed in claim 2 or 3, wherein each said module connection unit contains in its passive portion, module registers which, together with the general store form a common address area.

5. A data processing system as claimed in claim 2, wherein each computer and periphery module can respectively request access to the common bus system through the active portion of a module connection unit, the bus granting being effected in succession so that the bus access is passed on, always in the same direction along the common bus, from module to module so as to grant the bus access to that module which has requested access to the common bus and which is closest to the module which last had access to the common bus.

6. A data processing system as claimed in claim 5, wherein each said module which has access to the common bus automatically makes this available again after a data transmission operation thereby along the bus.

7. A data processing system as claimed in claim 6, wherein each said module can prevent the automatic making available of access to the bus, by locking up the bus, so that an exclusive access to the bus by one module can be realized over a given number of transmission operations.

8. A data processing system as claimed in any preceding claim, wherein the operating system is distributed between the modules so that each module contains only parts of the operating system for causing a specialised predetermined operation of the module and for communicating with the other modules.

9. A data processing system as claimed in any preceding claim, wherein the modules are configured to give orders to one other by means of an order language, to work out a task defined by user and/or service programs, the orders containing information as to where the data structures necessary for working out task are to be found.

10. A data processing system as claimed in claim 4, wherein the communication between one said module and another is effected exclusively via storage cells available in the common address area.

11. A data processing system as claimed in any preceding claim, wherein the system comprises substantially independent asynchronous component systems each component system having a respective said common bus, the common buses being interconnected by a bus coupler, jamming of the system being prevented by allocating different priorities to the component systems the priorities being in the bus coupler.

12. A data processing system as claimed in one or more of the preceding claims, wherein when any desired system device is connected into the general store tables are automatically drawn up which contain an accurate copy of the whole system device and are interlinked, the initial address of the linked tables being automatically imparted to each module.

13. A data processing system as claimed in one or more of the preceding claims, wherein the or each said computer module is adapted to process a plurality of user and/or service programs, interlaced in time.

14. A data processing system as claimed in one or more of the preceding claims, characterised in that each periphery module manages a plurality of peripheral devices.

15. A data processing system as claimed in one or more of the preceding claims characterised in that the computer modules and periphery modules connected to the bus system are structurally alike in their construction apart from their special functions, so that the operating systems of the individual modules have similarity in their essential parts.

1 6. A data processing system substantially as hereinbefore described with reference to the accompanying drawings.