JPS6151578A - Fault diagnostic system of electronic circuit device - Google Patents

Fault diagnostic system of electronic circuit device

Info

Publication number
JPS6151578A
JPS6151578A JP59173868A JP17386884A JPS6151578A JP S6151578 A JPS6151578 A JP S6151578A JP 59173868 A JP59173868 A JP 59173868A JP 17386884 A JP17386884 A JP 17386884A JP S6151578 A JPS6151578 A JP S6151578A
Authority
JP
Japan
Prior art keywords
circuit
diagnostic
diagnosis
data
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59173868A
Other languages
Japanese (ja)
Inventor
Shoji Tanaka
田中 昌治
Shige Matsuo
松尾 樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59173868A priority Critical patent/JPS6151578A/en
Publication of JPS6151578A publication Critical patent/JPS6151578A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To allow a host device to diagnose every slave device in detail by adding a bus dedicated to diagnosis and a control circuit for diagnosis. CONSTITUTION:The control circuit 101 of the host device 1 controls normal operation and has a diagnostic control program for controlling diagnostic control circuits 201 of slave devices 20. When a diagnosis is taken, the circuit 101 sends out a diagnostic command by the circuit 201 through a diagnostic dedicated bus 4, and the circuit 201 decides whether a diagnostic display is requested one or not from the address in sent data. The circuit 201 sends out diagnostic data to an input/output circuit 202 through a terminal 204 and data appearing at a terminal 205 is read and analyzed to diagnose the normalcy of the circuit 202. Similarly, the normalcy of logical circuits 2031 and 2032 is diagnosed and the circuit 201 diagnoses all elements in the device and then reports the diagnostic result to the circuit 101 of the device 1 together with its address, so that the result is displayed 208 when a fault occurs. The circuit 101 analyzes the reported data to control the presence/absence state of a fault as to each slave device.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、′電子回路装置の障害診断方式に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for diagnosing faults in electronic circuit devices.

(従来の技術) 第2図は、従来技術による雷、子回路装はの障害診断方
式を説明するためのブロック図である。
(Prior Art) FIG. 2 is a block diagram for explaining a fault diagnosis method for lightning and sub-circuit devices according to the prior art.

第2図にお込て、lは上位電子回路装置、20゜21は
それぞれ下位電子回路装刀、3はデータバスである。1
01はプログラム制御により下位装置を制御するための
制御回路であり、通常動作用のプログラムおよび障害と
なった下位装置を調べるための診断プログラムを備えて
いる。
In FIG. 2, 1 is an upper electronic circuit device, 20° and 21 are lower electronic circuit devices, and 3 is a data bus. 1
Reference numeral 01 denotes a control circuit for controlling a lower-order device by program control, and includes a program for normal operation and a diagnostic program for checking a lower-order device that has caused a problem.

102は下位装置との間の各種データを送受するだめの
入出力回路である。202は入出力装置102・と同様
な構成を有する入出力回路、203は制御回路101の
指示によシ各種の動作を行うための論理回路である。
Reference numeral 102 is an input/output circuit for transmitting and receiving various data to and from lower-level devices. 202 is an input/output circuit having a configuration similar to that of the input/output device 102; 203 is a logic circuit for performing various operations according to instructions from the control circuit 101;

第2図において、下位のいずれかの電子回路装置20 
、21に障害が生じた場合には診断全行って障害箇所を
判定する必要がある。しかし、従来の診断方式では上位
装置1に備えられた制御回路101の内部の診断プログ
ラムにより、通て下位装置20 、21に診断データを
与え、各下位装置20 、21では与えられた診断デー
タに応じて論理回路203ヲ動作させ、動作結果を入出
力回路202を経由して上位装置1に送出していた。上
位装置1に備えられた制御回路101では返送されてき
たデータを読取ることにより、障害が発生した下位装置
を判定することができるものであった。
In FIG. 2, one of the lower electronic circuit devices 20
, 21, it is necessary to perform a complete diagnosis to determine the location of the failure. However, in the conventional diagnostic method, a diagnostic program inside a control circuit 101 provided in a higher-level device 1 provides diagnostic data to lower-level devices 20 and 21, and each lower-level device 20 and 21 uses the provided diagnostic data. Accordingly, the logic circuit 203 is operated and the operation result is sent to the host device 1 via the input/output circuit 202. By reading the returned data, the control circuit 101 provided in the higher-level device 1 was able to determine which lower-level device has experienced a failure.

(発明が解決しようとする問題点) 従って、下位装置では上位装置の制御回路から送出され
る診断指令により通常の論理動作と同じ動作を行ってい
ると同時に、上位装置の制御回路では下位の被診断論理
回路全分割して各部分の動作を調査できないため、論理
回路のすべての動作を調べることができず、診断結果が
正常であると判定されても、実際には多重障害が潜在化
し、検出できないことが多いと云う欠点があった。
(Problem to be Solved by the Invention) Therefore, the lower-level device performs the same operation as normal logical operation based on the diagnostic command sent from the control circuit of the higher-level device, and at the same time, the control circuit of the higher-level device performs the same operation as the normal logical operation. Since it is not possible to divide the entire diagnostic logic circuit and examine the operation of each part, it is not possible to examine all the operations of the logic circuit, and even if the diagnosis result is determined to be normal, multiple failures may actually be latent. The drawback is that it is often undetectable.

本発明の目的は、上位の電子回路@置と下位の電子回路
装置との間に通常動作に使用されるバスとは分離して診
断専用バスを設け、さらに下位装置の内部に診断用制御
回路を設け、この診断用制御回路に上位装閲内の制御回
路から診断専用バスを経由して診断指示を与えることに
よシ上記欠点を除去し、下位装置内の論理回路を細部に
わたり診断し、障害の潜在化を防ぎ、精度の高い診断全
できるように構成し九電子回路装置障害診断方式を提供
することにある。
An object of the present invention is to provide a dedicated diagnostic bus between a higher-level electronic circuit and a lower-level electronic circuit device, separate from a bus used for normal operation, and further provide a diagnostic control circuit inside the lower-level device. The above-mentioned drawbacks are eliminated by providing a diagnostic control circuit with diagnostic instructions from the control circuit in the higher-level equipment via the diagnostic bus, and diagnosing the logic circuits in the lower-level equipment in detail. It is an object of the present invention to provide a nine-electronic circuit device failure diagnosis system configured to prevent failures from becoming latent and to perform highly accurate diagnosis.

(問題点を解決するための手段) 本発明による電子回路装置障害診断方式は上位装置と、
複数の下位装置と、バスとを具備して構成することによ
り実現したものである。
(Means for Solving the Problems) The electronic circuit device failure diagnosis method according to the present invention includes a host device,
This is realized by configuring the system to include a plurality of lower-level devices and a bus.

上位装置は、制御回路ならびに一対の入出力回路を備え
たものである。
The host device includes a control circuit and a pair of input/output circuits.

複数の下位装置は、それぞれ論理回路、一対の入出力回
路、ならびに上記装置からの診断指示を与える指令によ
って内部電子回路の動作の正常性を診断するための診断
用制御回路全備えたものである。
Each of the plurality of lower-level devices is equipped with a logic circuit, a pair of input/output circuits, and a diagnostic control circuit for diagnosing the normality of the operation of the internal electronic circuits based on commands that give diagnostic instructions from the device. .

バスは上位装置と複数の下位装置との間に設けてあり、
一対の入出力回路によって上記両芸置間全インターフェ
ースすることができるデータバス力らびに診断専用バス
より成るものである。
A bus is provided between a higher-level device and multiple lower-level devices,
It consists of a data bus and a diagnostic bus that can perform all the interfaces between the above-mentioned devices through a pair of input/output circuits.

(実 施 例) 次に、本発明の実施例について図面を8照して詳細に説
明する。
(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明による電子回路装置診断方式を実現する
ための一実施例を示すブロック図である。第1図におい
て、l 、 20.23.101 。
FIG. 1 is a block diagram showing an embodiment of the electronic circuit device diagnostic method according to the present invention. In FIG. 1, l, 20.23.101.

102 、202 、212 、3はそれぞれ第2図と
同様な要素を示す記号である。いっぽう、201はプロ
グラム制御により自装置内の論理回路を診断するための
診断用制御回路、  2031 、2032はそれぞれ
論理回路、208は障害表示ランプ、4は診断専用バス
である。
102, 202, 212, and 3 are symbols indicating the same elements as in FIG. 2, respectively. On the other hand, 201 is a diagnostic control circuit for diagnosing a logic circuit within the device itself under program control, 2031 and 2032 are logic circuits, 208 is a fault indicator lamp, and 4 is a diagnostic bus.

上位装置llの制御回路101は通常動作を制御するた
めのプログラムを備えると共に下位装置の診断用制御回
路を制御するための診断管理プログラムを備えている。
The control circuit 101 of the higher-level device 11 is equipped with a program for controlling normal operation and a diagnostic management program for controlling the diagnostic control circuit of the lower-level device.

診断実行時には制御回路101は下位装置20の診断用
制御回路201に診断専用バス4を介して診断指令を送
出する。診断用制御回路201は送出されてきたデータ
全分析し、送られてきたデータ内のアドレスによす診断
指示が自分に要求されたものか否かを判定する。判定結
果により診断を要求された診断用制御回路201ではプ
ログラム制御によυ自装置内の論理回路をいくつかの部
分に分け、71g?追って各部分の動作の正常性を診断
する。診断用制御回路201は端子204?介して入出
力回路202に診断データを送出し、端子205に現わ
れるデータ″f:読取って分析し、入出力回路202の
正常性を診断する。同様にして、端子205と端子20
6との間に!かれた論理回路2031の正常性を診断し
、さらに端子205と端子207との間に置かれた論理
回路2032の正常性を診断する。診断用制御回路20
1は装置内の全部分を診断した後、診断結果が正常であ
るか、あるいは障害であるかを自身のアドレスを付加し
て上位装置1の゛制御11回路101に報告すると共に
1.障害時には障害表示ランプ208f点灯する。制イ
餌・回路10・lでは報告さね、たデータを分析し、各
下位装置ごとに障害の有無′f−管理する。
When executing a diagnosis, the control circuit 101 sends a diagnosis command to the diagnosis control circuit 201 of the lower-order device 20 via the diagnosis dedicated bus 4. The diagnostic control circuit 201 analyzes all of the sent data and determines whether the diagnostic instruction given to the address in the sent data is what it requested. The diagnostic control circuit 201, which is requested to perform diagnosis based on the determination result, divides the logic circuit in its own device into several parts under program control, and performs 71g? Then, diagnose the normality of the operation of each part. Is the diagnostic control circuit 201 connected to the terminal 204? The diagnostic data is sent to the input/output circuit 202 through the input/output circuit 202, and the data "f" appearing at the terminal 205 is read and analyzed to diagnose the normality of the input/output circuit 202. Similarly, the terminal 205 and the terminal 20
Between 6 and 6! The normality of the logic circuit 2031 placed between the terminals 205 and 207 is further diagnosed. Diagnostic control circuit 20
After diagnosing all parts in the device, 1.1 reports whether the diagnosis result is normal or faulty to the control 11 circuit 101 of the host device 1 by adding its own address. In the event of a failure, the failure indicator lamp 208f lights up. The control circuit 10.1 analyzes the reported data and manages the presence or absence of a failure for each lower-level device.

(発−〇効、果) 本発明は以上説明したように、診断専用バスおよび診断
用1i111回路を付加して構成することにより、上位
装置は各下位装置ととに詳細に診断を実行できると共に
、各装置ごとの障害切り分けを容易rすることができる
と云う効果がある。
(Effects and Effects) As explained above, the present invention is configured by adding a dedicated diagnostic bus and a 1i111 circuit for diagnosis, so that a higher-level device can perform detailed diagnosis with each lower-level device. This has the advantage that fault isolation for each device can be easily identified.

【図面の簡単な説明】[Brief explanation of drawings]

第】図は、本発明による電子回路装置障害診断方式を実
現するための一実施例を示すブロック図である。 第2図は、従来技術による電子回路装置障害診断方式を
実現するための構成例を示すブロック図である。 1・・・上位装置i   101,201・・・制御回
路1.02,202・・・入出力回路 70’ 、 71−一下位装置 ?σ、1. 、203X 、 2032・・・倫理回路
208・−・障害表示ランプ 204〜207・−・端子
FIG. 1 is a block diagram showing an embodiment of the electronic circuit device failure diagnosis method according to the present invention. FIG. 2 is a block diagram showing an example of a configuration for implementing a conventional electronic circuit device failure diagnosis method. 1... Upper device i 101, 201... Control circuit 1.02, 202... Input/output circuit 70', 71-1st lower device? σ, 1. , 203X, 2032...Ethical circuit 208...Fault indicator lamps 204-207...Terminal

Claims (1)

【特許請求の範囲】[Claims] 制御回路ならびに一対の入出力回路を備えた上位装置と
、それぞれ論理回路、一対の入出力回路、ならびに前記
上位装置からの診断指示を与える指令によつて内部電子
回路の動作の正常性を診断するための診断専用制御回路
を備えた複数の下位装置と、前記上位装置と前記複数の
下位装置との間に設けてあり、前記一対の入出力回路に
よつて前記上位ならびに下位装置の間をインターフェー
スすることができるデータバスならびに診断専用バスよ
り成るバスとを具備して構成することにより実現したこ
とを特徴とする電子回路装置障害診断方式。
Diagnosing the normality of the operation of internal electronic circuits by a host device including a control circuit and a pair of input/output circuits, a logic circuit, a pair of input/output circuits, and a command giving a diagnosis instruction from the host device. A plurality of lower-order devices are provided between the higher-order device and the plurality of lower-order devices, and the pair of input/output circuits provide an interface between the upper and lower-order devices. What is claimed is: 1. A fault diagnosis method for an electronic circuit device, characterized in that the method is realized by comprising a data bus capable of performing a diagnostic operation and a bus consisting of a diagnostic bus.
JP59173868A 1984-08-21 1984-08-21 Fault diagnostic system of electronic circuit device Pending JPS6151578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59173868A JPS6151578A (en) 1984-08-21 1984-08-21 Fault diagnostic system of electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59173868A JPS6151578A (en) 1984-08-21 1984-08-21 Fault diagnostic system of electronic circuit device

Publications (1)

Publication Number Publication Date
JPS6151578A true JPS6151578A (en) 1986-03-14

Family

ID=15968620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59173868A Pending JPS6151578A (en) 1984-08-21 1984-08-21 Fault diagnostic system of electronic circuit device

Country Status (1)

Country Link
JP (1) JPS6151578A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01140834A (en) * 1987-11-27 1989-06-02 Nec Corp System for detecting communication fault
US5808102A (en) * 1992-12-23 1998-09-15 Bristol-Myers Squibb Company Phosphorus bearing taxanes intermediates
US6365750B1 (en) 1995-03-22 2002-04-02 Bristol Myers Squibb Comp. Methods for the preparation of taxanes using oxazolidine intermediates
US6906040B2 (en) 2000-09-22 2005-06-14 Bristol-Myers Squibb Company Method for reducing toxicity of combined chemotherapies

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01140834A (en) * 1987-11-27 1989-06-02 Nec Corp System for detecting communication fault
US5808102A (en) * 1992-12-23 1998-09-15 Bristol-Myers Squibb Company Phosphorus bearing taxanes intermediates
US6090951A (en) * 1992-12-23 2000-07-18 Poss; Michael A. Methods for the preparation of novel sidechain-bearing taxanes and intermediates
US6365750B1 (en) 1995-03-22 2002-04-02 Bristol Myers Squibb Comp. Methods for the preparation of taxanes using oxazolidine intermediates
US6906040B2 (en) 2000-09-22 2005-06-14 Bristol-Myers Squibb Company Method for reducing toxicity of combined chemotherapies
US6927211B2 (en) 2000-09-22 2005-08-09 Bristol-Myers Squibb Company Method for reducing toxicity of combined chemotherapies

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