JPS6041774B2 - logic circuit package - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit package that performs fault diagnosis using an electronic computer.

FLT is one of the methods for diagnosing computer failures.
(FaultLocatingTast) diagnosis method is available.

Regarding the FLT diagnostic method, for example, the Information Processing Society of Japan's
Improving the reliability of computer systems'' (P267-2
71). The FLT diagnostic method is a device to be diagnosed that is equipped with a scan-in mechanism, a scan-out mechanism, and a diagnostic control unit that controls these, and an external device issues a command to start diagnosis to the device to be diagnosed during diagnosis. This is a method in which the scan-in mechanism, the scan-out mechanism, and the diagnostic control section that controls them are operated, and the part to be diagnosed by the diagnostic control device is diagnosed by regarding it as a combinational circuit. When diagnosing using this method, in principle, the part to be diagnosed must be surrounded by flip-flops.

In other words, in order to diagnose using the FLT method, the part to be diagnosed consists of a flip-flop to which an arbitrary diagnostic pattern can be set, and a next stage that can be observed by setting the diagnostic pattern with the flip-flop and controlling the clock. It must be surrounded by flip-flops.
However, installing flip-flops in equipment for diagnosis generally leads to a decline in the performance of the equipment, so installing flip-flops in devices such as IC memory peripheral circuits and interfaces from the device to be diagnosed to other equipment, etc. The installation of diagnostic flip-flops has been avoided in areas where installing a flop would significantly degrade performance. Therefore, diagnosis using the FLT method has the disadvantage that this portion is always excluded from the diagnosis. The purpose of the present invention is to install a flip-flop exclusively for diagnosis in parallel to the normal signal line, and use the flip-flop as a flip-flop for observing the propagation of faults. An object of the present invention is to provide a logic circuit package that can expand the diagnostic range of a device.

The package of the present invention includes a scan-in bus that sequentially propagates diagnostic data only during diagnosis, and a first diagnostic data storage means that sequentially stores and outputs diagnostic data in parallel only during diagnosis via the scan-in bus. A diagnosis target circuit that supplies data in parallel and outputs it in parallel without holding it, and a second diagnosis that branches from at least this logic circuit to a normal data bus to store the data that is supplied in parallel and outputs it sequentially during diagnosis. It consists of a data storage means and a scan-out bus that sequentially outputs data from the second storage means only during diagnosis.

In the conventional embedded design of electronic computers, the installation of redundant flip-flops, especially flip-flops dedicated to diagnosis, has been avoided because it leads to a decrease in the performance of the device. The present invention connects a flip-flop dedicated to diagnosis in parallel to a signal line connecting elements, and enables FLT diagnosis without using the flip-flop as a flip-flop constituting a general logic circuit. By installing it as a flip-flop for observing pure fault propagation in the system, it is possible to expand the range of FLT diagnosis of the system without degrading the performance of the system.

The present invention enables the fault propagation state to be observed during FLT diagnosis without affecting the normal logic function and performance of the device by connecting the diagnostic flip-flops in parallel. It is based on the principle that Next, one embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes a central processing unit 11 and a group of flip-flops 1.
2, an IC memory 13, a logic circuit 14 for creating a data write address to the 1C memory, and a diagnostic flip-flop 15.

Now, in order to be able to detect a failure in the logic circuit 14 by executing FLT diagnosis, it is necessary to
It is necessary to be able to extract it from the central processing unit 11 as a combinational circuit. To do this, we need a flip-flop that can set a pattern for detecting a fault in the logic circuit 14, and a flip-flop that can observe the propagation state of the fault in the logic circuit 14 according to the pattern. Yes, and in this example, the former flip●
The flip-flop group 12 is used as a flop, and the diagnostic flip-flop 15 is used as the latter flip-flop.
, respectively. That is, when performing FLT diagnosis of the logic circuit 14, the pattern is flip-flopped using diagnostic hardware (not shown).
After scanning in, perform clock advance,
By scanning out the contents of the diagnostic flip-flop 15, the fault propagation state of the logic circuit 14 according to the pattern can be observed in the diagnostic flip-flop 15. In addition, the IC in this embodiment
It is clear that if the memory 13 is replaced with, for example, a main storage device, diagnosis using the FLT method will also be possible using the interface section from the central processing unit to the main storage device. As explained above, in the present invention, by providing a diagnostic flip-flop in parallel to the signal line,
It is now possible to carry out FLT diagnosis without deteriorating the performance of the device, in areas where it has traditionally been impossible to diagnose using the FLT method because the installation of flip-flops degrades the performance of the device. , there is an effect.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing a partial block diagram of an embodiment of the present invention. In FIG. 1, 11... central processing unit, 12...
・・・）・・・Flip●Flop group, 13・・・・・・
IC memory, 14...Logic circuit, 15...
...Diagnostic flip-flop.

Claims (1)

[Claims] 1 A scan-in path that sequentially propagates diagnostic data only during diagnosis; a first diagnostic data storage means that sequentially stores and outputs diagnostic data in parallel through this scan-in path only during diagnosis; At least one diagnostic target logic circuit that is supplied and output in parallel without being held; and a diagnostic data path that stores and diagnoses data that is supplied in parallel via a diagnostic data path branched from a predetermined normal data path of the logic circuit. 1. A logic circuit package comprising: second diagnostic data storage means that sequentially outputs data; and a scan-out path that sequentially outputs data from the second storage means only during diagnosis.