JPH01140834A - System for detecting communication fault - Google Patents

Abstract

PURPOSE:To detect a bus fault at an early stage by connecting a processor and a channel equipment by means of an individual lead line in a bus connection type processing system. CONSTITUTION:The processor 1 starts the channel equipment 2 through a bus circuit 5. The channel equipment 2 controls an input/output device under control, and communicates information to the processor 1 through the bus circuit 5. At the time, the individual lead line l1 is simultaneously switched ON. On the other hand, the fault detection circuit of the processor 1 compared ON information of the individual lead line l1 with the presence or absence of communication via the bus circuit 5. When there is no information from the bus circuit 5 even if there is ON information of the lead line l1, it displays an error as the bus fault.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a communication failure detection method, particularly a communication failure detection method when a communication failure occurs in a bus connection type. The present invention relates to a communication failure detection method suitable for application in communication between a processing device and a channel device in a processing system according to the present invention.

[Conventional technology]

In a system that has a processing device and a channel device controlled by the processing device, and the two are connected in the form of a bus and communicate via the bus, it is possible to know whether there is a communication failure.
This is necessary to achieve stable communication.

Conventionally, this type of failure detection has taken a soft timeout method. In other words, this method of detecting a communication failure is to count the timing at which the maximum response time is exceeded for the activation from the processing device as a timeout value, and if there is no response within a predetermined timing, there is a failure. It is determined that This conventional technique will be explained using FIG. 4 and subsequent figures.

FIG. 4 shows a general pink block diagram of the above-mentioned bus connection type processing system, and FIGS.
The figure shows an example of a communication sequence.

As shown in FIG. 4, this system includes a processing device 1 and a plurality of channel devices 2.3 controlled by this processing device 1.
,4. ... are connected in the form of a bus, and communication is performed via the bus 5.

Each channel device 2, 3, 4. Communication between ... is performed as follows.

First, assume that the processing device 1 activates the channel device 2. Then, the channel device 2 starts operating according to the instruction contents. When the operation is completed, the channel device 2 sends a completion report to the processing device 1 (sequence shown in FIG. 5). At this time, since the processing device 1 usually has a large capacity, the processing device 1 has a plurality of channel devices 2, 3, 4 .
..., and on the other hand, each channel device 2゜3.4. ... controls a significantly slower IO (input/output device), so a method is used to report it as soon as the operation is completed. In addition, as shown in the sequence of Fig. 6, the startup is immediately accepted for startup to confirm the normality of communication.
There is also a sequence in which reports are immediately accepted.

In this way, communication is performed via the bus 5, and in case of a communication failure due to a bus failure, etc., the timeout value is determined by adding a margin to the maximum operating time of the 10 slowest devices connected to the channel device. If a response still does not come back after a period of time longer than the specified value, it is assumed that there is a failure.

[Problem that the invention seeks to solve]

However, such a communication fault detection method has the following drawbacks, such as a lack of promptness in fault detection.

In the conventional method described above, the IO with the slowest timeout value
Therefore, the timeout value preset for determining the presence or absence of a failure becomes large, resulting in a delay in failure detection. Furthermore, during the system debugging stage, an analyzer is used to observe waveforms in order to investigate the cause of communication failures due to design errors, but in this case, failure detection (timer overflow) is triggered, so the timeout value is large. However, the disadvantage is that the waveform at the time of actual communication cannot be observed.

The purpose of the present invention is to be able to detect communication failures at an early stage, and to
It is an object of the present invention to provide a communication failure detection method that allows smooth investigation of the cause of a failure.

[Means for solving problems]

The present invention provides a communication failure detection method in a processing system in which a processing device and a plurality of channel devices controlled by the processing device are connected in a bus format and communicate via the bus, comprising: the processing device and the plurality of channel devices controlled by the processing device; Individual lead wires are connected between the channel devices, and during communication processing of reports from the channel device to the processing device, predetermined signals are sent to the individual lead wires between the processing device and the communicating channel device, and on the processing device side, the bus It is characterized in that a communication failure is detected based on the status of the presence or absence of communication via the route and the status of the signal on the individual lead wire.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, the processing device 1 includes a communication transmitting/receiving circuit 12, while the channel devices 2, 3, 4, . . . have communication transmitting/receiving circuits 21, 31, 41, .
..., each connected by a bus circuit 5.

Furthermore, between the processing device 1 and the channel devices 2, 3, 4 . . . are connected to the individual lead wires II, i, , It, . . . separately from the bus, and the channel devices 2, 3, 4 . . . . During the communication of the product document to the processing device 1 via the bus, the communication transmitting/receiving circuit in each channel device turns on the individual lead wires between the processing devices 1 and 1 in the communicating channel device. It is designed to control the information sent to the line.

On the other hand, the processing device 1 has a failure detection circuit 11 as a circuit that compares and detects the presence or absence of communication via the bus and 0N10FF of the individual lead wires.

This failure detection circuit 11 is connected to a communication transmitting/receiving circuit 12 in the processing device 1 and a lead wire 7! ,, z Z+β3. Communication transmitting/receiving circuits 21 and 31 on each channel device side via...
゜41. ..., which detects bus communication failure and displays the failure.

FIG. 2 shows a specific example of the fault detection circuit 11, in which 111 shows AND logic, 112 shows inverter logic, and 113 shows OR logic.

As described above, in the communication failure detection method shown in FIGS. 1 and 2, the processing device 1 and the plurality of channel devices 2, 3, 4, . . . are connected in the form of a bus, and communicate via this bus, in which a processing device 1 and channel devices 2, 3, 4, . . .
...Individual lead wires II, 12, 13 . ... and channel device F2. 3. 4. ...
During communication processing for reporting from to processing device 1, the individual lead wires between the processing devices 1 and between the communicating channel devices are turned ON, and on the processing device 1 side, communication is received via the bus and the individual lead wires are set to 0N.
A bus communication failure is detected by comparing 10FF.

Next, regarding the operation with the configuration shown in FIGS. 1 and 2, the third
The explanation will be made with reference to the communication sequence example shown in the figure.

The following example takes the case of communication between the processing device 1 and the channel device 2.

First, the processing device 1 is connected to the channel device 2 via the bus circuit 5.
Activate against. The channel device 2 controls the IO under its control, and communicates a report to the processing device 1 via the bus circuit 5 when the operation is completed. At this time, the individual lead wire 11 is also turned ON (the dotted line portion in FIGS. 1 and 3).

On the other hand, the processing device 1 compares the ON information of the individual lead wire 1 with the presence or absence of communication via the bus circuit 5, and displays a failure indication when a communication failure is detected.

In other words, there is an ON signal from the channel device 2 on the lead wire 11.
By sending out the information, the input given to the fault detection circuit 11 via the lead wire l is in a high level state, and the above-mentioned report communication is made from the channel device 2 via the bus circuit 5. If the communication transmitting/receiving circuit 2 of the processing device 1 provides information indicating "reported" to the fault detection circuit 11 as a high level signal, the fault detection circuit 1
The output of 1 becomes low level, so no error is displayed.

On the other hand, if the high-level signal indicating "reported" is not input from the communication transmitting/receiving circuit 12 side to the fault detection circuit 11 even though ON information is input via the lead wire I. Sometimes, the communication transmitting/receiving circuit 12
and the inverted input from lead wires 1, , /
2+β3. . . . As a result, the output of the fault detection circuit 11 becomes high level, and an error message is displayed. That is, a communication failure in the bus circuit 5 is detected and displayed.

Processing device 1 and channel devices 3, 4. . . . communication between them is carried out in accordance with this method, and if there is a communication failure, it can be detected quickly. Furthermore, since the delay in failure detection that occurs in the past can be eliminated, it is possible to smoothly investigate the cause of communication failures during the system debugging stage.

〔Effect of the invention〕

As described above, according to the present invention, bus failures can be detected early by connecting individual lead wires between the processing device and the channel device and sending signals to the individual lead wires during communication. Furthermore, when searching for the cause during the functional confirmation stage of incorrectly installed hardware, including the bus circuit, it becomes easier to observe the waveform using the fault display as a trigger, and this has the effect of making it possible to smoothly investigate the cause. It goes without saying that the case of detecting a startup failure from a processing device to a channel device can be similarly performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a specific example of the fault detection circuit, Fig. 3 is a diagram showing an example of a communication sequence, and Fig. 4 shows a conventional example. FIG. 5 is a block diagram showing an example of a conventional communication sequence, and FIG. 6 is a diagram showing another example of a 1ffl communication sequence. D...Processing device 2, 3.4...Channel device 5...Bus circuit engineer 1...Fault detection circuit 12, 21.31.41. ...Communication transmitting/receiving circuit 111
...And logic 112 ...Inverter logic 113 ...
・・・・Or logic agent Patent attorney Yoshiyuki Iwasa 5-・-Bus Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) In a communication failure detection method in a processing system in which a processing device and a plurality of channel devices controlled by the processing device are connected in a bus format and communicate via the bus, the processing device and each of the channels Individual lead wires are connected between the devices, and during communication processing of reports from the channel device to the processing device, a predetermined signal is sent to the individual lead wire between the processing device and the communicating channel device, and on the processing device side, the signal is sent via the bus. A communication failure detection method, characterized in that a communication failure is detected based on the presence/absence of communication and the status of a signal on the individual lead wire.