JPS63281539A - Error data generating circuit - Google Patents

Abstract

PURPOSE:To generate erroneous data to any transfer data without fail and to efficiently execute the detailed test by converting normal data on a common bus to arbitrary erroneous data with an error generating pattern and supplying them to a fault detecting circuit. CONSTITUTION:To a register 33 of an erroneous data generating circuit 3 through a common bus 1, an error generating pattern is set, and to respective plural bit lines B0-Bn to constitute the bus 1, plural signal inverting elements 320-32n are connected. To the output of the bit lines B0-Bn and the elements 320-32n, selectors 310-31n of two inputs are connected, and the connection at the section of the output of the elements 320-32n to the fault detecting circuit 4 is switched by an error generating pattern. To a register 33, an error generating pattern is set, a signal TP for a test is sent to a microprocessor 8, the output from the circuit 4 is processed by a logic element 5, an error display FF6 and a logic element 7, added to a processor 8 and a parity error is processed by the processor 8.

Description

[Detailed Description of the Invention] [Summary] Normal data on a common bus is signal-inverted according to an error occurrence pattern and converted into error data, which is supplied to a fault detection circuit to detect an error, and the fault detection circuit operates. This is to test.

[Industrial application field]

The present invention relates to data transfer tests in various control devices, and particularly relates to an error data generation circuit that converts normal data into error data and supplies it in order to test the operation of a fault detection circuit that detects error data. .

The control device performs control by transferring data between memory devices and other control devices, but in order to confirm that the data is normal, a fault detection circuit is installed to detect erroneous data and detect erroneous data. This prevents it from becoming a controlled action. If the fault detection circuit becomes faulty, the reliability of the control operation described above is lost, so in order to test the fault detection circuit, an error data generation circuit that can convert normal data into arbitrary error data must be considered. .

[Conventional technology]

FIG. 2 is a diagram of a conventional error data generation circuit, and shows an example used in a control device 2 such as an input/output control device.

The common J bus l, which connects the central processing unit and the memory device, has n bit lines BO that transfer n pinpoints of data.
~Bn and a parity line PTY that transfers the parity bit for the data.

The above data are bit lines B0 to B of the error data generation circuit 3.
Exclusive OR elements 30 to 3 provided respectively corresponding to n
The parity bit generated by this circuit is compared with the parity bit transmitted from the parity line PTY, and it is detected whether the data is normal or erroneous. be done.

The output of the fault detection circuit 4 is input to the AND element 5, and the parity check timing signal SP from the microprocessor (hereinafter referred to as MPU) 8 is given to the other input of the AND element 5, so that an error display flip-flop is input. (
(hereinafter referred to as EFF) 6 is set to a logic value of 0 when the data is normal, and to a logic value of 1 when error data is detected.

The EFF 6 set to the logical value 1 sends the interrupt signal RQ and the error signal EP to the MPU 8 via the OR element 7.

The MPU 8 controls parity error processing using these signals.

On the other hand, the input from the gate circuit 302 is added to the other inputs of the exclusive OR elements 30 to 3n, and since this input normally has a logic value of O, it does not affect the above operation. , when testing the fault detection circuit 4, the gate circuit 3
02 is opened, and the output of the nbee/'r counter 301 is applied to each of the exclusive OR elements 30 to 3n.

The timer 300 periodically generates a test signal TST, and the fault detection circuit 4 is tested using this signal.

That is, the test signal TST is input to the input terminal CK of the counter 301.
, the counter 301 adds +1 and outputs the n-ary count value from the output terminals QO to Qn to the exclusive OR elements 30 to 30 through the gate circuit 302 opened by the test signal TST. Output to 3n.

Logical value 1 of logical value 1 and logical value O representing the count value
Since the exclusive OR element to which is input inverts the input signal, the data transferred by the common bus l becomes erroneous data. The failure detection circuit 4 detects error data and outputs the EFF.
6 to the logical value l.

In addition to the above, the test signal TST is sent to the MPU 8 by setting the test display flip-flop (hereinafter referred to as TFF) 9 to a logical value of 1.
When the fault detection circuit 4 detects a fault, it sends the test signal TP to
Even if F6 remains at the logical value O, the interrupt signal RQ is sent to the MPU 8 via the OR element 7.

The MPU 8 enters the interrupt processing operation in response to the interrupt signal RQ, and since the error signal EP is being sent, it identifies a parity error, but since it is receiving the test signal TP, it is a parity error that has occurred due to the test. It is determined that parity error processing is not performed, and retry processing or the like is performed in which a central processing unit (not shown) retransmits data.

If the fault detection circuit 4 is faulty and the error signal EP is not sent, parity error processing is performed.

Furthermore, after receiving the interrupt signal RQ, the MPU 8 resets the EFF 6 and the T F 9 by sending out a reset signal RP to prepare for the next test.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, since a counter is used to generate error data, there is a problem in that it is not possible to set an arbitrary error occurrence pattern, and it is not possible to test specific bits of data.

Also, depending on the error occurrence pattern that is the output of the counter, for example, if the error occurrence pattern is all logical 0 and the transferred data is all logical 1, it will not be error data and the failure detection circuit will There are some problems that make it impossible to test.

[Means for solving problems]

The solution to the above problem is as shown in FIG.
and a plurality of signal inverting elements 320 to 32n connected to each of the plurality of bit lines B0 to Bn constituting the common bus l,
It has two inputs connected to the bit line and the output of the signal inversion element, and switches the connection between the bit line and the fault detection circuit 4 to the connection between the output of the signal inversion element and the fault detection circuit 4 according to the error occurrence pattern. A plurality of selectors 310 that output
This can be achieved by an error data generation circuit provided with .about.31n.

[Effect]

That is, the selectors 310 to 31n are controlled by the output of each corresponding pin point of the register 33, and when the bit has a logical value of 1, the connection between the harm detection circuit 4 and the bit line is switched to the connection with the output of the signal inverting element. It will be done.

Therefore, the selector connected to the pinto output of the register 33, which is set to logical value 1, inverts the signal on the bit line connected to the selector and outputs it according to the error occurrence pattern arbitrarily set by the central processing unit. I decided to do it,
The outputs of the selectors 310 to 3In become error data according to the error occurrence pattern and are applied to the fault detection circuit 4, where they are detected as faults.

In this way, any error occurrence pattern can be set in the register 33, making it possible to test specific bits of data and reliably generate error data.

〔Example〕

The present invention will be explained in detail below with reference to the illustrated embodiments. The same reference numerals indicate the same objects throughout the figures.

FIG. 1 is a diagram of an error data generation circuit according to an embodiment of the present invention, which is used, for example, in a control device 2 such as an input/output control device.

In the figure, 3'' indicates an error data generation circuit.

33 is a register in which an error occurrence pattern is set;
An error occurrence pattern in which bits of data to be tested are set to logical value 1 from a central processing unit (not shown) is common bus 1.
configured via.

310 to 31n are selectors, and the input terminal A of each selector is connected to the bit lines B0 to Bn constituting the common bus 1, and the other input terminals B are connected to the bit lines BO% and 7).
Signal inverting elements 320 to 32n each connected to Bn
The output Y of each selector is connected to the fault detection circuit 4.

Each selector also has a control terminal S connected to the output of the corresponding bit of the register 33, and when the bit has a logical value l, the connection between the output terminal Y and the input terminal A is The connection can be switched to

Parity line PTY is directly connected to fault detection circuit 4.

Normally, bits 0 to n of the register 33 are all logical 0, so the data on the common bus 1 is sent to the failure detection circuit 4 as is.
Similarly to the conventional example, when a parity error is detected, parity error processing is performed by the MPU 8.

In testing the fault detection circuit 4, an error occurrence pattern in which the bit to be tested is set to logic value 1 and other bits are set to logic value O is transmitted to the register 33 via the common bus 1 by the central processing unit.
is set, and then the test data is sent.

Now, when the 3300th bit of the register is set to the logical value l (the other bits are the logical value O), the selector 310 switches the connection between the input terminal B and the output terminal Y, and the bit line BO
For example, the output of the signal inverting element 320 which inverts the logical value 1 to a logical value O is sent to the fault detection circuit 4.

Since the data other than the bit line BO remains as it was, the parity bit created by the fault detection circuit 4 is connected to the parity line P.
The parity bit will be different from the parity bit sent from TY,
A parity error is detected.

On the other hand, as the error occurrence pattern is set in the register 33, the testing signal TP is sent to the MPU 8, and the interrupt signal RQ (when a parity error is detected,
FF6 is set to logical value 1 and an interrupt signal RQ is sent out) is sent to the MPU 8 and interrupt processing is performed.

The MPU 8 identifies a parity error by the error signal BP from the EFF 6, but since it has received the test signal TP, it does not perform parity error processing as in the conventional example, and the fault detection circuit 4 receives the error signal EP due to a fault. If not, it is the same as the conventional example (parity error processing is performed).

The register 33 has all bits set to logic value O upon completion of the above test.
will be reset to

Although the present embodiment has been described with respect to parity checking, the present invention is not limited to parity checking, and can be applied to testing any error data detection circuit.

〔Effect of the invention〕

As explained in detail above, according to the present invention, it is possible to reliably generate error data even for any transfer data, and the error generation pattern can be arbitrarily set, so that detailed tests can be carried out efficiently. (It can be done.

[Brief explanation of drawings]

FIG. 1 is an error data generation circuit diagram of an embodiment of the present invention. FIG. 2 is a diagram of a conventional error data generation circuit. In the figure, 1 is a common bus, 2 is a control device; 3' is an error data generation circuit; 4 is a fault detection circuit; 5 is an AND element, 6 is an error display flip-flop; 7 is a logical sum element, 8 is a microprocessor; 310 to 31n are selectors, 320 to 32n are signal inversion elements; 33 is a register, B0 to Bn are bit lines, PTY indicates a parity line.

Claims (1)

[Claims] A register (33) in which an error occurrence pattern is arbitrarily set via a common bus (1), and a plurality of bit lines (B0 to B0 making up the common bus (1)).
A plurality of signal inverting elements (320 to 320) connected to each of the
32n), and has two inputs connected to the bit line and the output of its signal inversion element, and connects the bit line and the failure detection circuit (4) to the output of the signal inversion element according to the error occurrence pattern. and a plurality of selectors (310 to 31n) that switch and output the connection with the fault detection circuit (4), and convert normal data on the common bus (1) into arbitrary error data according to the error occurrence pattern. An error data generation circuit characterized in that the error data generation circuit supplies the error data to the failure detection circuit (4).