JPS6135517B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a positron CT device.

Operation tests of positron CT devices, especially coincidence counting devices, have not been properly performed in the past. This will be explained using the coincidence counting device shown in FIG. In the figure, a plurality of detector groups 1 are detector groups formed by grouping for convenience to simplify the circuit. A plurality of detector address encoder circuits 2 are installed corresponding to the above-mentioned detector groups, and have a function of converting the outputs of the detectors in the group into binary codes.
The coincidence circuit 5 is composed of an AND circuit, and detects coincidence events between groups. A group address encoder circuit 6 encodes the group address signal of the detector into binary code. A detector address multiplexer circuit 7 sorts the detector address signals. The processing device 9 includes an encoder circuit 6 and a multiplexer circuit 7
The outputs 8A and 8B of , that is, the detector address and group address signals, which are the position information of the two detectors involved in detecting the coincidence event, are collected and the image is reproduced.

Generally, the detectors used in positron CT devices are arranged in a ring, with 100 detectors per ring.
Since the number of signals 8A and 8B is greater than 1, there are thousands of signals 8A and 8B handled by the coincidence counting device. Operation tests of coincidence counting devices are carried out to discover malfunctions in the circuit elements used, faulty connections in cables, etc., and faulty adjustments in the timing of each signal. The simplest operational test is to know the position information of the detectors collected by the processing device 9 using positron-emitting nuclides, ie, all combinations of detectors involved in detecting a coincidence event. However, with the above method 〓〓〓〓〓
cannot be tested solely on coincidence counting devices because of additional factors such as malfunction of the detector system and variations in sensitivity. In an improved test method for this purpose, a test signal equivalent to the output signal of the detector is sequentially inputted to the encoder circuit 2 instead of the two opposing detectors. However, as mentioned above, it is extremely difficult to implement this method because there are as many as 1000 combinations to input.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to make it possible to collect information for confirming circuit operation, that is, signals corresponding to all combinations of detectors involved in detecting a coincidence event, within a short time. Our objective is to provide a positron CT device.

The gist of the invention is as follows. The processing device is programmed with the combination order of detection values to be selected, and furthermore, based on the combination output of this processing device, a test signal is input in a simulated manner to the detector address encoder circuit for the corresponding combination detector. The main point of the present invention is that the processing device monitors the output to the processing device in response to this simulated test input and performs an operation check. Further, in the present invention, a test signal generation circuit is provided as having a function of generating a test signal based on the combined output from the processing device. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is an embodiment of the coincidence counting device of the present invention. The detector group 1 is a group of detectors arranged in a ring shape, and is the same as the conventional example shown in FIG. The multiple detector address encoder circuit 2 is basically the same as the conventional detector address encoder shown in FIG. . The configurations of the coincidence circuit 5, group address encoder circuit 6, and multiplexer circuit 7 are the same as the corresponding circuits of the conventional example shown in FIG. This embodiment is characterized by the internal functions (software) of the processing device 9.
is uniquely added, and furthermore, a test signal generation circuit 10 is provided.

The processing device 9 consists of a computer. Therefore, in the following, it will be referred to as a computer instead of a processing device. The computer 9 has built-in software for image reconstruction and operation test software.
The operational test software is programmed with the order of detector combinations to be selected, so that all combinations of detectors involved in detection of coincidence events can be realized for testing. This operational test software is accessed automatically or manually during operational test mode.

The test signal generation circuit 10 has a function of receiving detector combination order data from the computer 9 and setting which of the plurality of detector address encoder circuits 2 the data is to be distributed to, and a test signal sending function. The former function may be a hardware function that distributes, and the latter function may be a function that generates logical "1" or "0".

Explain the operation. An operational test mode, for example, is set before testing a subject, and the operational test software of the computer 9 is accessed according to an operator's instruction. This access activates the operation test software. The operation test software outputs the detector combination order one after another.
The signal is input to the test signal generation circuit 10. In the computer, the detector number is indicated by an address indicating the detector number, and the order of detector combinations is determined by indicating two addresses indicating the combination of detectors. 2 showing this combination detector
The two addresses are input to the test signal generation circuit 10.

The test signal generation circuit 10 that has received the two addresses indicating the combination detector finds the corresponding encoder circuit among the plurality of detector address encoder circuits 2, and sends test data to the corresponding encoder circuit. do. The above operation is performed using the calculator 9
The same process is performed for each pair of detector combinations output from the . The encoder circuit performs a predetermined operation on the test data input to the encoder circuit corresponding to each detector pair, and is further input to the computer 9 via the coincidence circuit 5, group address encoder circuit 6, and multiplexer circuit 7. do. Based on the correspondence between this input and the previous output address, the computer 9 checks the path specified by the address. Such a path check is performed for every pair of detectors. The object to be diagnosed as a result of the path check is all the electronic circuits between the detector group 1 and the computer 9. Also, calculator 9
Data as a diagnosis result includes data indicating which detector is abnormal and which encoder circuit 2 series is abnormal.
The data is displayed on a CRT device (not shown) and
The information is printed on a printer (not shown) and provided to the worker.

Figure 3 shows two opposing detector groups 1A.
and 1B are shown. For simplicity, the figure shows a case where the number of detectors in a group is four.
In the figure, (0) to (3) are the addresses of each detector, 1A
(0) ~ 1B (0), 1A (0) ~ 1B (1), 1
A(0) to 1B(2), 1A(0) to 1B(3)
shows a combination of detectors that detect coincidence events. In addition, similar combinations are established for address (1), address (2), and address (3) of 1A. Regarding such opposing groups, the computer 9 selects the opposing groups 1A and 1B, and then sequentially outputs specific corresponding detector combination data (address combinations) and inputs them into the operation test circuit 10. Sending this combination data is 1A(0) and 1B(0) → 1A(0)
and 1B (1) → 1A (0) and 1B (2) → 1A
(0) and 1B(3) are performed in this order. Encoder circuit 2 →… → multiplexer device 7 for each data
The output via the computer 9 is taken into the computer 9 and an abnormality check is performed. Next, for 1A(1), pairs with each of the detectors 1B(0) to 1B(3) are similarly selected, and data is sent out. Similar processing is then performed for all detector pairs. To perform all possible combinations, successively select another opposing group and repeat the same procedure.

FIG. 4 shows an example of address creation within the computer 9. The group selection signal is a clock signal, and based on this group selection signal, the addresses of the detector pairs of groups A and B are formed. When the number of detectors in a group is 4, for group A, the frequency of the above clock is divided by 4, and then the quadrupled frequency-divided signal is counted by a binary counter. The outputs Q ₀ and Q ₁ of the binary counter indicate the detector number (address) of the A group. For group B, the clock is counted by a binary counter. The outputs Q ₀ and Q ₁ of the binary counter indicate the detector number (address) of the B group. The count input for both groups A and B is a clock that forms a group selection signal. The computer 9 generates and divides the group selection signal, and also divides the frequency of each group selection signal.
Each counting process of the advance counter, the sending process of the detector pair address to the line 9A, and the storing process of each address for the purpose of checking are performed. Fourth
The views of groups A and B shown in the figure are as follows. A and B synchronized with group selection signal 1
The Q ₀ and Q ₁ signals are combination 1A (0) as shown by the broken line.
Corresponds to ~1B(0). Similarly, group selection signals 2, 3, and 4 are 1A (0)-1B, respectively.
(1), 1A(0)-1B(2), 1A(0)-1
Corresponds to B(3)... The same applies to other combinations below.

There are various modifications to the above embodiments.

(1) Although the test signal generation circuit 10 is shared, it is also possible to provide separate test signal generation circuits (same meaning as distributed) for each encoder circuit 2. In this configuration, since the encoder circuit 2 and the test signal generation circuit are directly connected, there is an advantage that the connection of the input of the test signal can be simplified.

(2) The division of processing between the test signal generation circuit 10 and the computer 9 can be changed in various ways. There are two methods: the first method is to allocate processing in a direction that reduces the processing load on the computer 9, and the second method is to allocate processing in a direction that increases the processing load on the computer 9. The most extreme example of the first method is one in which the test signal generation circuit is responsible for various types of processing in place of the computer 9, and the computer 9 only has the role of triggering the test signal generation circuit. This method is not very practical because the test signal generation circuit 10 has the same role as a computer. The most extreme example of the second method is a case in which the test signal generation circuit functions only as a signal transmission means, and the computer 9 performs all the main processing. This naturally has the disadvantage of increasing the burden on the computer 9. Therefore, it is necessary to allocate processing based on these points.

Next, FIG. 5 shows an embodiment employing the distributed configuration described in (1) above. In the figure, the encoder circuit 2A is
This corresponds to one of the encoder circuits 2 shown in the figure. In this embodiment, a test signal generation circuit 10A is added to the encoder circuit 2A. Encoder circuit 2A
consists of a receiver circuit 11, an encoder 12, a latch circuit 14, a timing generation circuit 13, and driver circuits 15A and 15B. The receiver circuit 11 has the function of receiving the detector output. encoder 1
2 is the test output and output of the test signal generation circuit 10A.
It has a function of selectively taking in the output of the receiver circuit 11 and encoding it into binary code. The timing generation circuit 13 has a function of determining the width of the timing signal generated from the output of the encoder 12.

The latch circuit 14 is controlled by the output timing of the timing generation circuit 13 and the encoder 12
latches the output. The driver circuit 15A has the function of sending the detector address signal latched by the latch circuit 14 to the multiplexer circuit 7, and the driver circuit 15B has the function of sending the output timing of the timing generation circuit 13 to the coincidence circuit 5.

The test signal generation circuit 10A is the receiver circuit 11
A, comparison circuit 16, 16A, comparison address setting circuit 1
7,17A, frequency divider circuit (rate down circuit) 1
8, an OR gate 19, a binary counter 20, and a binary-decimal counter 21. Receiver circuit 1
1A receives the detector group address signal to be selected sent via the bus 9A of the computer 9.
Comparison address setting circuits 17 and 17A set detector group addresses determined in advance for each group. Comparing circuits 16 and 16A have a function of reading group and B group address signals. The frequency dividing circuit 18 means a 4 frequency dividing circuit according to the example shown in FIG.

Corresponding to the cases shown in FIGS. 3 and 4, the encoder 12 supports group A and group B.
There are times when it is necessary to accommodate groups. Whether it corresponds to the A group or the B group depends on the instructions from the computer 9 and the decoding function of the receiver circuit 11A.
This will be explained in detail below. Test signal generation circuit 10
By configuring A in a distributed configuration, the test signal generation circuit 10A corresponding to each encoder circuit 2A is
An output must be sent to the corresponding encoder 12 depending on whether it is group A or group B. This output is in group A when the comparison circuit 16 is selected, and is in group B when the comparison circuit 16A is selected. Therefore, whether each test signal generation circuit 10A is made to work in group A or group B depends on the instruction to select between comparison circuits 16 and 16A. Receiver circuit 11A makes this determination. That is, the receiver circuit 11A decodes from the signal on the bus 9A whether the mode corresponds to the A group or the B group, and according to this result, the receiver circuit 11A decodes the mode corresponding to the A group or the B group.
Make one of the following choices. Here, deciphering may mean either a case where the judgment is made based on timing, or a case where the computer deciphers the code by placing it on the bus 9A, which directly indicates whether the computer is in group A or group B. . Explain the operation. Receiver circuit 11A receives the signal on bus 9A and selects either comparison circuit 16 or 16A depending on whether it corresponds to group A or group B. Since each encoder circuit 2A always exists in the A group and in the B group, the comparison circuits 16 and 16A are always selected in the test mode. When determining the A group, the comparison circuit 16 determines whether the group corresponds or not, depending on whether or not there is a match. If a match is found, the encoder circuit 2A is recognized as a corresponding group, and a signal corresponding to the group address is sent from the comparison circuit 16 to the frequency division circuit 18, where timing frequency division is performed. The output of this frequency dividing circuit 18 passes through an OR gate 19 and enters a binary counter 20 to form an address. Next, binary code-decimal conversion is performed in the conversion circuit 21, and the result is output to the corresponding encoder circuit 2A. In the corresponding encoder circuit 2A, the encoder 2A receives the above output, and the test data (“1”) is transmitted to the encoder 12, the latch circuit 14, and the driver circuit 15A.
The timing is sent out via the timing generation circuit 13 and the driver circuit 15B. This data and timing are provided by circuit 5,
As shown in FIG. 3, the data is inputted to the computer 9 via the terminals 6 and 7, and checked for diagnosis.

On the other hand, when it is determined that it is in the B group, the comparison circuit 16A performs a comparison, and when a match is obtained, the path from the OR gate 19 is followed and a similar diagnostic check is performed.

According to this embodiment, the connection of the test signal input is simplified. Incidentally, once the number of detectors and the number of groups are determined, the number of pits of each element used is determined accordingly, so it goes without saying that the system can be expanded or reduced by appropriately selecting the number of bits of each element.

According to the present invention, it is possible to simulate thousands of combinations of detector address signals handled by a coincidence circuit using a computer-based processing device.
Become. Therefore, by simply connecting the test signal generation circuit once, signals corresponding to all combinations of detectors involved in detecting a coincidence event can be arbitrarily collected, simplifying the operation test.

[Brief explanation of the drawing]

Fig. 1 is a diagram of a conventional example, Fig. 2 is an embodiment of the present invention, Fig. 3 is an explanatory diagram of opposing groups, Fig. 4 is a time chart, and Fig. 5 is another specific embodiment of the present invention. It is a diagram. 1...Detector group, 2A...Encoder circuit, 10,
10A...Test signal generation circuit, 9...Processing device (computer). 〓〓〓〓〓

Claims (1)

[Claims] 1. A plurality of detector address encoder circuits provided corresponding to a plurality of groups of detectors formed by grouping, and a simultaneous detection between the groups from the detector address of each encoder circuit. A coincidence means that detects a counting event and outputs the position information of the two detectors involved in detecting the coincidence event, that is, a detector address and a group address, and a coincidence means that takes in the position information output from the means and reconstructs an image. a processing device that sequentially selects and outputs opposing arbitrary detector groups under test mode; and a processing device that sequentially selects and outputs opposing arbitrary detector groups under test mode, test signal generating means for receiving the number of the detector group and inputting it to the corresponding encoder circuit in place of the output of the detector group; Diagnosis of the electrical system path from the test signal generating means to the processing device by importing into the processing device two pieces of position information related to the detection of coincidence events in the test mode obtained through the coincidence counting means. A positron CT device in which the processing device performs the check. 2. The positron CT apparatus according to claim 1, wherein the processing device comprises a computer. 3. The positron CT apparatus according to claim 1 or 2, wherein the test signal generating means is distributed and configured to correspond to each encoder circuit.