JP2900781B2 - Cable connection abnormality detection circuit and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cable connection abnormality detecting circuit for an apparatus for connecting a plurality of packages via a cable in which a plurality of signal lines are bundled. And a method for detecting the same.

[0002]

2. Description of the Related Art Conventionally, this kind of cable connection abnormality detecting circuit has been disclosed in, for example, Japanese Patent Application Laid-Open No. 4-101372 (literature 1).
Also, it is used for the purpose of shortening a check time for a cable dropping or disconnection.

FIG. 5 is a block diagram showing a conventional cable connection abnormality detection circuit. In FIG. 5, the logic board
1 and 32 are connected to each other via cables 33 and 34. Storage device 312 of logic board 1 and logic board 3
The storage devices 322 of the logical board 1 hold the identification numbers of the same bit pattern, and the storage devices 313 of the logic board 1 and the storage device 323 of the logic board 32 also hold the identification numbers of the same bit pattern. Have been. These storage devices 312, 313, 322,
And 323 output each bit pattern based on the address indicated by the identification number address 3100.
The identification number data 3120 read from the storage device 322 by the identification number address 3100 is
Through is transmitted to the logic board 1, in the same manner, the identification number data 3121 read from storage unit 323 is transmitted to the logic board 1 through the cable 34. Selector 3
14 selects one of the identification number data 3120 and 3121 in accordance with the cable selection signal 3101 and sends it to the comparator 316 as the transmission side identification number 3112.
Numeral 15 selects one of the identification signal data 3110 and 3111 in accordance with the cable selection signal 3101 and sends it to the comparator 316 as a receiver identification number 3113. Comparator 3
At 16, the transmission side identification number 3112 from the selector 314
Is compared with the receiving side identification number 3113 from the selector 315, and when a pattern having a different result is detected, a connection error signal 3114 is output.

FIG. 6 is a block diagram showing another conventional cable connection abnormality detection circuit. In FIG. 6 , packages 1, 2, and 3 are connected via cables A and B. Now, in the device in which the packages 1 and 2 are connected, the selection circuit 12 selects an identification signal unique to the signal line in order to perform a cable connection abnormality detection test within a predetermined time when the signal line is not used. And cable A
To the comparison circuit 52 via Identification signal generation circuit 6
2 transmits to the comparison circuit 52 an identification signal unique to the signal line equivalent to the transmission signal of the selection circuit 12. The comparison circuit 52 compares the identification signal sent from the selection circuit 12 input via the cable A with the identification signal sent from the identification signal generation circuit 62, determines whether or not they match, and determines the determination result. Monitoring times
Output to the path 72. When the determination results do not match, the monitoring circuit 72 determines that the cable connection is abnormal.

[0005]

As described above, according to the conventional cable connection abnormality detecting means, incorrect cable connection,
Unconnected, dropped, and disconnected can be inspected efficiently in terms of time, and a connection abnormality can be detected. However,
In the circuit of Document 1, the connectors to be connected connections should not be connected originally, i.e., erroneously though connected or not be detected can be inspected One not a signal line one constituting the cable Cannot be performed, and it cannot be inspected for disconnection of the signal line. Further, the conventional technique shown in FIG. 6 has a problem that the number of signal lines in a used cable is extremely small when not in use, and when there is not enough time, inspection cannot be performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cable connection abnormality detection circuit and a method for performing a connection abnormality detection test only when a cable is connected, eliminating the above-mentioned drawbacks.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, a cable connection abnormality detecting circuit and method according to the present invention comprise a cable according to a clock signal for recognizing connection when a cable is connected between packages. a first identification signal generating means for outputting at least one signal line unique identification signal of signal <br/> Route to, these identification signals are constituted by a cable for transmitting to the determining means for cable connection abnormality that the transmission means, and detecting means for generating a test signal for operating the time the cable connection abnormality detection circuit for detecting a clock signal predetermined after cabling, the less the signal Line constituting the cable in response to a clock signal
A second identification signal generating means for outputting a signal equivalent to the one output identification signal to the judging means for judging a cable connection abnormality without passing through a cable; Determining means for comparing the identification signals output by the second identification signal generating means to determine a cable connection abnormality;

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating a cable connection abnormality detecting circuit and a method thereof according to an embodiment of the present invention. In FIG. 1, a cable A for electrically connecting the packages 1 and 2 is composed of six signal lines.
These signal lines are used during the cable connection abnormality detection test.
The two signal lines transmit an identification signal, and the remaining two signal lines transmit a synchronization signal and a clock signal, respectively. At the normal time when the test is not performed, five signal lines other than the signal line transmitting the clock signal transmit the normal signal.

A clock signal a for causing the package 2 to recognize that the cable A is connected in the package 1
Is generated by a clock signal generation circuit (not shown) provided in the package 1 and is connected to the package 2 via the cable A.
Sent to The identification signal generation circuit 80 is constituted by a 4-bit binary counter, is reset when the synchronization signal b output from the synchronization circuit 90 is input, and counts up each time the clock of the clock signal a is input. The four output lines of the binary counter are output to the selection circuit 10 and the synchronization circuit 90 as identification signals. The synchronization circuit 90 to which the identification signal is input is constituted by a decoder, and outputs the synchronization signal b to the identification signal generation circuit 80 and the selection circuit 11 when the input 4- bit identification signal becomes 0. The selection circuit 11 is configured by a selector. A normal signal is input to a terminal 11A, a synchronization signal b is input to a terminal 11B, and a test signal g output from the detection circuit 30 of the package 2 is used as a control signal. And sends it out to cable A. The selection circuit 10 is also formed by a selector. A normal signal including four signal lines is input to a terminal 10A, an identification signal including four signal lines is input to a terminal 10B, and the test signal g is used as a control signal. The signal of each terminal is selected and transmitted to the cable A.

Next, in the package 2, when the clock signal a is input to the binary counter, the detection circuit 30 configured by connecting the binary counter and the flip-flop performs a connection abnormality detection test after the cable connection. A predetermined time T is measured by a binary counter and output to a flip-flop. The clock signal a is also input to the flip-flop as an edge trigger, generates a test signal g corresponding to the time T, and outputs it to the comparison circuit 50, the control circuit 70, and the selection circuits 10 and 11 of the package 1. . The identification signal generation circuit 60 is constituted by a 4-bit binary counter, is reset when the synchronization signal c selected by the selection circuit 11 is input, and counts up every time the clock of the clock signal a is input. The four output lines of the identification signal generation circuit 60 are output to the comparison circuit 50 as the identification signal i. The comparison circuit 50 compares the signal h transmitted through the cable A of the signal d selected by the selection circuit 10 and the signal i output from the identification signal generation circuit 60 according to the test signal g output from the detection circuit 30. Then, each of the four identification signals is compared, and the comparison result is output to the control circuit 70. FIG. 2 shows a circuit configuration of the comparison circuit 50. In FIG. 2, the identification signal i output from the identification signal generation circuit 60 composed of a 4-bit binary counter is composed of four signals n, o , p, and q, and the signal n corresponds to the MSB of the counter. The signal q corresponds to the LSB. Similarly, in the signals j, k, l, and m output from the identification signal generation circuit 80 and transmitted through the cable A, the signal j corresponds to the MSB and the signal m corresponds to the LSB. . In the comparison circuit 50, first, four
The exclusive OR circuit compares, for example, the signals j and n corresponding to the MSB so that the respective bits of the identification signals h and i correspond. These four comparison results are respectively inverted by the inverter. Next, the four inverted signals are ANDed, and the output signal and the test signal g are compared by the OR circuit and output to the control circuit 70. The control circuit 70 includes an OR circuit and a protection circuit 40 including a monostable multivibrator. When the test signal g is input, the protection circuit 40 takes a time equal to or longer than the time required until the identification signal generation circuit 80 is reset for the first time by the synchronization signal b, that is, the protection time t (16 types of outputs of the 4-bit binary counter). (Equal to or longer than the time required to output all the signals) is output to the OR circuit.
The OR circuit compares the output signal of the comparison circuit 50 with the output signal e of the protection circuit 40, and outputs a determination result as a signal f.

Next, the operation and detection method of the detection circuit shown in FIG. 1 will be described with reference to FIG. 3 by taking as an example a case where a connection abnormality exists in a signal line. FIG. 3 is a waveform diagram showing waveforms output from each circuit.

First, when the cable A is connected, the clock signal a is input to the binary counter and the flip-flop of the detection circuit 30 via the cable A. First,
In the flip-flop, the rising edge of the clock signal a is detected, the binary counter counts the number of clocks, and the time when the abnormal cable connection test is performed.
A signal corresponding to T is output to the flip-flop. In response to these inputs, the flip-flops use the low level signal as the test signal g during the time T as the selection circuits 10 and 1
Output to 1. The selection circuits 10 and 11 select and output one of the signals input to the two sets of input terminals using the test signal as a control signal. That is, the selection circuit 10 outputs the identification signal generated by the identification signal generation circuit 80 by counting the clock signal a to four signal lines corresponding to the four output bits of the counter, and the selection circuit 11 outputs the identification signal. A synchronized signal b is output as a synchronized signal c when the synchronized 4-bit binary counter outputs 0. Cable A
Are composed of a clock signal a, a synchronization signal c, and four identification signals d generated by the identification signal generation circuit 80. This signal d is equivalent to the signal i generated by the identification signal generation circuit 60. When these signals are input to the package 2 via the cable A, the identification signal generation circuit 60 that inputs the clock signal a and the synchronization signal c outputs the identification signal i to the comparison circuit 50. The signal g is input. At this time, the comparison circuit 50 first compares the four exclusive OR circuits with the four bits of the signals i and h, respectively. In this comparison, a high-level signal is sent to a bit having a signal that does not match, and a low-level signal is sent to the inverter circuit to a bit that matches. The inverter circuit inverts the signal output from the exclusive OR circuit and outputs the inverted signal to the AND circuit. The AND circuit takes the AND of the four input signals and outputs the result to the OR circuit. This output signal is the identification signal h.
If there is a signal that does not match with each bit of the identification signal i, it is a low-level signal, and if all match, it is a high-level signal. OR circuit is A
The output signal of the ND circuit is compared with the test signal g. If there is a signal that does not match among the recognition signal h and the recognition signal i within the inspection time, all the low-level signals match. In this case, a high level signal is sent to the control circuit 70. In the control circuit 70, the test signal g is input,
Protection circuit 4 configurable with monostable multivibrator
0 corresponds to the fall time of the test signal g. By adjusting the time constant by the capacitor C and the resistor R, a signal of a low level for a time corresponding to the protection interval t is set to O as a signal e.
Output to R circuit. The OR circuit compares the output signals of the comparison circuit 50 and the protection circuit 40. If there is a different signal between the corresponding bits of the identification signal h and the identification signal i within the inspection time T, it is determined that the cable connection is abnormal, A low-level signal is output as a signal f.

In the signal lines for transmitting the synchronizing signal c and the signal lines for transmitting the clock signal a other than the four signal lines for transmitting the identification signal d, when there is a connection abnormality in these signal lines, Does not operate, or the signal f is detected as a low-level signal, so that connection abnormalities of all signal lines constituting the cable can be detected.

FIG. 4 is a circuit diagram showing another example of the comparison circuit and the control circuit. Compared with the circuit diagrams shown in FIG. 1 and FIG. 2, the cable connection abnormality detection determination result is output for each of the four signal lines. It is possible to recognize which signal line connection is abnormal.

[0016]

As described above, according to the present invention, tested against the cable connection abnormality detection circuit and method according to the invention, for inspecting for all signal lines constituting the cable, One not a single signal line It is possible to check for erroneous connection, non-connection, dropout, disconnection, and the like. In addition, since the inspection is performed within a predetermined time after the connection of the cable, the inspection time can be shortened, and the inspection can be performed immediately even when there is not enough time for the signal lines to be used. Having.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a cable connection abnormality detection circuit and a method thereof according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a comparison circuit illustrated in FIG. 1;

FIG. 3 is a waveform diagram of an output signal of each circuit shown in FIG. 1;

FIG. 4 is a circuit diagram showing another example of a comparison circuit and a control circuit.

FIG. 5 is a block diagram showing a conventional cable connection abnormality detection circuit.

FIG. 6 is a block diagram showing another conventional cable connection abnormality detection circuit.

[Explanation of symbols]

1, 2, 3 , 3 2 Package (logic board) 10, 11, 12 Selection circuit 30 Detection circuit 40 Protection circuit 50, 52 Comparison circuit 60, 62, 80 Identification signal generation circuit 70 Control circuit 72 Monitoring circuit 90 Synchronization circuit A , B, 33, 34 Cables 310, 311, 320, 321, 330, 331, 3
40,341 Connector 312,313,322,323 Storage 314,315 Selector 316 Comparator

Claims (9)

(57) [Claims] 1. A first identification signal generating means for outputting at least one signal line unique identification signal of signal Line constituting the cable according to a clock signal to recognize the connection when connection by cable between packages, the A transmission unit composed of a cable for transmitting the identification signal to a determination unit for determining a cable connection abnormality, and a test signal for detecting the clock signal and operating a cable connection abnormality detection circuit within a predetermined time after the cable connection is output. Detecting means for
A second identification signal generating unit that outputs a signal equivalent to the identification signal to the determination unit without passing through the cable according to the clock signal, and the first and second identification units within a predetermined time according to the test signal A cable connection abnormality detection circuit comprising: a determination unit that compares the identification signal output by the signal generation unit to determine a cable connection abnormality. 2. The first identification signal generating means comprises a multi-bit binary counter which counts up each time the clock signal is input and outputs the identification signal to a first selection circuit and a synchronization circuit. A first identification signal generating circuit, and a synchronization signal synchronized with the input of the identification signal when the output of the multi-bit binary counter is 0;
A synchronization circuit including a discrimination signal generation circuit and a decoder for outputting to the second selection circuit; a first selection circuit including a selector for selecting the discrimination signal in accordance with the test signal and outputting the selected signal to the cable; The cable connection abnormality detection circuit according to claim 1, further comprising a second selection circuit including a selector that selects the synchronization signal according to a signal and outputs the selected synchronization signal to the cable. 3. The cable according to claim 2, wherein the number of bits of the plurality of binary counters constituting the first identification signal generating circuit is two less than the number of signal lines constituting the cable. Connection abnormality detection circuit. 4. The second identification signal generating means is constituted by a binary counter of a plurality of bits equivalent to that of the first identification signal generation circuit, and is reset each time the synchronization signal is inputted, 2. The cable connection abnormality detection circuit according to claim 1, further comprising a second identification signal generation circuit that counts up and generates an identification signal each time a signal is input. 5. The method according to claim 1, wherein the determining unit uses the identification signal output from the first selection circuit via the cable as a first input signal and uses the identification signal output from the second identification signal generation circuit as a second input signal. A comparison circuit for comparing the first and second input signals as input signals of the first and second input signals; and a plurality of binary bits constituting the first identification signal generation circuit by receiving the comparison result of the comparison circuit and the test signal. The cable connection abnormality detection circuit according to claim 1, further comprising a control circuit that outputs the comparison result as a determination result of the cable connection abnormality detection circuit after a time required for resetting the counter for the first time. 6. A plurality of exclusive OR circuits for comparing the identification signals so that each bit of the identification signals correspond to each other, and an output of the plurality of exclusive OR circuits. A plurality of inverter circuits to be inverted; an AND circuit for ANDing outputs of the plurality of inverter circuits ; a logical sum of an output of the AND circuit and the test signal ;
6. The cable connection abnormality detecting circuit according to claim 5, wherein the circuit is connected to an OR circuit which outputs the signal as an output . 7. The protection circuit according to claim 1, wherein the control circuit receives the test signal and recognizes a time required for resetting a multi-bit binary counter constituting the first identification signal generation circuit for the first time. a protection circuit to be output to the OR signal and the logical sum of the protection time signal
7. The cable connection abnormality detecting circuit according to claim 6, comprising an OR circuit for outputting . 8. The cable connection abnormality detection circuit according to claim 5, wherein the comparison circuit compares a plurality of exclusive OR circuits that correspond to each bit of the identification signals, and the plurality of exclusive OR circuits. A plurality of inverter circuits for inverting the outputs of the exclusive OR circuits; and ORing the outputs of the plurality of inverter circuits with the test signal, and outputting the result as a plurality of OR signals.
And a control circuit for receiving the test signal and recognizing a time required for resetting a multi-bit binary counter constituting the first identification signal generation circuit for the first time. A protection circuit that outputs a protection time signal to an OR circuit; and a logical sum of the plurality of OR signals and the protection time signal .
A plurality of OR circuits, wherein each of the plurality of OR circuits is two less than the number of signal lines constituting the cable. 9. A first detecting step in which a clock signal generated in the first package and recognizing that the cable is connected is transmitted to the second package, and a clock transmitted in the first detecting step. a second detecting step of generating a test signal for operating the time circuit performs connection abnormality detection test on the basis of the signal, signal Line constituting the cable by inputting the test signal generated in the second detection step a third detection step of transmitting a unique identification signal to at least one of said signal Line,
A fourth detection step in which the identification signal transmitted in the third detection step is transmitted from the first package to the second package via the cable, and wherein the identification signal is transmitted in the second package. A fifth detection step of generating an identification signal equivalent to a signal, and a fifth step of detecting a cable connection abnormality by comparing the identification signals generated in the third and fifth detection steps in the second package. 5. A method for detecting a cable connection abnormality, comprising: