JPS6134193U - display device - Google Patents
display deviceInfo
- Publication number
- JPS6134193U JPS6134193U JP11826384U JP11826384U JPS6134193U JP S6134193 U JPS6134193 U JP S6134193U JP 11826384 U JP11826384 U JP 11826384U JP 11826384 U JP11826384 U JP 11826384U JP S6134193 U JPS6134193 U JP S6134193U
- Authority
- JP
- Japan
- Prior art keywords
- frequency divider
- display device
- pulse
- waveform
- triggered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案によるディスプレイ装置の一実施例を示
す要部ブロック図、第２図ａ， ｂ、第３図ａ， ｂは
第１歯に示すブロック図の動作を説明するための波形図
である。
ＩＲ， １．， １８・・・ビデオ増幅器、２，４
・・・，第１、第２分周器、３，５・・二第１、第２マ
ルチバイブレーター回路。FIG. 1 is a block diagram of main parts showing an embodiment of a display device according to the present invention, and FIGS. 2a and 2b and 3a and 3b are waveform diagrams for explaining the operation of the block diagram shown in the first tooth. It is. IR, 1. , 18... video amplifier, 2,4
..., first and second frequency dividers, 3,5...2 first and second multivibrator circuits.
Claims (1)
を陰極線管に映像表示するディスプレイ装置に於いて、
データ処理装置から供給される映像信号に同期したドッ
トクロックパルスを分周シて水平同期信号の周期に一致
するパルスを出力する第１分周器と、この第１分周器の
出力信号によ−ってトリガされることにより波形整形お
よび位相調整された水平同期信号を再生す′る第１マル
チバ、 イブレーター回路と、前記第１分周器の出力信
号を分周することにより垂直同期信号の周期に一致する
パルスを出力する第２分周器と、この分周器の出力信号
によってトリガされることにより波形撃形および位相調
整された垂直同期信号を再生する第２マルチバイブレー
ター回路とを備えたことを特徴とするディスプレイ装ｔ
。In a display device that displays output information from a data processing device such as a personal computer on a cathode ray tube,
A first frequency divider divides the dot clock pulse synchronized with the video signal supplied from the data processing device and outputs a pulse that matches the period of the horizontal synchronization signal. - a first multi-verter circuit that regenerates the waveform-shaped and phase-adjusted horizontal synchronizing signal when triggered by the first frequency divider; A second frequency divider that outputs a pulse that matches the period, and a second multivibrator circuit that reproduces a waveform and phase-adjusted vertical synchronization signal by being triggered by the output signal of the frequency divider. A display device characterized by
.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11826384U JPS6134193U (en) | 1984-07-31 | 1984-07-31 | display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11826384U JPS6134193U (en) | 1984-07-31 | 1984-07-31 | display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6134193U true JPS6134193U (en) | 1986-03-01 |
Family
ID=30677152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11826384U Pending JPS6134193U (en) | 1984-07-31 | 1984-07-31 | display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6134193U (en) |
-
1984
- 1984-07-31 JP JP11826384U patent/JPS6134193U/en active Pending
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