JPS6126383A - Scan line converter - Google Patents

Abstract

PURPOSE:To convert the number of scan lines into 1/2 by adding an original signal and a signal obtained by delaying the original signal by one horizontal period at a level ratio of 1/4 and 3/4 and at that of 3/4 and 1/4 in one field and the other field, respectively. CONSTITUTION:A television signal with high finess degree from an antenna 1 is received by a tuner 2, comes to be a composite signal and is supplied to a selector circuit 3. Moreover, saod signal is supplied to the signal selector circuit 3 through one-horizontal period delay circuit 4. The signal from the tuner 2 is synchronously separated in a synchronous separator circuit 5, and supplied to a field deciding circuit 6. After it is discriminated to be an odd or even field, it is supplied to the selector circuit 3. One signal of the selector circuit 3 is supplied to a 1/4 level converter 7, while the other signal is supplied to a 3/4 level converter 8. After outputs of the converters are added by an adder 9, they are subjected to the time base expansion at the prescribed ratio in a time base expansion circuit 10, and supplied to a monitor receiver 12 through an adder 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a scanning line conversion device used when, for example, a so-called high-definition television with 1125 scanning lines is received by an NTSC system device with 525 scanning lines. .

BACKGROUND ART AND PROBLEMS So-called high-definition televisions have been proposed. This TV has a large number of scanning lines, 1125, and an aspect ratio of 3:5.
This is different from conventional systems such as NTSC. Therefore, in order to receive such television images, a new dedicated device is required.

However, it is expected that equipment for receiving such high-definition television will be extremely expensive. Therefore, it has been considered to convert the scanning lines of high-definition television so that it can be received by devices using conventional systems such as NTSC. If you do this, the screen will not have high definition, but you will still be able to watch the program.

That is, for example, in a high-definition television, there are 1045 video signals out of 1125 scanning lines. On the other hand, NTS
In the C method, there are 5 4Bs out of 525. Therefore, for example, 75 of the scanning lines at the top and bottom of a high-definition television are deleted,
If you convert the rest at a ratio of 1/2, it becomes (1045-75)
A total of 2 = 485, and high-definition television images can be viewed on an NTSC system device.

In that case, the 4th vj! As shown in J, input terminal (4
The video signal supplied to 1) is delayed by one horizontal period delay circuit (4
2), and convert this delayed signal and the original video signal into 1/2 level converters (43) and (44), respectively.
The adder (45>) adds the sum.

According to this, for example, in an odd field, the first scanning line (51o) and the second scanning line (52o) as shown in FIG.
o), a first scan line (51o') is formed by conversion, and a second scan line (52o') is formed by conversion from a third scan line (53o) and a fourth scan line (54o). Ru.

On the other hand, in the even field, in order to maintain the 1:2 interlaced scanning line arrangement with the odd field, the second scanning line (52e) and the converted first scanning line (51e') must be are made equal, and the fourth scan line (54e)
and the converted second scanning line (52e') are made equal. Therefore, in FIG. 4, the original signal from the input terminal (41) and the added signal from the adder (45) are connected to the switch (
46) for each field and output terminal (47)
For example, in an odd field, a signal obtained by adding two scanning lines at a level of 1/2 is taken out to the output terminal (47), and in an even field, the corresponding scanning line is directly sent to the output terminal (47). It will be taken out.

However, in this device, the circuit configurations through which light passes through odd and even fields are different. When the signals are passed through different circuits in this way, it is difficult to adjust the level, etc., and images such as ``Furi'' and ``7'' tend to occur.

Furthermore, the configuration in which the delay circuit (42) for one horizontal period, the level converters (43), (44), and the adder (45) are combined is a so-called comb filter configuration.
The filter characteristic is a trap characteristic with an attenuation pole of +fn (fn is the horizontal frequency) as shown by curve (61) in FIG. Here, in the video signal of passing birds, +
, f x , there is no signal, but the so-called shoulder portion of the characteristic curve is a problem, and the video signal in this portion is degraded. - Since such deterioration occurs, for example, only in odd-numbered fields, there is a risk that screen deterioration such as flicker may also occur due to this.

OBJECTS OF THE INVENTION In view of these points, the present invention is directed to converting scanning lines with a simple configuration.

Summary of the Invention The present invention adds an original signal and a signal obtained by delaying the original signal by one horizontal period at a level ratio of 1/4 to 3/4 in the - field, and 3/4 in other fields. This is a scanning line conversion device that converts the number of scanning lines to 1/2 by adding at a level of 1/4. According to this device, scanning lines can be converted with a simple configuration. can.

Embodiment In FIG. 1, a high definition television signal from an antenna (1) is received by a tuner (2) and converted into a composite signal.

This signal is supplied to the first input terminal of the selector circuit (3). Furthermore, the signal from the tuner (2) is supplied to a delay circuit (4) for one horizontal period, and the signal from this delay circuit (4) is supplied to the second input terminal of the selector circuit (3).

Further, the signal from the tuner (2) is supplied to a synchronization separation circuit (5) to separate the synchronization signal. This separated synchronization signal is supplied to a field discrimination circuit (6), which discriminates between odd and even two-yield, and this discrimination signal is supplied to a control terminal of a selector circuit (3).

Then, in the selector circuit (3), according to the discrimination signal, for example, in an odd field, the signals from the first and second input terminals are directly taken out to the first and second output terminals G, and in an even field, they are reversed. taken out.

The signal from the first output terminal of this selector circuit (3) is supplied to the 1/4 level converter (7), and the signal from the second output terminal is supplied to the 3/4 level converter (8). Supplied. Further, these level converters (71 (signals from 81 are added to adder +9)) are added together, and this added signal is supplied to a time axis expansion circuit QOI, where time axis expansion is performed at a predetermined ratio, which will be described later. The signal from the expansion circuit α@ is supplied to the receiver (12) through an adder (11).

Here, from the adder (9), first, in the odd field, a signal is obtained by adding a signal obtained by converting the level of the previous scanning line to 374 and a signal obtained by converting the level of the next scanning line to 1/4. In an even field, the level of the previous scanning line is converted to 1/4, and the level of the next scanning line is converted to 3/4.
A signal obtained by adding the level-converted signal and the level-converted signal is extracted. Then, this signal is extracted by the expansion circuit a after every other scanning line is expanded in a predetermined time axis.

Therefore, from the expansion circuit QO), the scanning line (21o
) (22o)...(21e) (22e)
Broken lines (21o') (22o')
)...(21e') (22e')...
A signal corresponding to the position indicated by is formed and extracted.

Note that 1:2 interlacing is maintained at these positions. Also, in reality, signals are not formed until after the lower scanning line, so for example, the dashed-dotted lines (21o") (22o") after the -scanning period, respectively.
...(21e") (22e")... are taken out at the positions.

This reduces the number of scanning lines to 1/2. i.e. 104
The 5-75 lines become 485 lines, and signals with 1:2 interlacing maintained are formed.

In addition, the horizontal period is approximately 30 μsec for high-definition television, which is 2
It is multiplied to about 60 μsec. On the other hand, in the NTSC system, it is approximately 63.5 μsec. Therefore, the position of the horizontal synchronization signal changes. Therefore, as shown in the figure, the separated synchronization signal is supplied to a second synchronization signal forming circuit (13) to form a desired synchronization signal and added to the output signal by an adder (11).

In addition, in the receiver (12), it is necessary to slightly widen the tolerance for horizontal scanning oscillation so that a period of 60 μsec can be pulled in, but even conventional receivers generally have this tolerance range.

Furthermore, the aspect ratio of a high-definition TV screen is 3:5.
This is different from 3:4 in the NTSC system.

Therefore, in the above-mentioned time axis expansion circuit aO), the horizontal scanning time is approximately 1, which is a ratio of 3:4 for 970 scanning lines.
The time axis is expanded so that 8.36 μsec becomes a horizontal scanning time of about 52.46 μsec, which is a ratio of 3:4 to 485 scanning lines. .

The scanning line is converted in this way, and since this device only uses a simple delay circuit, level converter, etc., the entire device can be manufactured at extremely low cost. Note that in the case of analog processing, the level converter can be configured with a simple linear amplifier.

Furthermore, since signals always pass through the same circuit in odd and even fields, the screen stability is extremely high.

In addition, in the above-mentioned device, the characteristics of the comb filter that combines the delay circuit (4), level converter (7), +81, and adder (9) are as shown by the curve (62) in FIG. The screen deterioration caused by this is extremely small.

Furthermore, in the above device, the output of the tuner (2) is set to A
It is also possible to perform D conversion and digital processing. In that case, it will be done as shown in FIG. 3, for example. In the figure, when converting the level of a digital signal to, for example, I/4, the lower two bits are deleted and the remaining bits are shifted two lower bits. If the signal is to be reduced to 3/4, it may be added to a signal which has been reduced to 1/2 by a 1-bit shift similar to the signal which has been reduced to 1/4 as described above.

Therefore, the signal from the tuner (2) mentioned above is sent to the AD converter (
31) and is converted into, for example, an 8-bit digital signal. This signal is supplied to a delay circuit (32) for one horizontal period consisting of a shift register or memory. The lower two bits of the input and output signals of this delay circuit (32) are deleted, and the input and output signals are processed into an 8-bit three-manufactured adder (33).
) is supplied to the lower 6 bits of the first and second inputs, respectively. "θ" is supplied to the upper two bits of the first and second inputs, respectively.

Furthermore, the lower 1 bit of each of the input and output signals of the delay circuit (32) is deleted, and the signals are supplied to a 7-biso, 12-manpower selector circuit (34). The signal selected by this selector circuit (34) is then supplied to the lower 7 bits of the third input of the adder (33). "θ" is supplied to the upper one bit of this third input.

As a result, when the selector (34) is switched to the upper side, 3/4 of the previous scanning line and 1/4 of the next scanning line are added, and when the selector (34) is switched to the lower side, the previous scanning line is added. 1/-4 of
and 3/4 of the next scanning line are added.

This addition output is then passed through a time axis expansion circuit (35) consisting of a shift register or memory to a D'A converter (
36) and the converted analog signal is sent to the adder (
6).

This also allows scanning line conversion to be performed in the same way as in the analog processing described above.

Further, this device can be applied to a device that displays an image by arranging a large number of display elements in a matrix, and when adjusting the number of scanning lines to match that of the display device.

Effects of the Invention According to the present invention, scanning line conversion can now be performed with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of the present invention, Fig. 2 is a diagram for explaining the same, Fig. 3 is a block diagram of another example, and Figs. 4 to 6 are diagrams for explaining the conventional device. It is a diagram. (3) is a selector circuit, (4) is a delay circuit, (6) is a field discrimination circuit, +71. (81 is a level converter,
(9) is an adder. Fig. 1 Fig. 2 ST number sentence Fa-rtF A style number feed I-do. Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] The original signal and a signal obtained by delaying this original signal by one horizontal period are added at a level ratio of 1/4 and 3/4 in one field, and at a level ratio of 3/4 and 1/4 in the other fields. A scanning line conversion device that converts the number of scanning lines to 1/2 by adding them.