JP2708848B2 - Television converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, particularly to a television system converter having a digital filter for converting an aspect ratio of a television signal.

[Conventional technology]

FIG. 2 is a diagram showing a television receiver as a prior art by the applicant, in which (1) is a first input terminal, (2) is an A / D converter,
(3) is a de-emphasis circuit, (4) is a first PLL circuit, (5) is a second PLL circuit, (6) is a scanning line conversion circuit, (7) is a luminance signal processing circuit, and (8) is a color difference. Signal processing circuit, (9) D / A converter, (10) switch circuit, (1)
1) Inverse matrix circuit, (12) CRT, (13) second
, An input terminal (14), a third input terminal, (15) an NTSC decoder, (16) a timing generation circuit, (17) a vertical deflection circuit, and (18) a horizontal deflection circuit.

Next, the operation will be described. MUSE for input terminal (1)
A high vision signal band-compressed according to the method is applied. The high vision signal is a signal having 1125 scanning lines, a field frequency of 60 Hz, and a 2: 1 interlace. MUSE
In the system, the high vision signal is compressed into a band of 8 MHz and transmitted by one channel using a broadcasting satellite. This compression is performed by an offset subspring, and an offset between fields and between frames is used for a stationary portion, and an offset between lines is used for a moving image portion. The two color difference signals (RY, BY) are time-compressed and multiplexed during the blanking period of the luminance signal.

The high-vision signal (hereinafter, referred to as a MUSE signal) according to the MUSE method applied to the input terminal (1) is converted into a digital signal by an A / D converter (2), and a de-emphasis circuit (3) and a first PLL circuit are provided. (4) are respectively applied. The first PLL circuit (4) reproduces a correct sampling clock based on the phase information in the MUSE signal. The correct sampling clock is supplied to the A / D converter (2), and the MUSE signal sampled at the correct phase is applied to the de-emphasis circuit (3). Day emphasis circuit (3)
The frequency characteristic of the SE signal is corrected, and the corrected signal is applied to the scanning line conversion circuit (6). The scanning line conversion circuit (6) discards 75 scanning lines from 1125 scanning lines per frame of the MUSE signal to convert them to 1050 scanning lines per frame, and uses a memory, for example, to write data at the speed of a write clock. Is the speed obtained from the time axis of the MUSE signal, and the read clock speed is the speed obtained from the time axis of the NTSC signal. This read clock is output from the second PLL circuit (5). Therefore, from this scanning line conversion circuit (6),
It has 1050 scanning lines, 2: 1 interlace, and a signal with a field frequency of 60 Hz.

The output signal of the scanning line conversion circuit (6) is applied to each of a luminance signal processing circuit (7) and a color difference signal processing circuit (8). In the luminance signal processing circuit (7), field interpolation corresponding to line offset sampling is performed, the band is restored, and then interlace conversion is performed.
A signal of 525 lines per frame, 2: 1 interlace, and a field frequency of 60 Hz can be obtained. On the other hand, in the color difference signal processing circuit (8), two color difference signals (R-
Y, BY) is extended in time, and a field interpolation process is performed to restore the band. Thereafter, an interlace conversion is performed to convert the signals into 525 interlace signals per frame. The luminance signal and the two color difference signals (RY, BY), which are output signals of the luminance signal processing circuit (7) and the color difference signal processing circuit (8), are applied to a D / A converter (9). And converted to an analog signal.

On the other hand, the NTSC signal applied to the third input terminal (14)
Guided to the NTSC decoder (15). The NTSC decoder (15) includes, for example, means for separating a luminance signal and a color difference signal and means for demodulating the color difference signal, and outputs a luminance signal and two color difference signals from the applied NTSC signal. The output signal of the D / A converter (9) and the output of the NTSC decoder (15) are applied to a switch circuit (10). Switch circuit (10)
Is configured to output one of two signals applied to the switch circuit (10) according to a signal applied to a second input terminal (13) described later. The output signal of the switch circuit (10) is input to an inverse matrix circuit (11), and an RGB primary color signal is generated. The inverse matrix circuit (11) is the same as that implemented in current television receivers. The output signal RGB of the inverse matrix circuit (11) is applied to a CRT (12) and displayed. The deflection timing of the CRT (12) is generated by a timing generation circuit (16), and the vertical deflection circuit (17)
The horizontal deflection circuit (18) is driven by a signal from the timing generation circuit (16). The vertical deflection circuit (17) is configured such that the deflection width can be controlled by a signal applied to a second input terminal (13) described later. The second input terminal (13) displays the MUSE signal on the TV screen or NTSC
A control signal for selecting whether to display a signal is applied. As described above, this signal is connected to the switch circuit (1
0) and the vertical deflection circuit (17). The switch circuit (10) outputs the output signal of the D / A converter (9) or the N signal in accordance with the control signal of the second input terminal (13).
Pass the output signal of the TSC decoder (15). The vertical deflection circuit (17) is connected to the switch circuit (10) by the NT.
When the output signal of the SC decoder (15) is selected, it is normally driven with the NTSC vertical deflection width. The output signal of the D / A converter (9) has an aspect ratio as shown in FIG.
4: 3 aspect ratio of 16: 9 video compressed in the horizontal direction
3B is a vertically long image as shown in FIG. Therefore,
When the switch circuit (10) selects the output of the D / A converter (9), the vertical deflection circuit (17)
The vertical deflection width is reduced so that a vertically long image as shown in FIG. 3B becomes an image with an aspect ratio of 16: 9 as shown in FIG. 3C.

[Problems to be solved by the invention]

Since the conventional television system converter is configured as described above, in the case of displaying a high-vision image on an almost full screen on an NTSC monitor, it must be modified so that the vertical deflection circuit of the NTSC monitor can be externally controlled. As a result, the NTSC monitor already on the market had the disadvantage that high-vision images could not be displayed on almost the entire screen.

The present invention has been made to solve the above problems, without modifying the vertical deflection circuit of the NTSC monitor,
It is an object of the present invention to obtain a television system converter capable of displaying a high-vision image on an NTSC monitor almost in full screen.

[Means for solving the problem]

The television converter according to the present invention comprises: means for converting scanning lines from 525 lines to 350 lines; means for vertically compressing the converted signal in the vertical direction; and a blanking period for the time-compressed signal. To make the number of scanning lines 525.

[Action]

The television converter of the present invention converts the scanning lines from 525 lines to 350 lines, vertically compresses the time, and adds a blanking period, so that the aspect ratio is correctly converted and the high-vision image is displayed on the NTSC monitor. Displays almost the entire screen of.

(Example of the invention)

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same symbols as those in FIG. 2 indicate the same components.
(19) a scanning line for converting a scanning line of a luminance signal (Y signal) and a color difference signal (RY, BY signal) output from the luminance signal processing circuit (7) and the color difference signal processing circuit (8). A conversion filter circuit, (20) is a speed conversion memory circuit, and (21) is a blanking insertion circuit. FIG. 4 is a diagram similar to FIG.
9) shows a scanning line conversion filter circuit, wherein (22) is an input terminal, (23) is a first vertical filter circuit, (24) is a second vertical filter circuit, and (25) is a first vertical filter circuit. A selector circuit for selecting (23) and an output of the second vertical filter circuit (24), (26) is an input terminal, (27) is a field determination circuit, and (28) is an output terminal.

The MUSE signal input to the input terminal (1) is quantized by the A / D converter (2), and the clock is reproduced by the first PLL circuit (4). On the other hand, the frequency characteristics of the quantized signal are corrected by the de-emphasis circuit (3). The corrected signal is input to the scanning line conversion circuit (6),
1050 of the scan lines are written to memory and read at a slower rate than write, 1050 lines / frame, 2: 1
Interlaced, converted to a signal with a field frequency of 60 Hz. The converted output is processed by two systems of luminance and color difference.
The luminance signal (Y) is subjected to field interpolation processing and scanning line conversion from 1050 lines to 525 lines in a luminance signal processing circuit (7).
On the other hand, since the color difference signals (RY, BY) are time-axis-compressed and multiplexed during the horizontal blanking period of the luminance signal, they are time-axis expanded (TCI decoder) by the color-difference signal processing circuit (8).
Furthermore, field interpolation processing and scanning line conversion from 1050 lines to 525 lines are performed. The color difference signal processing circuit (8) outputs two color difference signals RY and BY signals.

The signals (Y, RY, BY) output from the luminance signal processing circuit (7) and the color difference signal processing circuit (8) are 525 lines / frame, a field frequency of 60 Hz, and a 2: 1 interlace signal. It is. The signals (Y, RY, BY) are shown in FIG.
It is a vertically long image like. The signal is input to a scanning line conversion filter circuit (19). The operation of the scanning line conversion filter circuit (19) will be described with reference to FIGS.

The 525 / 60HZ signal input to the input terminal (22) is supplied to the first vertical filter circuit (23) and the second vertical filter circuit (2
Entered in 4). The first vertical filter circuit (23) is composed of a fourth-order digital filter, and its tap coefficient is 1 /
16, 1/4, ^3/8 , 1/4, 1/16, and the transfer characteristic is H _(Z) = (1 + 4Z ^-h + 6Z- ^2h + 4Z- ^3h + Z ^-4h ) / 16 Z- ^h : 1 horizontal It is expressed as scan line delay. The second vertical filter circuit (24) is composed of a fifth-order digital filter, the tap coefficient of which is 1 / 32,5 / 3.
With 2,5 / 16,5 / 16,5 / 32,1 / 32, the transfer characteristic is H _(Z) = (1 + 5Z- ^h + 10Z- ^2h + 10Z- ^3h + 5Z- ^4h + Z- ^5h ) /
32 Z ^-h : expressed by 1 horizontal scan line delay. The signals a and b output from the first vertical filter circuit (23) and the second vertical filter circuit (24) are input to the selector circuit (25). The selector circuit (25) uses the signal output from the field determination circuit (27) to
The signal a is selected during the first field period and the signal b is selected during the second field period, and is output to the output terminal (28). The above operation will be described with reference to FIG. In FIG. 5, the mark "印" indicates the input terminal (22).
, A black line indicates a second field scanning line, a black square indicates a first field scanning line of a signal input to the output terminal (28), and a white square indicates a second field. 3 shows a scanning line. Symbols A1 to A7 are the scanning lines of the first field of the input signal, B1 to B7 are the scanning line numbers of the second field, a1 to a4 are the scanning lines of the first field of the output signal, b1 to
b4 indicates the scanning line of the second field. The first field (A1 to A7) and the second field (B1 to B7) of the input signal are interlaced. The first vertical filter circuit (2
3) scan line conversion of the input signal scan lines (A1 to A7) to the output signal scan lines (a1 to a4). At this time, the scanning line is 3
Is converted at a ratio of two to two, and the phase is such that a1 is A1 and A2
A2 is in phase with A3, a3 is between A4 and A5, and a4 is in phase with A6. The second vertical filter circuit (2
4) scan line conversion of input signal scan lines (B1 to B7) to output signal scan lines (b1 to b4), and at this time, three to two scan lines are converted. The phase of b1 is B1 and B2
3: 1 phase, b2 is 1: 3 phase of B3 and B4, b3 is 3: 4 of B4 and B5:
A phase of 1 and b4 is a 1: 3 phase of B6 and B7. The selector circuit (25) outputs the output (a1 to a4) of the first vertical filter circuit (23) during the first field, and outputs the output (a1 to a4) during the second field during the second field.
The output (b1 to b4) of the vertical filter circuit is selected and output to the output terminal (28). The output signal is b1 is the center of a1 and a2, b2 is
The relationship is located at the center of a2 and a3, and the first field (a1 to a4) and the second field (b1 to b4) of the output signal
Are interlaced. The signal output to the output terminal (28) is a signal of 350 lines / 60Hz.

A signal (Y, RY, BY) of 350 lines / 60 HZ as shown in FIG. 6A is input from the scanning line conversion filter circuit (19) to the speed conversion memory circuit (20). The speed conversion memory circuit (20) is composed of a memory, and reads out the signal compressed at a speed faster than the writing so that the time-compressed signal in the vertical direction as shown in FIG. 6 (b) is supplied to the blanking insertion circuit (21). Output. In the blanking insertion circuit (21), blanking is added to the hatched portion shown in FIG. 6B for a period of 175 scanning lines, so that 525 lines / 60 Hz (effective scanning lines 350
) Signal (Y, RY, BY). The signal obtained in this way is an image whose vertical length has been corrected as shown in FIG. 3 (c). The signals (Y, RY, BY) obtained as described above are
It is converted to an analog signal by the D / A converter (9) and the switch (1
0) is input. On the other hand, N input to the input terminal (14)
The TSC signal is decoded by an NTSC decoder (15) into Y, RY, and BY signals and input to a switch (10). Switch (1
0) selects one of the output of the D / converter (9) and the output of the NTSC decoder (15) according to the MUSE / NTSC selection signal input from the input terminal (13), and outputs it to the inverse matrix circuit (11). Y, R−Y, B− input to the inverse matrix circuit (11)
The Y signal is converted to an RGB signal and displayed on the CRT (12).

In the above embodiment, the case where the television receiver is incorporated in the television receiver has been described. However, the NTS is provided after the D / A converter (9).
NTSC is provided by installing a C encoder and modulating the color difference signal.
An adapter type converter that outputs a composite signal and a Y / C separate signal may be used.

[Effects of the Invention] As described above, according to the present invention, since the aspect ratio conversion is configured to perform scanning line conversion by the vertical filter, compress the time in the vertical direction, and add a blanking period,
There is the effect that almost the entire screen of the high vision image can be monitored with the correct aspect ratio without modifying the vertical deflection circuit of the NTSC monitor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a television system converter according to one embodiment of the present invention, FIG. 2 is a block diagram showing a conventional television system converter, FIG. 3 is a diagram for explaining the operation of FIG. FIG. 4 is a block diagram of the scanning line conversion filter circuit in FIG. 1, FIG. 5 is a diagram for explaining the operation of FIG. 4, and FIG.
FIG. 2 is a diagram for explaining the operation of FIG. In the figure, (1), (13), (14), (22) and (26) are input terminals,
(2) is an A / D converter, (3) is a day emphasis circuit,
(4) and (5) are PLL circuits, (6) is a scanning line conversion circuit,
(7) is a luminance signal processing circuit, (8) is a color difference signal processing circuit, (9) is a D / A converter, (10) is a switch, (11) is an inverse matrix circuit, (12) is a CRT, (15) ) Is an NTSC decoder, (16) is a timing generation circuit, (17) is a vertical deflection circuit, (18) is a horizontal deflection circuit, (19) is a scanning line conversion filter circuit, (20) is a speed conversion memory circuit, and (21) ) Is a blanking insertion circuit, (23) and (24) are vertical filter circuits,
(25) is a selector circuit, (27) is a field judgment circuit,
(28) is an output terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A means for converting 1125 scanning lines of a MUSE signal into 1050 scanning lines; a means for performing field interpolation processing on the converted luminance signal; Means for converting the color difference signals converted into scan signals into time signals, means for extending the time axis of the color difference signals converted to the scan lines to output RY and BY color difference signals, and means for performing field interpolation on the two color difference signals And a television system converter for converting a MUSE signal into an NTSC signal having means for converting the chrominance signal into an interlace signal of 525 lines, using 525 scanning lines per frame and changing from three lines to two lines. Two digital filters having different coefficients to be converted,
Means for converting the two digital filters into 350 scanning lines by switching them for each field; means for vertically compressing the signal converted to 350 scanning lines in the vertical direction; Means for adding a ranking period to reduce the number of scanning lines to 525 lines.