JP2765999B2 - Television receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition television broadcast receiving apparatus in which a still image and a moving image of a video signal are band-compressed by different methods by multiple sub-sampling processing. In particular, it relates to a receiver having a simplified configuration.

[Conventional technology]

In recent years, as televisions have become larger, higher definition of images has been required. Against this background, NHK has established the MUSE (Multiple S
A ub-Nyquist Sampling Encoding (MUSE) system was developed. The MUSE system is scheduled to be broadcast regularly from the spring of 1989, starting with the test broadcasting at the Seoul Olympics in 1988, and has already reached the practical stage.

The MUSE method is described in the document "NHK Technical Research Journal, Vol. 39, No. 2, No. 2, 172, p18-p53". Its features are an interlaced signal with 1125 scanning lines and a frame frequency of 30 Hz, and a screen aspect ratio of 16: 9. 24MHz still image transmission band, 16MHz video transmission band signal
The band is compressed to 8 MHz and transmitted.
The SE method is a multiplex sub-sample band compression method in which a moving image is thinned out every other pixel every one horizontal cycle, and a still image is thinned out every other pixel so as to make one cycle in two frames. The band compression method is completely different for still images and moving images. Therefore, the signal processing in the MUSE decoder also has two signal processing systems, ie, still image / moving image processing.
It has a motion detection circuit and the like for determining a moving image. This is shown in FIG.

FIG. 2 shows a signal processing circuit of the MUSE decoder. Second
In the figure, reference numeral 201 denotes an 8 MHz analog signal input terminal for demodulating a received MUSE signal and returning it to a baseband; and 202, an analog / digital converter (hereinafter, an A / D converter) for converting the analog signal into a digital signal. ), 203
Is a de-emphasis processing unit, 204 is an inverse Γ processing unit that performs inverse gamma (Γ) correction, and 205 is a frame memory,
A motion detection processor 206 for detecting the difference between the current signal and the signal of one frame before to detect the motion of the image. The 206 detects a synchronization signal and a control signal from the digitized MUSE signal output from the A / D converter 202. A synchronization processing unit that extracts a signal and generates a system clock. Inside the frame indicated by 225,
A luminance signal processing unit for a still image, a frame indicated by 226 is a luminance signal processing unit for a moving image, 207 is an interpolation filter between frames, 208 is a low-pass filter (hereinafter, referred to as LPF), 209 is a frequency conversion processing unit that converts the sampling frequency, 210 is an interpolation filter between fields, 211 is
The interpolation filter in the field. Reference numeral 212 denotes a frequency conversion processing unit similar to the frequency conversion processing unit 209, and reference numeral 213 denotes a still image signal processed by the still image luminance signal processing unit 225 and a still image signal processed by the moving image luminance signal processing unit 225. This is a mixer (hereinafter, referred to as a MIX circuit) that mixes the moving image signal with the motion detection signal 205. The above is a block for processing a luminance signal, and the luminance signal subjected to the separate processing for the moving image and the still image is input to the RGB matrix circuit 217 at the next stage. Reference numeral 232 denotes a color difference signal processing unit for a still image, reference numeral 233 denotes a color difference signal processing unit for a moving image, reference numerals 214 and 226 denote a time axis expansion processing unit (hereinafter, referred to as a TCI decoder) for color signals,
Reference numeral 15 denotes a chroma interpolation processing unit between fields, and 227 denotes a chroma interpolation processing unit within a field. 228 is a MIX circuit that mixes the color difference signals processed for still images and moving images by the motion detection signal 205, 229 is a line-sequential decoder unit, and 234 and 235 are
The frequency conversion processing units 230 and 231 for color difference signals that operate in the same manner as the frequency conversion processing unit 209 are LPFs.
The above is a block for processing the color difference signal, and the color difference signal subjected to such processing is input to the RGB matrix circuit 217 at the next stage. 217 converts the luminance and color difference signals to red
RGB matrix circuit for converting to green / blue RGB signals, 218, 21
9,220 are analog / digital converters (hereinafter referred to as D / A) for converting red, green, and blue RGB signals into analog signals, respectively, 221,222,223 are LPFs, and 224 is an aspect ratio of 1
6: 9 1125 interlaced scan display.

In the MUSE decoder, the signal processing unit for a still image is generally independent of the luminance signal and the color difference signal as shown in the above configuration.
225 and 232 and the moving image signal processing units 226 and 233 are provided, and have a complicated circuit configuration. Next, the circuit configuration of the moving image color difference signal processing unit 233 in FIG. 2 will be described with reference to FIG.

FIG. 6 shows a chroma interpolation circuit 227 of the color difference signal processing unit 233 for a moving image in the conventional example of FIG.
The MIX circuit 228 is omitted from the configuration of the processing circuit up to this point. Sixth
In the figure, reference numeral 801 denotes an input terminal of an output signal from the field interpolation circuit 211 in the conventional example of FIG.
Is a latch circuit using 16 MHz as a clock, 804 and 808 are adders, and 806 and 807 are line memories. 809 and 810 are select switches that change every horizontal scanning synchronization, and 811 and 812 are R- switches.
Y, BY color difference signal output terminal.

In the figure, an input terminal 801 receives an output signal from a field interpolation circuit 211. The output signal from the field interpolation circuit 211 is input to the latch circuit 802 via the input terminal 801 and is latched by a clock of 16 MHz. Further, the adder 804 adds the output signals from the latch circuits 802 and 803 and performs horizontal chroma interpolation. The chroma-interpolated signal is input to the latch circuit 805 and the
And supplied to the line memory 806. The line memories 806 and 807 have a capacity (about 6K) capable of delaying the color signal sampled at 32 MHz by one horizontal scanning period.
bit). In each of the line memories 806 and 807, one horizontal scanning period (hereinafter, referred to as an input signal)
Abbreviated as 1H. ) A delayed signal is obtained. The adder 808 calculates the average of the horizontal chroma-interpolated signal from the latch circuit 805 and the signal delayed by 2H by the line memories 806 and 807. Further, the signals from the adder 808 and the signal from the line memory 806 are input to the select switches 809 and 810 which are switched every horizontal scanning synchronization, and are switched every horizontal scanning and output terminals 811,
Sent to 812. Here, it is assumed that the RY signal from the line memory 806 has been selected and obtained by the select switch 810 at the output terminal 811, for example. At this time, the output terminal 812
, A BY signal obtained by averaging the signal delayed by 1H and the signal advanced by 1H with respect to the RY signal is obtained.

As described above, the conventional MUSE decoder color signal moving image processing circuit requires two large-capacity line memories of about 6 Kbits for line-sequential decoding of the color difference signal, and has a large circuit scale.

[Problems to be solved by the invention]

The MUSE decoder in the conventional example described above transmits the transmitted MUSE
A circuit configuration for faithfully reproducing the signal, that is, a configuration for performing complicated signal processing such as switching between the luminance and color difference signals between moving image processing and still image processing depending on the presence or absence of image movement. Therefore, there is a problem that the scale of the processing circuit becomes very large. The problem is described in more detail as follows.

(1) In the conventional example shown in FIG. 2, if the circuit configuration described above is adopted, still image signal processing, moving image signal processing, luminance signal processing, color difference signal processing, image motion signal processing, motion correction, noise removal, etc. However, there is a problem that a large-scale signal processing circuit is required.

(2) In the conventional circuit configuration, two processing circuits are required for a still image and a moving image. For this reason, there is a problem that a large-scale circuit configuration is required which requires a large-capacity memory such as a frame memory for motion detection processing, a field memory for field interpolation processing, and a frame memory for frame interpolation processing. Was.

(3) In the conventional example of FIG. 2, the moving picture processing circuit included in the color difference signal processing section 233 passes through the still picture color difference signal processing section 232 and is mixed by the MIX circuit 228, and then the still picture / moving picture is processed. At the same time, since the configuration is such that line sequential decoding is performed, a processing configuration in which TCI decoding is performed, intra-field chroma interpolation is performed, and then line sequential decoding is performed. However, in such a configuration, there is a problem that the signal subjected to the chroma interpolation processing is supplied to the line memory for the line sequential decoder, so that the capacity of the line memory is increased.

(4) In the conventional example of FIG. 2, since the still image and the moving image are simultaneously decoded line-sequentially after being mixed by the MIX circuit 228 as described above, the frequency conversion units 234 and 235 are line-sequentially The configuration is such that it is arranged at the rear of the decoding unit 229. However, when such a configuration is adopted, two frequency converters are required for RY and BY, and the circuit scale is increased. There was a problem.

(5) The conventional example shown in FIG. 2 has two systems of moving image / still image processing for a luminance signal and a color difference signal. However, when such a configuration is adopted, two MIX circuits for mixing the signals subjected to the still image / moving image processing are required, which increases the circuit scale. There was a problem.

(6) In the conventional example shown in FIG.
Are performed by digital signal processing. When considering the sharing of the RGB matrix circuit with the current NTSC receiver, most of the current NTSC receivers are analog.
A built-in RGB matrix circuit, and processing this with digital signals increases the circuit scale. Further, although the characteristics of each of R, G, and B of the CRT slightly vary depending on the size, there is a problem that adjustment for such a change is difficult to be performed by a digital circuit.

An object of the present invention is to solve the above problems, and to solve the problem at 16: 9 (or
It is an object of the present invention to provide a simple high-definition television receiver having a small circuit size and a display device having an aspect ratio of 5: 3).

[Means for solving the problem]

The above problem is that in a device capable of receiving a high-definition television signal in which a still image and a moving image of a video signal are band-compressed by different methods by multiplex sub-sampling, a received analog high-definition television signal is A / D conversion means for converting the output signal of the A / D conversion means, a synchronization signal reproduction means for extracting and reproducing a clock and a synchronization signal for signal processing from the output signal of the A / D conversion means, and performing signal processing limited to the field. An in-field signal processing unit for reproducing a video signal; a D / A conversion unit for converting a digital signal output of the in-field signal processing unit into an analog signal; and a wide-screen display unit. Can be realized by performing in-field signal processing irrespective of a still image or a moving image.

[Action]

The in-field signal processing circuit reproduces a video signal by processing all of the signal processed by the still image and the signal processed by the moving image on the encoder side. When a still image transmitted by multiple sub-samples is reproduced by moving image processing, some aliasing interference occurs at a position having high horizontal and vertical frequency components, but this is the same as that of a television receiver that receives a normal standard television system. Deterioration of the image quality of the screen of the simple MUSE decoder of the present invention due to viewing at an approximate viewing distance is a sufficiently tolerable disturbance. Furthermore, since all of the video processing is performed, signal processing parts such as a still image signal processing, a motion detection processing, a motion correction, a noise removal, a frequency conversion unit, and a MIX circuit, which are conventionally required, can be eliminated. A large-capacity memory such as a field memory for the interpolation processing and a frame memory for the inter-frame interpolation processing is not required, and the circuit scale can be significantly reduced.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 101 denotes an analog signal input terminal for demodulating a received MUSE signal and returning it to a baseband in a band of about 8 MHz; 102, an A / D converter for converting the analog signal into a digital signal; An emphasis processing unit 104 is an interpolation filter in the field. 105 is a TCI decoder, 106 is a line sequential decoder, 107 is a chroma interpolation processing unit, 108 is a synchronization signal from a digitized MUSE signal output from the A / D converter 102,
A synchronous processing unit that extracts a control signal and also generates a system clock, 109, 110, and 111 are D / A converters,
Reference numerals 112, 113, and 114 denote LPF sections, reference numeral 115 denotes an RGB matrix circuit, and reference numeral 116 denotes an interlace scanning display having an aspect ratio of 16: 9 and 1125 scanning lines. Reference numeral 120 denotes an in-field video signal processing circuit that receives an output signal from the A / D converter 102 and reproduces a video signal.

Next, the operation of FIG. 1 will be described. The MUSE signal input from the input terminal 101 is converted into a digital signal by the A / D converter 102. The converted MUSE signal is supplied to the de-emphasis processing unit 103 and the synchronization processing unit 108. The synchronization processing unit 108 extracts a synchronization signal and a control signal from the MUSE signal, generates a system clock, and operates the entire system. The de-emphasis processing unit 103 performs inverse nonlinearity on the MUSE signal transmitted by the FM modulation to filter the de-emphasis characteristics to reduce triangular noise in the transmission path, and furthermore, a noise component that is conspicuous in a place where the amplitude of the video signal is small. To reduce. The processed MUSE signal is input to the field interpolation filter 104, and the still image / moving image signal and the luminance / color difference signal are subjected to the field interpolation processing to be reproduced as a signal having a band of 16 MHz or less. . Here, the luminance signal has a blanking period inserted and D /
It is supplied to the A converter 109. At this time, in the field interpolation filter 104, the color difference signals are still band-compressed in the horizontal / vertical directions and the time axis direction. Therefore, the color difference signal is input to the TCI decoder and expanded on the time axis. The color difference signal in which the luminance signal and the time axis are aligned by the TCI decoder 105 (time axis expansion circuit) is sent to the chroma interpolation processing unit 107.
Here, the color difference signal is subjected to pixel interpolation in the horizontal direction and sent to the line-sequential decoder 106. In the line-sequential decoder 106, line interpolation is further performed on the color difference signal in the vertical direction, and RY and BY signals are generated for each line. The color difference (R-Y, B-Y) signal subjected to the above series of processing is finally inserted with a blanking period, and the RGB matrix circuit 115 outputs the red, green, and blue RG signals.
Converted to B signal. Thereafter, the video signals supplied to the D / A converters 110 and 111 and converted into analog signals by the D / A converters 109, 110 and 111 are input to the 16: 9 display 116 after being band-limited by the LPFs 112, 113 and 114, respectively, and input as images. Will be played.

In the simplified MUSE decoder shown in FIG. 1, the interpolation processing between fields, which is normally performed in the still image processing part, is not performed, but the moving image processing is performed for both the still image part and the moving image part by the interpolation filter 104 in the field. This processing method eliminates the need for complicated signal processing circuits such as a frame memory, an interpolation filter between frames, a motion detection circuit, a frequency conversion circuit, and a MIX circuit, which are necessary for the conventional MUSE decoder, as shown in FIG. Very simple signal processing like this is enough.

Furthermore, there is no need for conversion of the synchronization frequency, such as the MUSE / NTSC converter that converts a MUSE signal to an NTSC standard television signal, and it does not thin out the number of scanning lines or cut off both ends of the screen. The image quality has been minimized and the image quality has been greatly improved compared to the MUSE / NTSC converter. Furthermore, even when the image of the simple MUSE decoder of the present invention and the image obtained by doubling the normal NTSC video are displayed on the display 116 having the aspect ratio of 16: 9 in common, the simple MUSE decoder is more suitable. High-quality reproduction is possible.

Next, the interpolation filter 104 in the field will be described in detail.

FIG. 3 is a diagram showing an example of the field interpolation filter 104. In FIG. 3, reference numeral 301 denotes a MUSE signal input terminal input from the de-emphasis processing unit 103, and 302, 303, and 3
04 is a line memory, 305, 306, 307, and 310 are select switches, 308, 309, 317, and 319 are adders, 311, 312, and 313 are latch circuits, 314, 315, and 316 are transversal filters (hereinafter, referred to as TRFs), and 323 is a 16-MHz signal output from the synchronization processing unit in FIG. The sub-sample clock is a clock (hereinafter referred to as SS) input terminal and an input terminal 324 having a phase according to the transmission control data in the luminance signal period and the color difference signal period.
Is an inverter, 325 is an input terminal for inputting a V / C signal (signal in which the C (color difference) signal period is LOW and the Y (luminance) signal period is High) output from the synchronization processing unit in FIG.
Reference numeral 322 denotes an output signal terminal of the field interpolation filter 104.

The circuit configuration shown in FIG. 3 can be realized as, for example, a single integrated circuit. However, for simplicity, it can be easily realized, for example, by integrating only the remaining circuits using an existing line memory. . Below, our line memory HM63021
The operation of FIG. Input terminal 30
The MUSE signal input from 1 is delayed by the line memories 302, 303, 304. More specifically, line memory
The lines 302, 303, and 304 operate in the 1H / 2H delay line mode. The line memories 302 and 303 simultaneously delay the luminance signal and the color difference signal, and the line memory 304 delays only the color difference signal. The line memory 302 uses a 1H, 2H delayed MUSE signal (a signal before being separated into a luminance signal and a color difference signal), and the line memory 303 uses the 2H delayed data of the line memory 302 to use a 3H, 4H data.
The H-delayed MUSE signal (the signal before being separated into the luminance signal and the color difference signal)
Using the 4H delay data, only the color difference signal period of the MUSE signal input to the line memory 304 is extracted and stored.
A color difference signal delayed by H and 8H is obtained. That is, the line memory
In 304, the amount of transmitted information in the time axis direction is 1 compared to the luminance signal.
Utilizing the properties of the color difference signal as small as / 4,
Performs 2H / 4H delay. Select switch 305, 306, 3
07 and 310 are switches for selecting the a side during the luminance signal period and the b side during the color difference signal period using the YC signal output from the input terminal 325. FIG. 5 shows the arrival signal at this time and the state of processing in the selected state of the select switch. In FIG. 5, the color difference signal is
It is transmitted 4H ahead, and it is supposed that the currently arriving signal is the position of the luminance signal Y5. In FIG. 5, the output of the select switch 310, that is, the signal of the portion A is the select signal H.
At the time of igh input (at the time of luminance signal processing), it becomes a signal (Y3) delayed by 2H from the current arriving signal. Also, when the select signal is input low (during color difference signal processing), it becomes a signal (R5-Y5) delayed by 4H from the current incoming signal. Input terminal during the luminance signal period in part B
The signal (Y3) delayed by 1H with respect to the input signal from 301 and the average ((1H + 3H) / 2) of the signal delayed by 3H is converted into a signal (H) delayed by 2H with respect to the input signal from the input terminal 301 during the color difference signal period ( An average ((2H + 6H) / 2) signal of (R7−Y7) and the signal (R3-B3) delayed by 6H is obtained. Part C includes an input signal Y5 from the input terminal 301 during the luminance signal period and a signal Y1 delayed by 4H.
Signal (R0-H9) and the signal (R1-Y1) delayed by 8H from the input signal (R9-Y9) from the input terminal 301 during the color difference signal period. Get. This signal processing will be further described with reference to FIG. The incoming signal is defined as the position of the luminance signal Y5.
With the signal delayed by 2H as the luminance signal processing center and the signal delayed by 4H as the color difference signal processing center, it can be seen that the RY signal is transmitted to the odd lines and the BY signal is transmitted to the even lines. That is, to match the processing center of the luminance signal and the color difference signal,
The color difference signal has to be processed every other line with respect to the luminance signal.

As can be seen from FIG. 5, the signal is the processing center of the luminance signal and the color difference signal in both the B section and the C section. This means that the average of the upper line and the lower line is obtained for the portion A. As described above, in the present embodiment, the processing center of the luminance signal and the processing center of the chrominance signal are shifted by 2H. However, this takes into account the vertical delay caused by the TCI decoder 105 and the line-sequential decoder to be described later, and the processing centers of the D / A converters 109.110 and 111 will eventually match, causing a problem. is not.

From the input terminal 323, an SS having a phase according to the control signal is input in each of the luminance signal period and the color difference signal period. The latch circuits 311 and 313 have the same phase SS, and the latch circuit 312 has the inverter 324 and the latch circuits 311 and 313.
As a result, the SS having the opposite phase is input as a clock. As a result, the signals of the A section, the B section, and the C section having the same phase are transmitted to the TRF sections 314 and 31.
Sent to 5,316. The output signal of TRF 315 and the output signal of TRF 316 are added and averaged by adder 317. Further, the addition average output and the output signal of the TRF 314 are added and averaged by the adder 319. The output of the adder 319 is input to the output terminal 322. FIG. 4 shows an example of a characteristic of the output signal from the output terminal 322 when viewed as a two-dimensional filter characteristic.

FIG. 4 shows a two-dimensional fill characteristic of the field interpolation filter of FIG. This filter characteristic is a filter characteristic for simultaneously processing both a still image and a moving image during transmission of a MUSE signal. The characteristics of the filter characteristics include
In consideration of the transmission band of the moving image of the MUSE signal and the three-dimensional frequency characteristics of the still image, this is a characteristic that eliminates aliasing components that interfere with the image and ensures the necessary resolution.

Thus, a field interpolation filter can be realized with a relatively simple configuration. In the above embodiment, the TRF
Are used to realize the filter characteristics, but the present invention is not limited to this, and can be further simplified. In FIG. 12, the same reference numerals in FIG. 12 denote the same operations as those in another embodiment. 1200, 1201, 1202, 1203, 1204 are line memories, 120
5, 1206, 1207 are adders, 1207 is a select switch, 1209
Is a TRF, and 1210 is an output terminal of an output signal from the TRF. Although the circuit operation will be obvious from FIG. 3, it is a feature of this embodiment that the circuit scale can be reduced to a smaller value, such as the line memories 1200, 1201, 1202, 1203, 1204 and TRF1209.

FIG. 8 is a diagram showing another embodiment of the present invention. In FIG. 8, components denoted by the same reference numerals as those in FIG. 1 perform the same operations.

Next, the operation of FIG. 8 will be described. The operation of FIG.
Although it is almost equivalent to FIG. 1, the processing order of the chroma interpolation and the line sequential decoder is different from that of FIG. The chrominance signal whose time axis is aligned with the luminance signal by the TCI decoder 105 is sent to the line-sequential decoder 106. In the line sequential decoder 106,
Interpolation processing in the vertical direction is performed on the color difference signal, and RY and BY signals are generated for each line. Next, the color difference signal is
It is sent to the chroma interpolation processing unit 107. Where the color difference signal is
The color difference (RY, BY) signal subjected to the horizontal interpolation process and subjected to the series of processes is finally inserted with a blanking period, and subjected to red, green, and blue RGB by the RGB matrix circuit 115.
Converted to a signal. Thereafter, the MUSE signals supplied to the D / A converters 110 and 111 and converted into analog signals by the D / A converters 109, 110 and 111 are input to and displayed on the 16: 9 display 116 after being band-limited by the LPFs 112, 113 and 114, respectively. The processing units of the chroma interpolation and the line sequential decoder will be described in detail with reference to FIG.

FIG. 7 shows a detailed configuration of the line sequential decoder section 106 and the chroma interpolation circuit 107 in FIG. Seventh
In the figure, 901 is an input terminal to the line sequential decoder 106,
902,903 is line memory, 906,907,909,910,911,913 is 16
D flip-flops 908 and 912 clocked by MHz are adders, and those having the same operations as those in FIG. 6 are denoted by the same reference numerals.

Next, the operation of FIG. 7 will be described. The input terminal 901 receives an output signal from the TCI decoder 105 in another embodiment of the present embodiment shown in FIG. 8, that is, a signal having a band of 8 MHz. The line memories 902 and 903 generate 1H delay and 2H delay signals with respect to the input signal from the TCI decoder 607, and
The delay signal is supplied to the adder 808, and the 1H delay signal is supplied to the select switches 809 and 810. At this time, the line memory 90
Since 2,903 has a sampling frequency of 16 MHz, it requires only half the capacity of the line memories 806 and 807 in FIG. The operations of the select switches 809 and 810 are the same as those in FIG. By the above operation, select switches 809 and 8
The RY signal and the BY signal obtained at 10 (E section and F section) are input to latch circuits 906 and 910, respectively. Latch circuits 906, 907, 909, adder 908 and latch circuits 910, 911, 913
And the adder 912 correspond to the latch circuits 802, 803, 805 in FIG.
Is equivalent to the operation of the adder 804, and the description is omitted. By the above operation, the RY signal and the BY signal interpolated with the chroma are obtained at the output terminals 811 and 812, respectively. By performing the chroma interpolation after the line-sequential decoding as described above, in the present embodiment, the memory capacity of the line-sequential decoder unit 106 can be reduced by half compared to FIG.

FIG. 9 is a diagram showing another embodiment of the present invention. In FIG. 9, components denoted by the same reference numerals as those in FIG. 1 perform the same operations, and reference numeral 130 denotes an RGB matrix circuit constituted by an analog circuit. The operation of FIG.
Although it is almost equivalent to the figure, the position of the RGB matrix is different from that of FIG. 1, and 131 is an in-field video signal processing circuit that receives an output signal from the A / D converter 102 and reproduces a video signal. 1 does not include an RGB matrix circuit. The color difference signal whose time axis is aligned with the luminance signal by the TCI decoder 105 is sent to the chroma interpolation processing unit 107. Here, the color difference signal is subjected to horizontal processing, and then the color difference signal is sent to the line-sequential decoder 106. In the line-sequential decoder 106, the color difference signal is processed in the vertical direction, and RY and BY signals are generated for each line. The color difference (RY, BY) signal that has been subjected to the above series of processing is inserted with a blanking period at the end, and thereafter the D / A converters 110, 1
The luminance and color difference signals supplied to the D / A converters 109, 110, and 111 and converted into analog signals are supplied to the LPFs 112 and 1, respectively.
After limiting the band at 13,114, the RGB matrix circuit 130
The signals are converted into green / blue RGB signals, input to a 16: 9 display 116, and displayed. The advantage of supplying the RGB matrix circuit 130 after D / A conversion of the color difference signal is NTSC
When considering sharing with a receiver of the NTSC system, most of the receivers of the NTSC system use an analog RGB matrix circuit. The circuit size of the RGB matrix circuit can be reduced as compared with FIG. The change in the RGB characteristics due to the change in the display size is the same as the digital RGB in FIG.
Compared to the matrix circuit, the analog RG
B matrix circuits are easier. The position at which the blanking level is added in the above is not limited to the above, and may be added before displaying on the display, for example, after chroma interior processing, after TCI decoding, or the like.

FIG. 10 is a diagram showing another embodiment of the present invention. No.
10, the same reference numerals as those in FIG. 1 denote the same operations, and the operation in FIG. 10 is almost equivalent to the operation in FIGS. Compared with FIG. 8 and FIG. 9, the processing order of the color difference signal is different, and the line sequential decoding, chroma interpolation processing, D / A conversion, LP
The order of the F and RGB matrix circuits is as follows. By performing such a signal processing, the present embodiment provides, as shown in FIG.
As compared with FIG. 9, the memory capacity of the line-sequential decoder unit 106 can be reduced.

FIG. 11 shows another embodiment of the present invention, in which AM transmission is used.
FIG. 3 is a diagram illustrating a configuration when a MUSE signal is received. In FIG. 11, components denoted by the same reference numerals as those in FIG. 1 perform the same operations, and the operations in FIG. 10 have a reduced number of de-emphasis circuits as compared with FIG. The de-emphasis circuit is an effective means for removing noise components in the transmission path when performing FM transmission, but can be omitted because it does not exhibit its effect during AM transmission.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to this invention, there exists an effect that a simple high-definition television receiver with a small circuit scale provided with the display device which has an aspect ratio of 16: 9 (or 5: 3) can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIGS. 3 and 12 are field interpolation processing blocks in one embodiment of the present invention. FIG. 4 is a diagram showing the filter characteristics of FIG. 3, FIG. 5 is a diagram for explaining the operation of FIG. 3,
FIG. 6 is a block diagram showing a configuration of a conventional chroma interpolation circuit and a line-sequential decoder unit. FIG. 7 is a block diagram showing a configuration of a line-sequential decoder unit and a chroma interpolation circuit of the present invention. FIG. 8, FIG. 9, FIG. 10, and FIG. 11 are views of another embodiment of the present invention. 101 MUSE signal input terminal, 102 A / D converter, 103
De-emphasis processing unit, 104: field interpolation filter, 105: TCI decoder, 106: line-sequential decoder, 107: chroma interpolation circuit, 108: synchronization processing unit, 109
~ 111 ... D / A converter, 112 ~ 114 ... LPF, 115 ... RGB
Matrix section, 116 ... Display with aspect ratio of 16: 9, 120 ... Video signal processing circuit in field.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazumio Nakagawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliances Research Laboratory, Hitachi, Ltd. (72) Kenji Katsumata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Home Appliances Research Laboratory Co., Ltd. (72) Inventor Mitsuo Konno 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Inside Hitachi, Ltd. Home Appliances Research Laboratories (72) Kenmasa Miyake 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Video Engineering Co., Ltd. (72) Inventor Yuichi Ninomiya 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation, Research Institute of Broadcasting Technology (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 7/015

Claims (4)

(57) [Claims] 1. A television receiver capable of receiving a high-definition television signal in which a still image and a moving image of a video signal are band-compressed by different methods by a multiplex sub-sampling process. A / D conversion means for converting into a digital signal, synchronization signal reproduction means for extracting and reproducing a clock signal and a synchronization signal for signal processing from the output signal of the A / D conversion means, and supply from the synchronization signal reproduction means. In-field signal processing means for performing signal processing in which the digital signal from the A / D conversion means is limited to a field using the clock signal to be reproduced, and reproducing a digital video signal corresponding to a wide aspect screen; and D / A conversion means for converting the digital video signal output of the internal signal processing means into an analog video signal; A wide-aspect display means for inputting a synchronization signal generated and an analog video signal from the D / A conversion means, and the transmitted video signal is processed in a wide-aspect field by signal processing in a field regardless of a still image or a moving image. A television receiver for reproducing an image. 2. The in-field signal processing includes: interpolation filter processing means for extracting luminance and chrominance signals; TCI processing means for extending the color difference signals extracted by the interpolation filter processing means on a time axis; A line-sequential decoder processing means for performing vertical interpolation processing from an output of the processing means, and a chroma interpolation processing means for processing the output of the line-sequential decoder processing in a horizontal direction. The television receiver according to 1. 3. A clock signal supplied from said synchronizing signal reproducing means to said in-field video signal processing means has a frequency not more than twice as high as a transmission sample clock of a high-definition television signal. The television receiver according to claim 1. 4. An in-field signal processing means comprising an analog RGB matrix circuit for inputting an analog video signal from the D / A conversion means, and supplying an output of the analog RGB matrix circuit to the display means. 2. The reproduced digital video signal supplied to the D / A conversion means is a luminance and color difference signal.
The television receiver as described.