JPH02285897A - Television system converter - Google Patents

Abstract

PURPOSE:To enable almost the entire picture of high-definition television to be displayed without applying modification on an NTSC monitor by converting an aspect ratio correctly by converting the number of scanning lines from 525 to 350, and performing time compression in a perpendicular direction. CONSTITUTION:A MUSE signal applied on an input terminal 1 is converted to a luminance signal and two color difference signals RY and B-Y by a luminance signal processing circuit 7 and a color difference signal processing circuit 8. The luminance signal and the color difference signals are signals having 525 scanning lines per frame and with field frequencies of 60Hz and with interlaces of 2:1. A blanking insertion circuit 21, when a signal time- compressed in the perpendicular direction of a velocity conversion memory circuit 20 being inputted, attaches period blanking with 175 scanning lines on a hatched part shown in figure (b), and outputs the luminance signal and the two color difference signals with the 525 scanning lines per frame and with the field frequencies of 60Hz (350 effective scanning lines).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television format conversion device that converts the aspect ratio of a television signal, and particularly to a digital filter in a video signal processing circuit thereof.

[Conventional technology]

FIG. 2 is a diagram showing a television receiver according to the prior art by the present applicant. In the figure, l is a first input terminal, 2 is an A/D converter, 3 is a de-emphasis circuit, and 4
1 is a first PLL circuit, 5 is a second PLL circuit, 6 is a scanning line conversion circuit, 7 is a luminance signal processing circuit, 8 is a color difference signal processing circuit, 9 is a D/A converter, 10 is a switch circuit, 11 is an inverse matrix circuit, 12 is a CRT, 13 is a second input terminal, 14 is a third input terminal, 15 is an NTSC decoder, 16 is a timing generation circuit, 17 is a vertical deflection circuit, 1
8 is a horizontal deflection circuit.

Next, the operation will be explained. A high-definition signal band-compressed by the MUSE method is applied to the input terminal 1. This high-definition signal has 1125 scanning lines, a field frequency of 60 Hz, and a 2:1 interlace signal. In the MUSE method, the above high-definition signal is transmitted in a band of 8 MH.
z and transmitted over one channel using a broadcasting satellite. This compression is performed by offset subsampling, using inter-field and inter-frame offsets for still image portions and inter-line offsets for moving image portions. Further, the two color difference signals (R-Y, B-Y) are time-compression multiplexed during the blanking period of the luminance signal.

The high-definition signal according to the MUSE method (hereinafter referred to as the MUSE signal) applied to the input terminal 1 is converted into a digital signal by the A/D converter 2, and applied to the de-emphasis circuit 3 and the first PLL circuit 4, respectively. . The first PLL circuit 4 reproduces a correct sampling clock based on the phase information in the MUsE signal. This correct sampling clock is supplied to the A/D converter 2, and the MUSE is sampled with the correct phase.
A signal will be applied to the de-emphasis circuit 3. The de-emphasis circuit 3 corrects the frequency characteristics of the MUSE signal, and this corrected signal is applied to the scanning line conversion circuit 6.

This scanning line conversion circuit 6 uses, for example, a digital memory, sets the write clock speed to the speed obtained from the time axis of the MUSE signal, and sets the read clock speed to NTSC.
By using the speed obtained from the time axis of the signal, the MU
It is configured to discard 75 scanning lines from the 1125 scanning lines per frame of the SE signal and convert them into 1050 scanning lines per frame. This read clock is output from the second PLL circuit 5.

Therefore, from this scanning line conversion circuit 6, 1
A signal having 0.050 scanning lines, 2:1 interlacing, and a field frequency of 60 Hz can be obtained.

The output signal of the scanning line conversion circuit 6 is transmitted to the luminance signal processing circuit 7.
The signal is applied to each of the five color difference signal processing circuits 8. The luminance signal processing circuit 7 performs field interpolation corresponding to line offset sampling to return the band to its original value, and then performs interlace conversion to obtain 525 pixels per frame.
A signal with a 2:1 interlace and a field frequency of 60 Hz is obtained. On the other hand, the color difference signal processing circuit 8 expands the time axis (TCI decoder) of the two time compression multiplexed color difference signals (RY, B-Y), and performs intra-field interpolation processing based on the band. return.

After this, interlace conversion is performed and 52 pixels per frame.
Convert to 5 interlaced signals.

The luminance signal which is the output signal of the luminance signal processing circuit 7 and the color difference signal processing circuit 8 and the two color difference signals (R-Y, B-Y
) are respectively applied to the D/A converter 9 and converted into analog signals.

On the other hand, the NTSC signal applied to the third input terminal 14 is guided to the NTSC decoder 15. NTSC decoder 1
Reference numeral 5 includes, for example, means for separating a luminance signal and a color signal, and means for demodulating a color signal, and outputs a luminance signal and two color difference signals from the applied NTSC signal. D above
The output signal of the /A converter 9 and the output of the NTSC decoder 15 are applied to a switch circuit 10. switch circuit 1
0 is configured to output one of two signals applied to this switch circuit 10 in response to a signal applied to a second input terminal 13, which will be described later. The output signal of the switch circuit 10 is input to an inverse matrix circuit 11, and RoG and B primary color signals are generated. The inverse matrix circuit 11 is similar to that used in current television receivers. The output signals R1G and B of the inverse matrix circuit 11 are applied to the CRT12 and displayed.

The deflection timing of this CRT 12 is generated by a timing generation circuit 16, a vertical deflection circuit 17, a horizontal deflection circuit 1
8 is driven by a signal from the timing generation circuit 16. The vertical deflection circuit 17 is configured so that its deflection width can be controlled by a signal applied to a second input terminal 13, which will be described later. A control signal for selecting whether to display the MUSE signal or the NTSC signal on the television screen is applied to the second input terminal 13.

As already mentioned, this signal is also applied to the switch circuit 10. The switch circuit 10 passes the output signal of the D/A converter 9 or the output signal of the NTSC decoder 15 according to the control signal of the second input terminal 13. Further, when the switch circuit 10 selects the output signal of the NTSC decoder 15, the vertical deflection circuit 17 is driven with a normal NTSC vertical deflection width.

Furthermore, the output signal of the D/A converter 9 is as shown in FIG. 3(a).
This is a vertically elongated video with an aspect ratio of 4:3, as shown in FIG. 3 (b), which is obtained by compressing the time in the horizontal direction from a video with an aspect ratio of 16:9. Therefore, the switch circuit 10 is connected to the D/A
When the output of the converter 9 is selected, the vertical deflection circuit 17 converts a vertically elongated image as shown in Figure 3 (B) into an image with an aspect ratio of 16:9 as shown in Figure 3 (C). Reduce the vertical deflection width to .

[Problem to be solved by the invention]

Conventional television format converters are configured as described above, so if you want to display almost full-screen high-definition video on an NTSC monitor, you must modify the vertical deflection circuit of the NTSC monitor so that it can be controlled externally. figure,
NTSC monitors already on the market have the drawback of not being able to display almost full-screen high-definition images.

This invention was made in order to solve the problems of the conventional ones as described above, and provides a television format conversion device that can display almost full-screen high-definition images on an NTSC monitor without modifying the vertical deflection circuit of the NTSC monitor. The purpose is to obtain.

[Means to solve the problem]

The television system conversion device according to the present invention has a 1050
A digital filter is provided to convert the number of 525 interlaced signals converted from the scanning lines of a book from 525 to 350.

[Effect]

The television system conversion device of this invention converts the scanning lines from 525 to 350 and compresses the time in the vertical direction so that the aspect ratio is converted correctly, so there is no need to modify the NTSC monitor. , it is possible to display almost the entire screen of high-definition video.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a television format conversion device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. Luminance signal (Y signal) and color difference signal (R-Y, B
20 is a speed conversion memory circuit, and 21 is a blanking insertion circuit.

Next, the operation will be explained. M applied to input terminal 1
The USE signal is converted into a luminance signal and two color difference signals RY and BY by the luminance signal processing circuit 7 and color difference signal processing circuit 8 in the same manner as in the conventional circuit. The luminance signal and color difference signal are 525 signals per frame, a field frequency of 60 Hz, and a 2:1 interlace signal.

The luminance signal and two color difference signals output from the luminance signal processing circuit 7 and color difference signal processing circuit 8 are input to a scanning line conversion filter circuit 19. The scanning line conversion filter is composed of a 4th-order digital filter in the vertical direction, and the tap coefficients are 1/16.1/4.3/8.1/4.1/16.
The transfer characteristic H(Z) is H(Z)-(1+4 Z-'-+6 Z-''-+42-
"+Z-"")/16z-': is expressed as a horizontal scanning line delay.

Hereinafter, this scanning line conversion filter circuit 19 will be explained using FIG.
Explain the operation. The O marks A1 to A7 indicate input scanning lines, and the marks a1 to a4 indicate output scanning lines.
At this time, the scanning lines are converted from 3 to 2, and the phase of al is between A1 and A2, a2 is in the same phase as A3, a3 is between A4 and A5, and a4 is the same as a6. It is a phase.

The signal output from the scanning line conversion filter circuit 19 has 350 scanning lines per frame and has a field frequency of 60 Hz.

350 scanning lines per frame as shown in FIG. 5(a), a luminance signal with a field frequency of 60 Hz, and two color difference signals are inputted to the speed conversion memory circuit 20 from the scanning line conversion filter circuit. The speed conversion memory circuit 20 is composed of, for example, a digital memory, and outputs a vertically time-compressed signal as shown in FIG. 5, etc. by reading at a faster speed than the writing speed.

The blanking insertion circuit 21 is the speed conversion memory circuit 2.
When a time-compressed signal in the vertical direction of 0 is input, period blanking of 175 scanning lines is added to the shaded area shown in Figure 5, resulting in a field of 525 scanning lines per frame. It outputs a luminance signal with a frequency of 60 Hz (350 effective scanning lines) and two color difference signals. The signal thus obtained is a vertically corrected image as shown in FIG. 3(C).

The luminance signal and two color difference signals obtained through the above processing are converted into analog signals by the D/A converter 9 and input to the switch 10.

On the other hand, the NTSC signal input to the input terminal 14 is
The C decoder 15 decodes the signal into a luminance signal and two color difference signals, which are input to the switch 0. The switch 10 selects either the output of the D/A converter 9 or the output of the NTSC decoder 15 according to the MUSE/NTSC selection signal input from the input terminal 13 and outputs the selected signal to the inverse matrix circuit 11 . The luminance signal and two color difference signals input to the inverse matrix circuit 11 are converted into R, G, and B signals and sent to the CRT 12.
will be displayed.

In the above embodiment, the case where the NTSC is built into the television receiver has been explained, but the NTSC is installed after the D/A converter 9.
By providing a C encoder and modulating the color signal, NT
It can also be used as an adapter-type system conversion device that outputs SC composite signals and Y/C separate signals.
It may also be built in, and the same effects as in the above embodiment can be achieved.

Furthermore, in the above embodiment, a case was explained in which 1050 scanning lines were converted into 525 interlaced signals.
Converting to 525 non-interlaced signals can also be realized using the same concept as the present invention.

Further, in the above embodiment, the scanning line conversion filter is configured with a 4th order digital filter, but it may also be configured with a 4th order and a 5th order digital filter that are alternately switched for each field. It has the same effect as the example.

〔Effect of the invention〕

As described above, the television system converter according to the present invention is configured to convert the number of scanning lines using a digital filter, so that almost all high-definition images can be converted without modifying the vertical deflection circuit of the NTSC monitor. This has the effect of allowing you to monitor the screen with the correct aspect ratio.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a television system converter according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional television system converter, and FIG. 3 is a diagram explaining the operation of FIG. 2. , FIG. 4, and FIG. 5 are diagrams explaining the operation of FIG. 1. In the figure, 1, 13 and 14 are input terminals, 2 is an A/D converter, 3 is a de-emphasis circuit, 4.5 is a PLL circuit, 6 is a scanning line conversion circuit, 7 is a luminance signal processing circuit, and 8 is a color difference circuit. A signal processing circuit, 9 a D/A converter, 10 a switch,
11 is an inverse matrix circuit, 12 is C115 is NTSC
16 is a timing generation circuit, 17 is a vertical deflection circuit, 18 is a horizontal deflection circuit, 19 is a scanning line conversion filter circuit, 20 is a speed conversion memory circuit, and 21 is a blanking insertion circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a television system converter that converts a MUSE signal to an NTSC signal, a means for converting 1125 scanning lines of the MUSE signal into 1050 scanning lines, and a means for converting the scanning line-converted luminance signal into NTSC signals within the field. means for performing interlace processing; means for converting the luminance signal into a 525-line interlaced signal;
and a means for outputting a B-Y color difference signal, a means for performing intra-field interpolation processing on the two color difference signals, a means for converting the color difference signal into a 525 line interlaced signal, and 525 line scanning per frame. 1. A television format conversion device comprising: a digital filter that converts three scanning lines into two scanning lines using lines and outputs 350 scanning lines per frame.