JPH0670256A - Master/slave screen signal synthesizing circuit for high-vision receiver - Google Patents

Abstract

PURPOSE:To display a master screen of the NTSC signal and a slave screen of the HD signal after the synthesization of both screens and furthermore to attain the function of an HDTV/NTSC converter with addition of a simple circuit. CONSTITUTION:When a switching circuit 64 is set at the side of a 1st D/A converter 54, the NTSC signal is converted into a digital signal and then into an analog signal after the time base conversion. Meanwhile the HD signal is converted into a digital signal and then into an analog signal after undergoing the processing for a prescribed slave screen size and the time base conversion. Such NTSC and HD signals are synthesized by a synthesizing circuit 66. Then a slave screen of the HD signal is displayed on a part of a master screen of the NTSC signal by a high-vision monitor 38. When the circuit 64 is switched to the side of a synchronizing separator 62, the circuit 66 synthesizes the synchronizing signal of the NTSC signal to the HD signal processed for a prescribed size. Then a high-vision broadcast screen is displayed by a general-purpose NTSC receiver.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition monitor, which is a display unit of a high-definition receiver, and has an NTSC (Nat
Ional Television System C
The present invention relates to a circuit for synthesizing (superimposing) and displaying a child screen by an HD signal on a part of a parent screen by an ommittee signal.

[0002]

2. Description of the Related Art Conventionally, an NTSC display which is a display portion of an NTSC television receiver (hereinafter, simply referred to as an NTSC receiver) is a circuit for combining and displaying a child screen on a part of a parent screen. That is, the picture-in-picture (PIP) circuit was configured as shown in FIG. That is, the first NTSC signal for the child screen is A / D
The (analog / digital) conversion circuit 10 converts it into a digital signal, the small screen processing circuit 12 processes the signal for a predetermined small screen size, and then the D / A (digital / analog) conversion circuit 14 converts it into an analog signal. Synthesis circuit 1
6 to one input side. The second NTSC signal for the parent screen is led to the other input side of the combining circuit 16.

Then, the parent-child screen signal synthesized by switching the predetermined timing in the synthesis circuit 16 is sent to the NTSC.
By outputting to a display (not shown), the child screen is combined with a part of the parent screen and displayed. However, there is no high-definition monitor of a high-definition receiver which synthesizes and displays a sub-screen by an HD signal on a part of a main screen by an NTSC signal. Here, the HD signal is, for example, HDTV (High
Definition Television) R, G, B video signals, and NTSC signals are, for example, R, G, and NT of the NTSC system TV which is a current television signal.
B video signal.

[0004]

However, a conventional NTSC display has a circuit configuration for combining and displaying parent and child screens. In a high-definition monitor, a part of the parent screen based on NTSC signals is combined with a child screen based on HD signals. If it is used as it is for the configuration of the circuit to be displayed, there is a problem that distortion such as lateral expansion and lateral contraction occurs in the image due to differences in synchronization and aspect ratio. Further, when an image based on an HD signal is displayed on a general-purpose NTSC television receiver or VTR, a new HDTV-NTSC converter is required.

The present invention has been made in view of the above-mentioned problems, and it is possible to display a composite picture of an HD signal on a part of a main picture of an NTSC signal without distortion of the screen display such as lateral expansion or lateral contraction. HD by adding a simple circuit
An object of the present invention is to provide a parent-child screen signal synthesizing circuit for a high-definition receiver that can achieve the function of a TV-NTSC converter.

[0006]

A parent-child screen signal combining circuit of a high-definition receiver according to the present invention comprises a first A / D converting circuit for converting an NTSC signal into a digital signal and a second A / D converting circuit for converting an HD signal into a digital signal. A D conversion circuit, a first time axis conversion circuit for time-axis-converting the output signal of the first A / D conversion circuit and outputting it as a screen signal having a corresponding aspect ratio, and an output signal of the first time axis conversion circuit. A first D / A conversion circuit for converting into an analog signal, and the second A / A conversion circuit
A child screen processing circuit that processes the output signal of the D conversion circuit for a predetermined child screen size, and a second time when the output signal of this child screen processing circuit is time-axis converted and output as a screen signal of a corresponding aspect ratio. An axis conversion circuit and a second D / A for converting an output signal of the second time axis conversion circuit into an analog signal.
A conversion circuit, a combination circuit for combining the parent screen signal output from the first D / A conversion circuit and the child screen signal output from the second D / A conversion circuit, and outputting the combined result to a high-definition monitor via an output terminal; A switching circuit inserted between the first D / A conversion circuit and the synthesizing circuit for selecting one of the signal output from the first D / A conversion circuit and the synchronizing signal of the NTSC signal and outputting it to the synthesizing circuit. It is characterized by comprising.

[0007]

The NTSC signal is converted into a digital signal by the first A / D conversion circuit and is time-axis converted (for example, time-axis compressed) by the first time-axis conversion circuit to become a screen signal having a corresponding aspect ratio. The signal is converted into an analog signal by the / A conversion circuit and is guided to one input side of the synthesizing circuit via one of the switching circuits. The NTSC signal sync signals (horizontal sync signal Hd and vertical sync signal Vd) separated by the sync separation circuit are led to the other of the switching circuits. HD
The signal is converted into a digital signal by the second A / D conversion circuit, processed by the small screen processing circuit for a predetermined small screen size, and time-axis converted (for example, time-axis compressed) by the first time-axis conversion circuit. It becomes a screen signal of the corresponding aspect ratio,
Then, it is converted into an analog signal by the second D / A conversion circuit and guided to the other input side of the synthesis circuit.

By switching the switching circuit to the parent-child screen display side,
When the signal output from the first D / A conversion circuit is guided to the combining circuit, the NTSC signal converted into a digital signal, time-axis converted, and then converted into an analog signal is input to one input side of the combining circuit. Be guided. In addition, it is converted to a digital signal and has a predetermined child screen size (eg 1 / n)
The HD signal, which has been subjected to signal processing, time-axis conversion, and then converted into an analog signal, is guided to the other input side of the combining circuit. For this reason, the synthesizing circuit processes the N processed for the parent screen.
The TSC signal and the HD signal processed for the small screen are switched at a predetermined timing and output to the high-definition monitor,
A small screen by the HD signal is combined with a part of the main screen by the NTSC signal and displayed.

When the switching circuit is switched to the HDTV-NTSC converter side and the synchronizing signal of the NTSC signal is guided to the synthesizing circuit, only the screen by the HD signal is displayed. Set it appropriately. For example, the thinning rate in the horizontal direction is set to zero, and the thinning rate in the vertical direction is appropriately set in consideration of the aspect ratio and the time axis conversion (for example, thinning to 1/3). In this case, the NTSC signal synchronizing signal is introduced to one input side of the synthesizing circuit, and converted to a digital signal on the other input side of the synthesizing circuit, and the image signal of the corresponding aspect ratio (3: 4) is obtained. Then, the HD signal converted to the time axis and then converted to the analog signal is introduced.

Therefore, an NTSC receiver or N
When the TSCVTR is connected, the synthesizing circuit switches the HD signal processed for the parent screen and the synchronizing signal of the NTSC signal at a predetermined timing to switch the NTSC receiver side or the NTSCVT side.
It is possible to output to the R side, display a screen of high-definition broadcasting with this general-purpose NTSC receiver, and record and reproduce the video signal with a general-purpose NTSC VTR.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a parent-child screen signal synthesizing circuit of a high-definition receiver according to the present invention will be described below with reference to FIG. In FIG. 1A, reference numeral 20 is a VHF or UHF receiving antenna, 22 is a BS antenna, and 24 is a receiving circuit of a high-definition receiver. The receiving circuit 24 includes a tuner 26 and a tuner 26 which are sequentially coupled to the receiving antenna 20. I
The F circuit 28, the BS tuner 30 and the MUSE decoder 32 which are sequentially coupled to the BS antenna 22, and the NTSC signal (for example, R, which is output from the IF circuit 28).
A PIP circuit 36 as a parent-child screen signal synthesizing circuit for synthesizing the G and B video signals) and the HD signal (for example, the R, G, B video signals) output from the MUSE decoder 32 and outputting the result to the output terminal 34. It is equipped with.

A high-definition monitor 38 and an RGB / composite conversion circuit 40, which are selectively selected, are coupled to the output terminal 34, and an NTSC receiver 42 and an NTSC VTR are provided on the output side of the RGB / composite conversion circuit 40.
Both or one of 44 is bound. The RGB / composite conversion circuit 40 is a circuit for converting R, G, B video signals into composite signals.

The PIP circuit 36 is formed as shown in FIG. That is, the first circuit for converting the NTSC signal output from the IF circuit 28 into a digital signal
A / D conversion circuit 46 and a second A / D for converting the HD signal output from the MUSE decoder 32 into a digital signal
The conversion circuit 48 and an ED (Enhanced or Extended) sequentially coupled to the output side of the first A / D conversion circuit 46.
Nested Definition) processing circuit 50, first
A time axis conversion circuit 52 and a first D / A conversion circuit 54,
A sub-picture processing circuit 56, a second time axis conversion circuit 58, and a second circuit, which are sequentially coupled to the output side of the second A / D conversion circuit 48.
A D / A conversion circuit 60, a sync separation circuit 62 for separating a sync signal (horizontal sync signal Hd, vertical sync signal Vd) from an NTSC signal, a sync signal from this sync separation circuit 62 and the first D / A conversion circuit. A switching circuit 64 for selecting one of the signals from the switching circuit 54 and a combining circuit for switching the signal from the switching circuit 64 and the signal from the second D / A conversion circuit 60 at a predetermined timing and outputting them to the output terminal 34. 6
6 and.

The ED processing circuit 50 sequentially scans interlaced scanning (non-interlaced).
Signal processing such as scanning line interpolation and double speed conversion in order to realize the above-mentioned operation. Known EDTV (Enhanced Te
Levision or Extended Define
It is a well-known circuit used in an edition television receiver. For example, a screen display of 2: 1 interlace scanning (262.5) by superimposing two field images into one frame image.
(60/60 seconds) to double-speed progressive scanning (non-interlaced) screen display (525/60 seconds), the horizontal scanning frequency (15.734 kHz) of the receiver is doubled to 31.47 kHz, Two scanning lines are drawn within a normal horizontal scanning period.

The first time axis conversion circuit 52 is a high-definition monitor 38 having an aspect ratio of 9:16 and reproduces an NTSC screen having an aspect ratio of 3: 4 as a video image without distortion such as lateral expansion or lateral contraction. In addition, it is a circuit for time-axis conversion (for example, time-axis compression) of a signal. Also, the second
When the switching circuit 64 selects the sync signal from the sync separation circuit 62, the time axis conversion circuit 58 has the NTSC receiver 42 with a display screen aspect ratio of 3: 4.
Then, in order to reproduce a high-definition screen having an aspect ratio of 9:16 as a video without distortion such as lateral expansion or lateral contraction, the signal is time-axis converted (for example, time-axis expanded), and the switching circuit 64 is operated by the first D / A. When the signal for the main screen from the conversion circuit 54 is selected, the signal for reproducing the high-definition screen having the aspect ratio of 9:16 synchronized with the main screen by the NTSC signal is displayed on the high-definition monitor 38 having the aspect ratio of 9:16. Is a circuit for performing time-axis conversion (for example, time-axis compression).

The sub-screen processing circuit 56 is configured to operate the second A /
This is a circuit for processing the signal output from the D conversion circuit 48 to have a predetermined child screen size. For example, the signals in the horizontal direction and the vertical direction are thinned out to reduce the signal to 1 / n. At this time, when n = 1, there is no thinning in the horizontal and vertical directions.

Next, the operation of the above embodiment will be described with reference to FIG. A: First, the case where the parent-child screen is displayed on the high-definition monitor 38 will be described. (A) The switching circuit 64 is switched to the first D / A conversion circuit 54 side, and the output terminal 34 is connected to the high-definition monitor 38 as shown by the dotted line in FIG. At this time, the NTSC signal is converted into a digital signal by the first A / D conversion circuit 46, signal processing such as scanning line interpolation and double speed conversion is performed (deinterlaced) by the ED processing circuit 50, and then the first time axis. The conversion circuit 52 performs a time-axis conversion (for example, time-axis compression) process for reproducing an image without distortion such as lateral expansion and lateral contraction on the high-definition monitor 38, and is converted into an analog signal by the first D / A conversion circuit 54. , Is guided to one input side of the combining circuit 66 via the switching circuit 64.

At this time, if the frequency of the sampling clock by the first A / D conversion circuit 46 is 4Fsc (Fsc represents a color subcarrier frequency of about 3.58 MHz), and the frequency of the sampling clock of the ED processing circuit 50 is 8Fsc, The frequency of the read clock from the conversion memory in the first time axis conversion circuit 52 is 4/3 times the frequency of the write clock, that is, (32 /
3) It becomes Fsc.

(B) Further, the HD signal is converted into a digital signal by the second A / D conversion circuit 48, and the child screen processing circuit 5
6, the signal is processed for a predetermined small screen size (for example, reduced to 1 / n), the second time axis conversion circuit 58 performs time axis conversion (for example, time axis compression), and then the second D / A conversion circuit 60.
Is converted into an analog signal and guided to the other input side of the combining circuit 66. Assuming that the frequency of the sampling clock in the second A / D conversion circuit 48 is 12 Fsc, the number of sample data of the HDTV video portion in one horizontal scanning period is about 1.
057 (24.6 (μs) x 12 Fsc (MHz))
Becomes This 24.6 (μs) indicates one horizontal scanning period (effective portion) of HDTV.

For this reason, the image portion of the small screen by the HD signal which is thinned to 1 / n by the small screen processing circuit 56 is
1057 / n pixels in the horizontal direction and 1035/2 in the vertical direction
If there are n lines and the horizontal period is x ₁ , this x _{1 can be} calculated by the following equation (1). 490: 1035 / 2n = 26.4: x ₁ (1) Here, 490 represents the number of effective scanning lines of the main screen by the non-interlaced NTSC signal, and 26.4 (μ
s) represents one horizontal scanning period (valid) of the parent screen.
Therefore, when the frequency of the read clock from the conversion memory in the second time axis conversion circuit 58 is F ₁ , this F ₁ is obtained by the following equation (2). F ₁ = 1 / {x ₁ / (1057 / n)} (2)

(C) Therefore, the synthesizing circuit 66 uses the first D
The parent screen signal from the A / A conversion circuit 54 and the child screen signal from the second D / A conversion circuit 60 are switched at a predetermined timing and output to the high-definition monitor 38 via the output terminal 34. ), A high-definition monitor 38 having an aspect ratio of 9:16 displays a parent screen 70 by an NTSC signal having an aspect ratio of 3: 4, and a part of the parent screen 70 has an aspect ratio of 9: 9. 1
The child screen 72 based on the HD signal 6 is synthesized and displayed.

B: Next, a general-purpose NTSC receiver 42 displays a high-definition broadcast screen, and a general-purpose NTSCV
A case of recording a high-definition broadcast signal in TR44 will be described. (A) The switching circuit 64 is switched to the HDTV-NTSC conversion side, that is, the sync separation circuit 62 side, and the output terminal 34 has RGB signals as shown by the solid line in FIG.
Connect either or both of the NTSC receiver 42 and the NTSC VTR 44 via the composite conversion circuit 40.

NTSC having an aspect ratio of 3: 4
The thinning rate of the small screen processing circuit 56 is set in order to display a video screen having an HDTV aspect ratio (9:16) on a predetermined area of the display screen of the receiver 42. For example, when the high-definition broadcast screen is displayed horizontally on the display screen of the NTSC receiver 42, horizontal thinning is not performed, and vertical vertical thinning is performed to 1 / n.

(B) At this time, the horizontal synchronizing signal Hd and the vertical synchronizing signal Vd separated from the NTSC signal by the synchronizing separating circuit 62 are introduced to one input side of the synthesizing circuit 66 via the switching circuit 64. On the other input side of the synthesizing circuit 66, the second A / D converting circuit 48 converts the signal into a digital signal, the small screen processing circuit 56 processes the signal to a predetermined screen size, and the second time axis converting circuit 58 processes the time. Axis converted, second
The HD signal converted into an analog signal by the D / A conversion circuit 60 is guided.

Specifically, the sub-screen processing circuit 56 does not thin out in the horizontal direction but thins out to 1/3 in the vertical direction (n = 3).
in the case of). That is, as shown in FIG. 2B, the display screen of the NTSC receiver 42 has an aspect ratio of 3: 4, one horizontal scanning period (effective) in interlaced scanning is 52.8 μs, and one field. The number of effective scanning lines is 490/2. On the other hand, as shown in FIG. 2C, an HD signal HD video screen has an aspect ratio of 9:16 and one horizontal scanning period (effective) in interlaced scanning of 24.6 μ.
s The number of effective scanning lines in one field is 1035/2.

Therefore, when a video screen having an aspect ratio of 9:16 according to the HD signal is displayed in the horizontal direction of the display screen of the NTSC receiver 42, the desirable number of scanning lines in one field is (b) in FIG. As indicated by the dotted line, the number is about 183 ((490/2) × 3/4 = about 183). on the other hand,
The number of effective scanning lines in one field by HD signal is 1035
This is because, since the number of scanning lines is / 2, the number of scanning lines is approximately 172, which is close to 183, which is desirable, when thinning out to 1/3 (that is, n = 3) in the vertical direction, which is not visually noticeable.

Further, the second time base conversion circuit 58 specifically carries out the following time base expansion. That is, since the effective time required for one horizontal scanning is different as shown in (b) and (c) of FIG. 2, the data of one horizontal scanning period (24.6 μs) by the HD signal is converted into one horizontal scanning period by the NTSC signal. It is necessary to extend the data to (52.8 μs).

Therefore, assuming that the frequency of the sampling clock in the second A / D conversion circuit 48 is 12 Fsc, the number of sample data of the HDTV video portion in one horizontal scanning period is about 1057 (24.6 (μs) × 12 Fsc).
(MHz)), and since the effective horizontal scanning period of 1057 pixels is 52.8 μs, the frequency of the read clock from the conversion memory in the second time axis conversion circuit 58 is F
_If this is ₂ , this F ₂ is obtained by the following equation (3). F ₂ = 1 / {52.8 (μs) / 1057} (3) When the above formula (3) is calculated, F ₂ becomes 20.02 (MHz).

(C) Therefore, the synthesizing circuit 66 receives the synchronizing signals Hd and Vd from the synchronizing separating circuit 62 and the second D / A.
The signal from the conversion circuit 60 processed into a predetermined size is switched at a predetermined timing and output to the output terminal 34.
Therefore, the NTSC receiver 4 connected to the output terminal 34
2 displays a high-definition broadcast screen as shown in FIG. 2D, and is an NTSC VTR 4 connected to the output terminal 34.
Reference numeral 4 records and reproduces a high-definition broadcast signal (HD signal subjected to predetermined signal processing).

In the above embodiment, the NTSC signal is the signal received by the receiving antenna and the HD signal is the signal received by the BS antenna. However, the present invention is not limited to this.
For example, the NTSC signal may be a signal obtained from a general-purpose TV camera, a VTR, or the like, and the HD signal may be a signal obtained from a high-definition camera, a high-definition VTR, or the like.

[0031]

As described above, when the switching circuit is switched to the parent-child screen display side, the parent-child screen signal synthesizing circuit of the high-definition receiver according to the present invention uses the NTSC signal as the parent screen signal and the HD signal as the child screen. Lead it to the synthesis circuit as a signal
This composition circuit switches the parent screen signal and the child screen signal at a predetermined timing and outputs them to the high-definition monitor connected to the output terminal, so that the child screen is composed and displayed on a part of the parent screen. , The HD monitor of the HDTV receiver does not cause distortion such as lateral expansion or lateral contraction, and H is displayed on a part of the parent screen by the NTSC signal.
It is possible to synthesize and display the sub-screen by the D signal.

Furthermore, when the switching circuit is switched to the HDTV-NTSC converter side, that is, the sync separation circuit side,
Since the synchronizing signal separated from the NTSC signal and the signal obtained by processing the HD signal to a predetermined size are guided to a synthesizing circuit and synthesized and output to an NTSC receiver or NTSC VTR connected to the output terminal New HDT
A high-definition broadcast screen can be used for general-purpose NT without adding a V-NTSC converter and simply adding a simple circuit.
It can be displayed on an SC receiver, and a high-definition broadcast signal can be recorded and reproduced by a general-purpose NTSC VTR.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a parent-child screen signal combining circuit of a high-definition receiver according to the present invention.

FIG. 2 is an explanatory view for explaining the operation of FIG. 1, in which (a) is a high-definition monitor and H is displayed on a part of the parent screen by the NTSC signal.
Explanatory drawing explaining the display state at the time of displaying the small screen by D signal, (b) Explanatory drawing explaining the scanning line number and the horizontal scanning period of the interlaced scanning display screen of an NTSC receiver,
(C) is an explanatory view for explaining the number of scanning lines and the horizontal scanning period of the interlaced scanning display screen of the high-definition monitor, and (d) is N
It is explanatory drawing explaining the display state at the time of displaying the high-definition broadcast screen by a HD signal with a TSC receiver.

FIG. 3 is a block diagram showing a parent-child screen signal combining circuit of a conventional NTSC receiver.

[Explanation of symbols]

34 ... Output terminal, 36 ... PIP (picture in picture) circuit, 38 ... Hi-vision monitor, 42 ... NTS
C receiver, 44 ... NTSC VTR, 46 ... First A / D
Conversion circuit, 48 ... second A / D conversion circuit, 50 ... ED processing circuit, 52 ... first time axis conversion circuit, 54 ... first D / D
A conversion circuit, 56 ... Small screen processing circuit, 58 ... Second time axis conversion circuit, 60 ... Second D / A conversion circuit, 62 ... Sync separation circuit, 64 ... Switching circuit, 66 ... Combining circuit.

Claims (1)

[Claims] 1. A first A / D conversion circuit for converting an NTSC signal to a digital signal, a second A / D conversion circuit for converting an HD signal to a digital signal, and an output signal of the first A / D conversion circuit on a time axis. A first time axis conversion circuit for converting and outputting as a screen signal of a corresponding aspect ratio, and a first D for converting an output signal of the first time axis conversion circuit into an analog signal.
/ A conversion circuit, a sub-screen processing circuit for processing the output signal of the second A / D conversion circuit for a predetermined sub-screen size, and an aspect corresponding to the output signal of the sub-screen processing circuit by time-axis conversion A second time axis conversion circuit for outputting as a ratio screen signal, a second D / A conversion circuit for converting an output signal of the second time axis conversion circuit into an analog signal, and the first
The parent screen signal output from the D / A conversion circuit and the second D / A
A combination circuit for combining the sub-screen signal output from the A conversion circuit and outputting the same to the high-definition monitor via an output terminal, and the first D / A conversion circuit and the combination circuit inserted between the first D / A conversion circuit and the combination circuit. The signal output from the conversion circuit and the N
A parent-child screen signal synthesizing circuit for a high-definition receiver, comprising: a switching circuit for selecting one of the synchronizing signals of the TSC signal and outputting it to the synthesizing circuit.