JPH06125498A - Multi-picture processing circuit for multi-picture display television receiver - Google Patents

Abstract

PURPOSE:To prevent a video signal out of synchronization from being outputted to a monitor. CONSTITUTION:A multi-picture display television receiver implementing A/D conversion of a correspondent video signal and video signal processing with a clock signal synchronously with synchronizing signals D1-D4 separated from plural video signals V1-V4 and outputting a video signal synthesized by a picture synthesis circuit 36 to a monitor via a D/A converter circuit 38 to display a multi-picture is provided with a synchronizing signal switching circuit 50 selecting the synchronizing signals D1-D4 and outputting the selected signal as the synchronizing signal for video processing at the time of picture synthesis and after the synthesis, a synchronizing signal detection circuit 60 detects the synchronizing signal outputted from the changeover circuit 50, a microcomputer 64 compares the detected value with a reference value stored in advance in a memory 62 and the circuit of the synchronizing signal changeover circuit 50 is controlled on the result of comparison to prevent it that the video signal out of synchronization is outputted to the monitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
A multi-screen display television capable of displaying two or more multi-screens by performing D (analog / digital) conversion and video signal processing, combining by a screen combining circuit, and then D / A converting and outputting to a monitor. The present invention relates to a multi-screen processing circuit in a John receiver.

[0002]

2. Description of the Related Art Conventionally, in this type of multi-screen display television receiver, a Pict which displays a child screen on a part of a parent screen.
The one with the picture in picture function and the picture out which displays the child screen outside the parent screen
Those with a Picture function are known. Then, in the case of this parent-child screen (for example, when one of the parent screen and the child screen is an HD screen and the other is an NTSC screen), a clock signal used for the processing of the video signal after the screen combination and for the D / A conversion. Was made based on the sync signal included in the video signal for the parent screen.

When the above concept is applied to a multi-screen display television receiver including a composite display of three or more screens,
A configuration as shown in FIGS. 3 to 5 can be considered. That is, in FIG. 3, the video signal received by the BS antenna 10 is guided to the BS tuner 12, and the BS tuner 12
The detection output signal from is guided to the high-definition monitor 16 via the MUSE decoder 14, and the aspect ratio is 16 :.
9 HD screen can be displayed and MUS
Input selection circuit 20 via E-NTSC converter 18
Lead to. In addition, some BSs (satellite broadcasts) use the NTSC system, so the BS tuner 1
The output from 2 is directly led to the input selection circuit 20. Also, U
The video signal received by the / V antenna 22 is guided to the input selection circuit 20 via the U / V tuner 24, and the VTR
The video signal from the external input device 26 as described above is guided to the input selection circuit 20.

Then, the plurality of video signals selected by the input selection circuit 20 are signal-processed by the multi-screen processing circuit 28 and guided to the high-definition monitor 16, and the high-definition monitor 16
Thus, multiple screens (that is, multiple screens) corresponding to a plurality of video signals selected by the input selection circuit 20 can be combined and displayed.

For example, as shown in FIG.
The four screens P _{1 to} P ₄ (each of which has an aspect ratio of 4: 3) by the SC system first to fourth video signals V _{1 to} V ₄ are displayed on the high-definition monitor 16 or (in the same figure). As shown in c), seven screens P _{1 to} P ₇ according to the first to seventh video signals V _{1 to} V ₇ of the NTSC system are displayed on the high-definition monitor 16. Thereby, as shown in FIG. 4A, one screen P ₁ by the first video signal V ₁ of the NTSC system is displayed on the high-definition monitor 1
No-image part 25, 25 when displayed on 6
Can be effectively utilized.

The multi-screen processing circuit 28 is a circuit for performing signal processing such as NTSC-HD conversion, video signal thinning-out, screen composition, etc., and is configured as shown in FIG. That is, the first, second, third and fourth input terminals 30 ₁ , 30 ₂ , 3
0 _3, 30 ₄ first entered into the second, third, and fourth video signal V _1, V _2, V _3, V _4, first, second, third, 4A / D
The conversion circuits 32 ₁ , 32 ₂ , 32 ₃ , 32 ₄ convert the signals into digital signals, and the first, second, third, and fourth video signal processing circuits 34
_The screen synthesizing circuit 3 performs signal processing such as NTSC-HD conversion and video signal thinning at ₁ , 34 ₂ , 34 ₃ , and 34 _4.
Lead to 6. The video signal synthesized by the screen synthesis circuit 36 is converted into an analog signal by the D / A conversion circuit 38 and guided to the high-definition monitor 16 via the output terminal 40.

First, second, third and fourth A / D conversion circuits 3
The signal processing in 2 ₁ , 32 ₂ , 32 ₃ , 32 ₄ and the first, second, third, and fourth video signal processing circuits 34 ₁ , 34 ₂ , 34 ₃ , 34 ₄ is performed in the first, second, and 3, 4th sync separation circuit 4
_1st , _2nd , 3rd and 4th sync signals (horizontal sync signal and vertical sync signal) separated by 2 ₁ , 42 ₂ , 42 ₃ and 42 _4.
It is performed based on a predetermined clock signal synchronized with D ₁ , D ₂ , D ₃ and D ₄ .

The signal processing in the screen synthesizing circuit 36 is performed for a predetermined clock signal synchronized with the first, second, third and fourth synchronizing signals D ₁ , D ₂ , D ₃ and D ₄ and a reference synchronizing signal. This is performed based on the selected first video signal V ₁ and a predetermined clock signal synchronized with the first synchronization signal D ₁ . Video signal for the reference synchronizing signal may be a second, third or fourth video signal V _2, V _3, V ₄ other than the first video signal V _1.
The signal processing in the D / A conversion circuit 38 and the high-definition monitor 16 is performed based on a predetermined clock signal synchronized with the first synchronization signal D ₁ . Reference numeral 44 is an output terminal for outputting the first synchronizing signal D ₁ to the high-definition monitor 16.

[0009]

However, in the multi-screen processing circuit 28 shown in FIG. 5, the screen composition circuits 36, D
/ Signal processing in A conversion circuit 38 and the high definition monitor 16, since performed based on a clock signal synchronized with the first synchronization signal D ₁ of the reference synchronizing signal, as an input selection circuit 20 first video signal V ₁ When a signal of a channel without broadcasting (for example, the fifth channel in the Tokyo region) or a signal of which broadcasting has ended is selected, the screen synthesis circuit 36 or D
There is a problem that the synchronization signal D _{1 which} is the basis of the clock signal for the signal processing in the A / A conversion circuit 38 disappears and the screen becomes out of synchronization.

A MUSE HDTV broadcast signal is selected as the first video signal V ₁ , and NTSC TV broadcast signals are selected as the second, third and fourth video signals V ₂ , V ₃ and V _4. When the timing of the first sync signal D ₁ for the reference sync signal is different from the timing of the second, third, and fourth sync signals D ₂ , D ₃ , and D ₄ as in the case of selection, output to the high-definition monitor 16. However, there is a problem that the video signals to be synchronized cannot be synchronized.

The present invention has been made in view of the above problems, and provides a multi-screen processing circuit of a multi-screen display television receiver capable of preventing a video signal which is out of synchronization from being output to a monitor. That is the purpose.

[0012]

A multi-screen processing circuit of a multi-screen display television receiver according to the first aspect of the present invention uses a clock signal synchronized with a sync signal separated from a plurality of video signals to generate an A A multi-screen display television receiver configured to display a multi-screen by performing D / D conversion and video signal processing, and then outputting a video signal composited by a screen composition circuit to a monitor through a D / A conversion circuit. , A sync signal switching circuit for selectively switching the plurality of sync signals to output as a sync signal for video signal processing during and after screen composition, and whether or not there is a sync signal output from the sync signal switching circuit And a switching control circuit that controls switching of the synchronization signal switching circuit based on the determination output of the synchronization signal determination circuit. And it is characterized in Rukoto.

The multi-screen processing circuit of the multi-screen display television receiver according to the second aspect of the present invention uses the clock signal synchronized with the sync signal separated from the plurality of video signals to perform A / D conversion of the corresponding video signal and the video signal. In a multi-screen display television receiver configured to display a multi-screen by performing a process and then outputting a video signal synthesized by the screen synthesis circuit to a monitor through a D / A conversion circuit,
A synchronization signal switching circuit for selectively switching the plurality of synchronization signals and outputting as a synchronization signal for video signal processing during and after screen composition, and a synchronization signal for detecting the synchronization signal output from the synchronization signal switching circuit. A detection circuit, a memory in which a reference synchronization signal is stored in advance, a synchronization signal detected by the synchronization signal detection circuit and a reference synchronization signal of the memory are compared, and the synchronization is performed based on the comparison result. And a switching control circuit for controlling switching of the signal switching circuit.

[0014]

In the multi-screen processing circuit of the multi-screen display television receiver according to the first and second aspects of the present invention, the plurality of video signals correspond to the corresponding video signals in the corresponding A / D conversion circuits and video signal processing circuits. Is subjected to A / D conversion processing and video signal processing by a clock signal synchronized with the sync signal separated from the above, and then guided to a screen synthesis circuit. The video signal synthesized by the screen synthesis circuit is output to the monitor via the D / A conversion circuit, and multiple screens (plural screens) are displayed on one screen of the monitor. In this case, the synthesizing process, the D / A converting process, and the displaying process are performed by a signal (for example, a clock signal) synchronized with one of the plurality of synchronizing signals separated from the plurality of video signals.

At this time, according to the first aspect of the present invention, video signal processing at the time of screen composition and after composition (for example, a screen composition circuit, D /
Signal processing in the A conversion circuit and the monitor) is processed by a signal synchronized with the sync signal which is selectively output from the sync signal switching circuit, and the sync signal determination circuit determines the presence or absence of the sync signal output from the sync signal switching circuit. Then, the switching control circuit controls switching of the synchronization signal switching circuit based on the discrimination output from the synchronization signal discrimination circuit. Therefore, the video signal corresponding to the sync signal output from the sync signal switching circuit is
In the case of a signal of a channel without broadcasting or a signal of which broadcasting has ended, the sync signal determination circuit determines the absence of the synchronization signal, and the switching control circuit controls the switching of the synchronization signal switching circuit based on this determination output, The switching circuit outputs another synchronizing signal to prevent an unsynchronized video signal from being output to the monitor.

Further, in the second aspect of the present invention, a screen synthesis circuit, D
The signal processing in the A / A conversion circuit and the monitor is processed by the signal synchronized with the sync signal that is alternatively output from the sync signal switching circuit. This sync signal is detected by the sync signal detection circuit. The switching control circuit compares the detected synchronization signal with the reference synchronization signal stored in the memory in advance, and controls switching of the synchronization signal switching circuit based on the comparison result. Therefore, when the timing of the synchronizing signal output from the synchronizing signal switching circuit is different from the timing of the synchronizing signal separated from the other video signals (for example, the former synchronizing signal is an HDTV (MUSE system) signal is NTS).
The sync signal separated by the C-system sync separation circuit, where the latter sync signal is the NTSC system TV sync signal), and the switching control circuit controls the switching of the sync signal switching circuit based on the mismatch of the sync signals. The switching circuit outputs another synchronizing signal to prevent an unsynchronized video signal (for example, a video signal out of synchronization) from being output to the monitor.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multi-screen processing circuit of a multi-screen display television receiver according to the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the first invention, and the same parts in FIG. 1 as those in FIGS.
In FIG. 1, reference numerals 30 ₁ , 30 ₂ , 30 ₃ , and 30 ₄ input the first, second, third, and fourth video signals V ₁ , V ₂ , V ₃ , and V ₄ selected by the input selection circuit 20. It is an input terminal to.

The first, second, third and fourth input terminals 30
Each of ₁ , 30 ₂ , 30 ₃ , 30 ₄ has a first, second,
Third and fourth A / D conversion circuits 32 ₁ , 32 ₂ , 32 ₃ , 32 ₄
And the first, second, third and fourth video signal processing circuits 3
4 ₁ , 34 ₂ , 34 ₃ , 34 ₄ are sequentially coupled, and first, second, third and fourth sync separation circuits 42 ₁ , 42 ₂ , 42 are connected.
₃ , 42 ₄ are combined. The first, second, third, fourth
A screen synthesizing circuit 36, a D / A converting circuit 38 and an output terminal 40 are sequentially coupled to the output sides of the video signal processing circuits 34 ₁ , 34 ₂ , 34 ₃ and 34 ₄ , and the output terminal 40 is an input of the high-definition monitor 16. Is bound to the side.

The first, second, third and fourth sync separation circuits 42 ₁ , 42 ₂ , 42 ₃ , 42 ₄ are connected to the first, second, third and fourth video signals V ₁ , V _{2 respectively.} , V ₃ , V ₄ , separated from the first, second, third, and fourth synchronization signals D ₁ , D ₂ , D ₃ , D ₄ ,
The first, second, third and fourth A / D conversion circuits 32 ₁ , 3
2 ₂ , 32 ₃ , 32 ₄ and the first, second, third, and fourth video signal processing circuits 34 ₁ , 34 ₂ , 34 ₃ , 34 ₄ corresponding to the corresponding circuits, and the screen synthesis circuit 36. It is output to the synchronization signal switching circuit 50.

The sync signal switching circuit 50 is one of the first, second, third and fourth sync signals D ₁ , D ₂ , D ₃ and D _4.
One of them as a sync signal for the reference sync signal (for example, D ₁ ), and the screen synthesizing circuit 36 and D / A are switched.
It is configured to output to the conversion circuit 38 and also to the high-definition monitor 16 via the output terminal 44.

Reference numeral 52 is a sync signal discriminating circuit for discriminating whether or not there is a sync signal on the output side of the sync signal switching circuit 50, and 54 is the sync signal switching circuit based on the discriminative output of the sync signal discriminating circuit 52. A switching control circuit that controls switching of the circuit 50. The switching control circuit 54 is configured to switch and control the synchronization signal switching circuit 50 based on a signal that the synchronization signal determination circuit 52 determines that there is no synchronization signal. ing.

Next, the operation of the above embodiment will be described. (A) First, second, third and fourth input terminals 30 ₁ , 30 ₂ ,
1st, 2nd, 3rd, respectively input to 30 ₃ and 30 ₄
The fourth video signals V ₁ , V ₂ , V ₃ , V ₄ are converted into digital signals by the first, second, third and fourth A / D conversion circuits 32 ₁ , 32 ₂ , 32 ₃ , 32 ₄ , The first, second, third, and fourth video signal processing circuits 34 ₁ , 34 ₂ , 34 ₃ , and 34 _{4 use} NTSC-.
Signal processing such as HD conversion and thinning of video signals is performed.

At this time, the first, second, third and fourth A / D
The conversion circuits 32 ₁ , 32 ₂ , 32 ₃ , 32 ₄ have first, second, third, and fourth synchronization separation circuits 42 ₁ , 42 ₂ , 42, respectively.
The first, second, third and fourth synchronization signals D ₁ from ₃ , 42 ₄
Sync signal D ₁ , created based on D ₂ , D ₃ and D ₄ ,
The video signals V ₁ , V ₂ , V ₃ and V ₄ are converted into digital signals by the clock signal synchronized with D ₂ , D ₃ and D ₄ .

The first, second, third and fourth video signal processing circuits 34 ₁ , 34 ₂ , 34 ₃ , 34 ₄ are based on the synchronizing signals D ₁ , D ₂ , D ₃ , D ₄ , respectively. By the clock signal created and synchronized with the synchronizing signals D ₁ , D ₂ , D ₃ and D ₄ ,
Signal processing such as NTSC-HD conversion and thinning of video signals for the digitally converted video signals V ₁ , V ₂ , V ₃ , and V ₄ is performed. For example, a memory such as a line memory and a frame memory is used to reduce the area of a video signal of one screen size as necessary (for example, if five screens are displayed, the area of each small screen is 1 /
9 times). Also, in order to output to the high-definition monitor,
Scan line interpolation is performed using a memory such as a frame memory.

(B) Next, the signals processed by the first, second, third, and fourth video signal processing circuits 34 ₁ , 34 ₂ , 34 ₃ , and 34 ₄ are combined by the screen combining circuit 36. The combined video signal is converted into an analog signal by the D / A conversion circuit 38, and is output via the output terminal 40 to the high-definition monitor 16
Be led to.

At this time, the screen synthesizing circuit 36 makes clocks synchronized with the synchronizing signals D ₁ , D ₂ , D ₃ and D ₄ which are created based on the synchronizing signals D ₁ , D ₂ , D ₃ and D _4. Depending on the signal, the first, second, third and fourth video signals V ₁ , V ₂ ,
The data of V ₃ and V ₄ are written in a memory such as a frame memory and read from the memory by a clock signal synchronized with a reference synchronizing signal synchronizing signal (for example, D ₁ ) output from the synchronizing signal switching circuit 50.

Further, the D / A conversion circuit 38 uses the digital signal output from the screen synthesizing circuit 36 in response to the clock signal synchronized with the reference synchronizing signal synchronizing signal (for example, D ₁ ) output from the synchronizing signal switching circuit 50. Converts the composite video signal for the screen into an analog video signal. Then, the high-definition monitor 16 uses the deflection signal created based on the sync signal (for example, D ₁ ) output from the sync signal switching circuit 50 to generate the first, second, third, and fourth video signals V ₁ , V _2. , V
A multi-screen in which each of _four screens P ₁ , P ₂ , P ₃ , and P ₄ of ₃ and V ₄ is combined in a predetermined size is displayed.

(C) The sync signal discriminating circuit 52 receives the sync signal for the reference sync signal (for example, D from the sync signal switching circuit 50).
Determine whether or not ₁ ) is output. Switching control circuit 5
Reference numeral 4 controls switching of the synchronization signal switching circuit 50 based on the determination output from the synchronization signal determination circuit 52 (determination output that the synchronization signal for the reference synchronization signal is not output).

Therefore, when the signal of a channel without broadcasting (for example, the fifth channel in the Tokyo region) or the signal of which broadcasting is finished is selected as the first video signal V ₁ for the reference synchronizing signal, the synchronizing signal switching circuit 50 Although the sync signal D ₁ for the reference sync signal being output disappears, the sync signal determination circuit 5
2 determines that the sync signal D ₁ has disappeared, and the switching control circuit 54 controls the switching of the sync signal switching circuit 50. Therefore, the sync signal switching circuit 50 replaces the first sync signal D ₁ with the second sync signal D _1. D ₂ is output as a sync signal for a new reference sync signal. When the second synchronizing signal D ₂ disappears, the synchronizing signal switching circuit 5 operates in the same manner as described above.
0 outputs the third synchronization signal D ₃ .

That is, the synchronization signal switching circuit 50 includes
Since any of the fourth synchronization signals D _{1 to} D ₄ is output as the synchronization signal for the reference synchronization signal, a video signal without synchronization is not output to the high-definition monitor 16. Further, when all of the synchronizing signals D _{1 to} D ₄ are not present, the synchronizing signal switching circuit 50
The switching is repeated without outputting the synchronization signal, but there is no video signal to be displayed on the high-definition monitor 16, so there is no problem.

FIG. 2 shows an embodiment of the second aspect of the present invention. In this figure, the same parts as in FIG.
In FIG. 2, reference numeral 60 denotes a sync signal detection circuit that detects the sync signal output from the sync signal switching circuit 50. 62
Is a sync signal Dra for the first reference sync signal (for example, the same signal as the sync signals D _{1 to} D ₄ of the NTSC video signal) and a sync signal Drb for the second reference sync signal (for example, an HDTV signal). Is the same signal as the sync signal separated by the NTSC sync separation circuit) as pattern data.

64 is a microcomputer, and this microcomputer 64 is
The detection value K of the sync signal detection circuit 60 is stored in the memory 62.
Data is compared, the switching of the sync signal switching circuit 50 is controlled based on the comparison output, and a control signal for display is output to the on-screen circuit 66.

That is, the microcomputer 64 detects the detected value K
Is equal to the sync signal Dra for the first reference sync signal, neither the control signal for switching nor the control signal for display is output,
When the detected value K matches the sync signal Drb for the second reference sync signal, the sync signal switching circuit 50 outputs the control signal for switching.
To the sync signal D
A control signal for displaying that it is a broadcast (for example, high-definition broadcast) corresponding to rb (for example, the same as the sync signal obtained by separating the HDTV signal by the NTSC sync separation circuit) is output to the on-screen circuit 66 and detected. The value K has synchronization signals Dra and D for the first and second reference synchronization signals.
When it does not match rb, a control signal for switching is output to the synchronization signal switching circuit 50.

Therefore, when the signal of a channel without broadcasting (for example, the fifth channel in the Tokyo region) or the signal of which broadcasting is finished is selected as the first video signal V ₁ , the microcomputer 64 loses the synchronizing signal D _1. The control signal for switching is output to the synchronizing signal switching circuit 50 to control the switching, so that the synchronizing signal switching circuit 50 is the first
The second synchronization signal D ₂ is output instead of the synchronization signal D ₁ . When the second synchronizing signal D ₂ disappears, the third synchronizing signal D ₃ is newly output by the same operation as described above.

When the HDTV video signal is selected as the first video signal V ₁ instead of the NTSC system, the microcomputer 64 sends the switching control signal to the synchronization signal switching circuit 50.
To control the same switching as above,
Output a control signal for display to the on-screen circuit 66,
The display data is sent to the high-definition monitor 16 via the output terminal 68, and it is displayed that the video signal selected as the reference screen here is high-definition broadcasting.

[0036]

The multi-screen processing circuit of the multi-screen display television receiver according to the first aspect of the present invention,
By outputting another sync signal from the sync signal switching circuit under the switching control by the switching control circuit, a signal (for example, a clock signal) for performing the signal processing of the screen synthesizing circuit and the signal processing of the video signal after synthesis is obtained. With this configuration, it is possible to prevent an unsynchronized video signal from being output to the monitor and prevent a non-synchronized multi-screen display.

In the multi-screen processing circuit of the multi-screen display television receiver according to the second aspect of the present invention, the timings of the synchronizing signals for video signal processing during and after the screen synthesis are the same as those of other NTSC system synchronizing signals. In order to perform the signal processing of the screen synthesizing circuit and the signal processing of the video signal after the synthesizing by outputting another NTSC system synchronizing signal from the synchronizing signal switching circuit by the switching control by the switching control circuit, Since a signal (for example, a clock signal) suitable for the above is obtained, it is possible to prevent an out-of-synchronization video signal from being output to the monitor and prevent a multi-screen display that cannot be synchronized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-screen processing circuit of a multi-screen display television receiver according to the first invention.

FIG. 2 is a block diagram showing an embodiment of a multi-screen processing circuit of a multi-screen display television receiver according to the second invention.

FIG. 3 is a block diagram of a multi-screen display television receiver.

[Figure 4] HDTV monitor with one or more NTSC
It is explanatory drawing which displays a screen.

FIG. 5 is a block diagram of a multi-screen processing circuit when the concept of the conventional example is applied to a multi-screen display television receiver.

[Explanation of symbols]

16 ... HD _{monitor, 32 1 ~32 4 ... A /} D conversion circuit, 34 _{1-34 4} ... video signal processing circuit, 36 ... screen combining circuit, 38 ... D / A conversion circuit, 42 _{1-42 4} ...
Sync separation circuit, 50 ... Sync signal switching circuit, 52 ... Sync signal discriminating circuit, 54 ... Switching control circuit, 60 ... Sync signal detecting circuit, 62 ... Memory, 64 ... Microcomputer, D ₁ ...
D ₄ ... Sync signal, V _{1 to} V ₄ ... Video signal.

Claims (2)

[Claims] 1. A / A of a corresponding video signal by a clock signal synchronized with a synchronization signal separated from a plurality of video signals.
A multi-screen display television receiver configured to display a multi-screen by performing D conversion and video signal processing, and then outputting a video signal composited by a screen composition circuit to a monitor through a D / A conversion circuit, A sync signal switching circuit that selectively switches the plurality of sync signals and outputs the sync signals as a sync signal for video signal processing during and after screen composition, and determines the presence or absence of the sync signal output from the sync signal switching circuit. A multi-screen display television receiver comprising a sync signal discriminating circuit and a switching control circuit for controlling switching of the sync signal switching circuit based on a discriminative output of the sync signal discriminating circuit. Screen processing circuit. 2. A / A of a corresponding video signal by a clock signal synchronized with a synchronization signal separated from a plurality of video signals
A multi-screen display television receiver configured to display a multi-screen by performing D conversion and video signal processing, and then outputting a video signal composited by a screen composition circuit to a monitor through a D / A conversion circuit, A synchronization signal switching circuit for selectively switching the plurality of synchronization signals and outputting as a synchronization signal for video signal processing during and after screen composition, and a synchronization signal for detecting the synchronization signal output from the synchronization signal switching circuit. A detection circuit, a memory in which a reference synchronization signal is stored in advance, a synchronization signal detected by the synchronization signal detection circuit and a reference synchronization signal of the memory are compared, and the synchronization is performed based on the comparison result. A multi-screen processing circuit for a multi-screen display television receiver, comprising a switching control circuit for controlling switching of a signal switching circuit.