JPS61251897A - Image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing apparatus, and particularly to an image processing apparatus that enlarges a display image drawn on a display screen at a predetermined scale.

(Prior Art) Conventionally, an image enlargement operation involves taking out image data from a frame memory that stores a source image and performing calculations using complicated hardware.

(Problems to be Solved by the Invention) However, such conventional image processing apparatuses require the use of complex hardware and computations are complex, and therefore cannot be performed at high speed.

An object of the present invention is to provide an image processing device that can perform image enlargement operations at high speed with a simple configuration and without using complicated hardware.

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides an image processing device for enlarging a display image drawn on a display screen, which includes a first frame memory that stores an image for one frame; a second frame memory that stores another frame worth of images;
The tSAM is capable of inputting and outputting a part of image data to the first frame memory, and the tSAM is capable of inputting and outputting a part of the image data to the second frame memory, and the image data stored in the 15th AM is stored in a predetermined manner. was configured to be transferred with a scale factor of 25th AM, X and X address counters that specify the addresses of the first frame memory and second frame memory, DX and DY registers that determine the initial address for reading image data of the first frame, and the X address counter. An image processing apparatus is provided, characterized in that it has an X address correction counter that corrects an X address from.

(Operation) One line of source image data in the first frame memory is transferred from the address specified by the DY register to the first SAM (details of the SAM will be described later). One line of image data stored in the first SAM is transferred from the address specified by the DX address to the 25th AM, but at this time, the data is transferred to the second SAM according to the scale factor, for example, 1:2.
Duplicate pixels are input to AM. The image data stored in the second SAM is transferred to the second frame memory,
An X address correction counter is used to input duplicate rows, thereby providing enlarged image data in the second frame memory.

(Example) FIG. 1 is an explanatory diagram for explaining the present invention in detail, FIG. 2 is a block diagram of an image processing apparatus of the present invention, and FIG. 3 is a diagram showing a part of image data. It is a schematic diagram showing movement of.

As shown in FIG. 1, the present invention provides for enlarging image data stored in a first frame memory, for example the letter "A 11", into a second frame memory by a predetermined scale factor, in particular by a scale factor of 1:2. Specifically, as shown in Figure 2, each pixel constituting the image stored in the first frame memory is written to the second frame memory redundantly in both row and column directions. The upper left point of the desired image can be determined using the DX and DYX address counters.

Next, the configuration and operation of the image processing apparatus of the present invention will be explained with reference to FIG.

In FIG. 2, 1.2 is an X address counter, which specifies the X address and the X address of the first frame memory and the second frame memory. 3.4 is up (adder), and up 3 is
The address signal from the X address counter 1 and the DX address signal from the DX register 14 are added together and output to the multiplexer 6. Up 4 is used to add the address signal from the X address counter 1 and the DX address signal from the DX register 14 and output it to the multiplexer 6. DY address signal of the DY register 15 and the X address correction counter 18 outputted via the gate 17
The address correction signal from
The access control unit 7 is notified. The opening/closing of game) 16 and 17 is controlled by the RRAM-5A access control section 7. 5 is a CPU, which controls each part of the circuit. 6 is a multiplexer which selects the X address of the first frame memory and the 27th frame memory under the control of the CPU 5;
9 is specified. 7 is RRAM-
5A access control unit, which is a
'Controls reading/writing of image data between SAMII and the 25th A
Image data is transferred to M11 at a predetermined scale factor. 8 is a first frame memory, which stores a source image as usual. 9 is a first SAM (serial access memory);
Parallel input/output is possible, information can be retrieved from any address, and stored contents can be shifted. This first SAM 9 is configured to be able to input and output one row of images from the first frame memory to and from the first frame memory 8, and is determined by the DX register 14 based on the shift clock of the RRAM-5A access control unit 7. The image data is transferred from the offset position to the second SAM. lO is the second frame memory.

This is for storing enlarged images. Reference numeral 11 denotes a second SAM consisting of a serial access memory similar to the first SAM, and is configured to receive and receive image data from the first SAMQ, and to be able to read/write the image data to/from the second frame memory. However, the shift clock of l:2 is RR with respect to the shift clock of the first SAM.
Input from the AM-3A access control unit 7 to the first SAM
It is configured such that the pixels of the image data stored in the image data are inputted redundantly. 12.13 is the data transmitter/receiver, as usual.

CPU data bus and first frame memory8. or second
Image data is received and transferred to and from the frame memory 10 under the control of the CPU 5.

Also, 14 is a DX register, on the X coordinate (row direction)
15 is a DY register, which sets the offset amount DY on the Y coordinate (column direction) and outputs it to up 4 via game) 16. It is something. 18 is a Y address correction counter which counts up the corrected address on the Y coordinate and outputs it to up 4 via gate 17.

Next, the operation of the image processing apparatus of the present invention will be described below. The source image is written to the first frame memory 8 in the usual manner under the control of the CPU 5. In addition, desired offset amounts DX and DY are set in the DX register 14.0 and the Y register 15, respectively, according to the upper left point (enlargement copy start address) of the image portion to be enlarged. X and Y address counters 1.2 and Y address correction counter 18
Reset. Note that the gate 17 is prohibited at this point.

In this state, one line of image data is transferred from the first frame memory 8 to the first SAM, but as mentioned above, the offset iDY from the DY register 15 is the Y address from the Y address counter 2 (zero at this point). (reset to ) is added at up 4 and input to multiplexer 6, so the one row at the address offset by the DY address is the 3rd r1! 0 transferred to the first SAM as shown in FIG. Pixels are sequentially transferred to the second SAM from the address specified in the DX register of So x7
An overflow signal is output from the dress counter l.

The X address counter l is incremented by +1 each time a shift clock is sent to the second SAMII.

Furthermore, when the number of columns for one row is counted up, that is, when an overflow signal is generated, the count becomes zero.

Next, the first row is transferred from the second SAM to the second frame memory, but the initial address at this time is 0 determined by the Y address correction counter. For example, when the Y address correction counter is zero, the zero address is determined by the Y address correction counter. °Specified. That is, at this point, gate 17 is open, while gate 16 is closed, and the address of Y address counter 2 (which remains reset to zero at this point) and the setting of Y address correction counter 18 are The corrected address (e.g., zero address) is specified as the desired address (e.g., zero address) added in UP4. One line of image data is transferred from the second SAM to this designated address in the second frame memory IO as shown in FIG.

Next, the Y address correction counter 18 is counted up by 1, and one row of the same image data stored in the second SAM is transferred to the next row (second row) of the second frame memory as shown in FIG. will be forwarded to.

After that, the next row of image data in the first frame memory is Y
It is specified by incrementing the address counter 2 by 1, and thereafter one line of data is transferred to the first SAM in the same way.Furthermore, the image data is sequentially transferred to the second SAM in duplicate from the address offset by DX, and then the image data is transferred to the second SAM in duplicate.
It is input to the next row (third) of the frame memory 10. Then, the Y address correction counter is counted up by 1, and one row of the same image data is transferred to the next row (fourth) of the second frame memory IO.

Thereafter, the above-described operations are repeated to obtain an enlarged copy.

Note that the operation when the output of Up 4 overflows is outside the range and is therefore ignored.

(Effects of the Invention) As explained above, according to the present invention, with a simple configuration,
This has the effect of enlarging images at high speed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the present invention in detail. FIG. 2 is a block diagram of the image processing apparatus of the present invention. FIG. 3 is a schematic diagram showing movement of a portion of image data. l...X address counter, 2...Y address counter, 3, 4...up, 6...multiplexer,
7...RRAM-5A access control unit, 8...1st
Frame memory, 9...$ISAM, 10...2nd
Frame memory, 11...2nd SAM, 14...D
X register, 15...DY register, 18...Y address correction counter.

Claims (1)

[Claims] In an image processing device that enlarges a display image drawn on a display screen, a first frame memory that stores an image for one frame, a second frame memory that stores an image for another one frame, and a first frame memory that stores an image for one frame; a first SAM capable of inputting and outputting a part of image data to and from a second frame memory; and a first SAM capable of inputting and outputting a part of image data to and from a second frame memory;
A second SAM configured to transfer image data stored in the AM at a predetermined scale factor; DX and D for determining the initial address for reading image data
An image processing device comprising: a Y register; and a Y address correction counter that corrects the Y address from the Y address counter.