JPH0697393B2 - Bitmap processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device, and more particularly, to a processing device suitable for processing an image memory mapped in bit units.

[Conventional technology]

2. Description of the Related Art In recent years, display devices are equipped with a bitmap memory in which pixels on the screen correspond to the bits of the memory in order to display characters, graphic image images, and the like on the screen in a mixed manner and to obtain higher display capability. . That is, all the display on the screen is performed by rewriting the bit-mapped display memory in bit units (pixel units). When such a bit-mapped memory is processed by a conventional general processing device, since the unit for addressing the memory is a byte unit, the data on the bit map memory is directly addressed in a bit unit, It was impossible to handle arbitrary bit data. If this is handled consciously, the program to be processed becomes very complicated and the processing time increases. In order to solve such a problem, a hardware configuration as shown in FIG. 4 has been conventionally used. That is, according to FIG. 4, the bit processing unit 2 for exclusive use is provided for the defect in the bit processing of the general-purpose processing unit 1 and a specific bit processing such as bit block transfer and vector drawing is performed at high speed. The dedicated bit processing device 2
As disclosed in, for example, Japanese Patent Laid-Open No. 61-80331, the inside thereof is composed of a barrel shifter, a logical operation unit, and a master circuit to speed up specific bit processing.

[Problems to be solved by the invention]

However, in the conventional configuration shown in FIG. 4, although it is possible to perform high-speed processing within the range of the functions of the dedicated bit processing device 2, it is necessary to perform processing by the general-purpose processing device 1 when performing processing other than that function. Occurs and the processing performance is extremely reduced. In particular, recent display devices require a wide variety of display processing because the screen is made into a multi-window and characters, figures, images, etc. are combined and displayed in the window. It is very expensive to provide a dedicated bit processing device for each of such display processes.

Here, a problem when a conventional general-purpose processing device processes a bit-mapped memory is that the address management means of the memory is in byte units and cannot be directly addressed in bit units. Further, even if the address can be designated in bit units, there is no means for processing the bit length (data width) to be processed from that bit position as an arbitrary unit. That is, the memory is treated logically as a linear continuum addressed by bits, and a free memory space can be treated by giving an arbitrary bit length as a unit of processing.

It is an object of the present invention to provide a bitmap processing device that can obtain performance close to that of a conventional dedicated bit processing device by allowing a general-purpose processing device to process a bit-mapped memory.

[Means for solving problems]

The above object has and has a means for addressing a memory by bits, a means for specifying a bit length to be processed from the address position, and a means for calculating a specified bit length from the specified position. This is achieved by detecting that the bit length exceeds the physical memory word boundary and accessing the memory based on this detection.

[Action]

First, the unit of data transfer between the physical memory and the processing unit is
Because of a certain fixed bit length, physical memory addressing is addressed in that unit. The bit address part indicating the bit position is used to specify the bit position of the bit length. The word data read from the memory is set in a data register in the processing device, and bit arithmetic of arbitrary length is performed from the position indicated by the bit address section on this data register.

This data register corresponds to the word boundary of the memory and is composed of registers for two words. This is because an operation with an arbitrary bit length is operated across word boundaries. The trigger for updating the memory and the data register, which occurs when an operation is performed across word boundaries, is detected by testing the boundary detection flag. This is detected when calculating the bit address, and the memory is accessed based on the detection result. By providing such means in the processing device, the memory is logically managed by bits, and processing in arbitrary bit units becomes possible. That is, it is not necessary to directly recognize the physical word boundary of the memory as long as the memory is accessed based on the boundary detection flag.

〔Example〕

 An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the processing apparatus of the present invention. The bitmap memory 1 is a memory to be processed, and is usually a display memory (video RA) of a display device.
M) and character generator etc. 2 is the memory address register (MAR), 3 is the memory register (IDR), 4
Is a temporary register (OD
R). The general-purpose register (GR) 5 is a scratchpad type register file, and defines therein an address register and a data register managed by bits. The general-purpose register 5 has a length twice the data transfer width with the memory. The adder / subtractor 6 is a general-purpose register 5
Is a computing unit for calculating the bit address within, and sets the carry (down) to the word at the time of calculating the bit address in the word boundary detection flag 7. The source bit address register (SBA) 8 and the destination bit address register (DBA) 9 are the source operand,
Indicates the bit position of the data register of the destination operand. The bit address registers 8 and 9 are copies of the bit address part of the address register in the general-purpose register 5, and are set together with the address register of the general-purpose register 5 when calculating the address. Bit width register (WN
R) 10 is a register for designating an arbitrary bit length, and is operated by this bit length. Like the bit address registers 8 and 9, the bit width register 10 is also set when the bit length register defined in the general-purpose register is updated. The bit width register 10 also serves as the source input of the adder / subtractor 6. This is because the processed bit length is reflected in the address calculation. The bit calculator 20 includes a differential barrel shifter 11, a mask pattern generator 12, and a maskable logic calculator 13. The calculator 20 calculates the bit positions designated by the source bit address register 8 and the destination bit address register 9 by the bit length designated by the bit width register 10.

The arbitrary bit length data calculated by the bit calculator 20 is set in the data register in the general-purpose register 5. At this time, zero detection of arbitrary bit length data is set in the bit width zero detection flag 14. The detection flag 14 is used for testing an arbitrary bit length (for example, pixel data). Next, an embodiment in which a typical raster operation in a display device and bit block transfer which is the basis of character expansion are applied in the processing device of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 2 is a diagram for explaining an example of transferring 20-bit data from the source area of the memory to the destination area and the register definition in the general-purpose register at that time. SAR is a bit address register (RO) of the memory source, and DAR is a bit address register (R1) of the memory destination. BC
NT is a bit length register (R2) and has a transfer bit length set. SD _(n) and _{(n + 1)} are source data registers (R3), and DD _(n) and _{(n + 1)} are destination data registers (R4). Both have a data width of 2 words.

In this embodiment, the data transfer width between the memory and the processor is set to 16
Since it is a bit, the bit address part is represented by 4 bits. The lower 4 bits of the SAR and DAR addresses are used to indicate the bit address of the data register, and the respective bit addresses are set in SBA8 and DBA9. As the address to the memory, the address except the lower 4 bits is supplied as a physical word address.
The lower 4 bits of BCNT are set to WNR10, and 1 to 16 bits are arbitrarily calculated by this value. In this embodiment, since the transfer amount is 20 bits,
The remaining 4 bits divided by 16 are set in WNR10. Next, an example of the operation will be described with reference to the flowchart of FIG. First, as pre-processing, the word data in the memory indicated by SAR and DAR is read 2 words
_(n) , _{(n + 1)} , DD _(n) , and DD _{(n + 1)} are set (300). At this stage, a copy on the memory is prepared in the data register, so bit operation is executed (302). At this time, WNR10
Since the value of is 4 bits long, it is processed to the right by 4 bits. Here, in order to update the next bit address, the processing bit length indicated by WNR10 is added to SAR and DAR (30
4,308). That is, SAR and DAR indicate the next bit position, and this bit position is set again in SBA8 and DBA9. At this time, the boundary detection flag is set, so check it. If the boundary is exceeded, a memory read (306) is made to the source, a memory write is made to the destination,
Read (310).

If the boundary detection flag is not set, the bit data remains in that state because it can still be used. The value of WNR8 is subtracted from the value of BCNT to check the end of bit transfer (312). Since the remaining value at this time is 16, this value is set again in WNR10 and processed in the next loop 16-bit length.

This operation is repeated until BCNT becomes zero. Finally,
Since the operation on the data register ends, this result is written to the memory (314). In this way, the program is the same as the normal word transfer. The only difference is that the memory access is generated by the boundary detection flag.

Also, regarding bit processing, it is done internally in the register, and only when the bit data in the register becomes unnecessary
Since the memory is accessed, the memory is not unnecessarily accessed.

In the present embodiment, an example in which the bit block transfer is processed from the left direction has been shown, but it goes without saying that it is also possible to process from the right direction by giving the bit arithmetic unit directivity.

According to the present embodiment, since the memory can be managed by the bit address, the performance can be improved without adding a dedicated bit processing device, and the bit processing program can be simplified.

〔The invention's effect〕

According to the present invention, since the bit processing can be easily performed on the memory bit-mapped by the general-purpose processing device, it is possible to improve the processing performance without adding a dedicated bit processing device. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a bitmap processing device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the embodiment, and FIG. 3 is based on FIG. , A flowchart showing the operation, and FIG. 4 is a block diagram of a conventional display device. 1 ... bit map memory, 2 ... memory address register, 3,4 ... memory register, 5 ... general-purpose register,
6 ... Adder / subtractor, 7 ... Boundary detection flag, 8, 9 ... Bit address register, 10 ... Bit width register, 11 ...
Differential barrel shifter, 12 ... Mask pattern generator, 13 ... Maskable logic calculator.

Claims (1)

[Claims] 1. A processing device having a bitmap memory for addressing the memory on a bit-by-bit basis, wherein the processing device has a width twice the data transfer width with the memory. A data register that holds data, an address register that indicates a bit position of the data, a unit that calculates arbitrary bit data based on the bit position of the address register, and the calculated bit data is a boundary of the data register. And a means for detecting that the data has been processed beyond the range, the memory is sequentially accessed based on the detecting means, and the information in the bit map memory is processed in arbitrary bit units.