JPS61240723A - Communication equipment - Google Patents

Abstract

PURPOSE:To start easily a communication to a users who have changed their address or subscribed newly, by constituting the titled device so that a registered call code of a receiving device can be changed, added and erased easily. CONSTITUTION:In case of erasing a call code which has been registered in a RAM 31 in a receiving device contained in an electronic wrist watch, a call code writing circuit 60 makes a counter 54 count down, when a specified code for instructing an erasion is detected from a received message data. Subsequently, a registered call code of an address which is set from the counter 54 is outputted from the RAM 31, and this registered call code of 2 bytes and a call code of 2 bytes following the specified code are compared by a coincidence circuit 28. In case when they coincide, its coincident registered call code in the RAM 31 is erased. In this case, the call code writing circuit 60 brings a value of a pointer register 55 to a decrement, and always execute a control so as to indicate the largest address of the address in which the call code is stored.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a small communication device.

[Prior art and its problems]

In recent years, it has been considered to incorporate the well-known blur and topel systems into portable devices such as small electronic calculators and electronic wristwatches. In such a system, a receiving device is built into a computer or an electronic wristwatch, and when the corresponding call code sent from the transmitting device is received by the receiving device, an alarm sound is generated to alert each person wearing the watch. An individual will be called.

Furthermore, a system having a function of displaying the transmitted message data on the display section of the electronic wristwatch when the message data is transmitted together with the calling code from the transmitting device is also conceivable.

By the way, in the above system, the call code 9 (consisting of a group code and an individual code) for each receiving device is fixedly stored in advance in a ROM (usually a P-ROM). Therefore, it is difficult to change the registration of the calling code, and there is a problem in that it is not possible to respond flexibly to user changes. Further, for example, when calling all users in a specific group, it is necessary to send each call code.

[Purpose of the invention]

An object of the present invention is to easily change the registered calling code of the receiving device in a communication system using a receiving device built into a small computer, electronic wristwatch, etc., and to easily communicate with users corresponding to a plurality of corresponding calling codes. An object of the present invention is to provide a communication device capable of performing the following functions.

[Key points of the invention]

According to the present invention, in a communication device in which a receiving device is incorporated in, for example, an electronic wristwatch, individual data for registration transferred from a transmitting device or input means is stored in a memory that can be rewritten by a memory control means. Furthermore, a plurality of pieces of individual data can be stored in the memory, and the coincidence detecting means detects a coincidence between the individual calling data stored in the rewritable memory and the calling data transmitted from the transmitting means. Ru. Based on the coincidence detection by the coincidence detection means, the reception operation of the reception means is executed by the reception control means.

With a communication device having such a configuration, it is easy to change the registration call data registered in the receiving device. In addition, since multiple pieces of registration call data can be stored in the rewrite memory, by storing the same individual call data for all members of a particular group, it is possible to send one type of call data to a specific group. It becomes possible to communicate with everyone.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the basic configuration of a communication device according to an embodiment. In FIG. 1, the transmission system includes key gates 1-1 to 1-n1 transmitting device 2 and transmitting antenna 2h-1.
~2b-k. The keys 1-1 to 1-n are input devices for manually inputting a call code and message data to call the corresponding receiver and send the message data. Each of the key gates 1-1 to 1-n is installed at, for example, a pill or a predetermined n location in a factory.

The transmitting device 2 includes a transmission control section 2h, a reference clock circuit 2b, a memory 2c, and a BCH encoding circuit 2d.

FSK (Frequ@ncy 5hift Keyi
ng) Encoder 2e.

It includes a transmitter 2f and a distributor 2g. Transmission control section 2
a controls the transmitting operation in synchronization with the operation of the receiving system based on the time data supplied from the reference clock circuit 2b. When the transmission control unit 2a receives data from key dates 1-1 to 1-n, it outputs each data 'i' to the BCH encoding circuit 2d and converts it into BC)I code data (shortened 7-range code data). Make it convert. At this time, if there are many transmission requests, the transmission control unit 2a stores the input data in the temporary memory 2c. FSX encoder 2 is BC
The BCH code data output from the H encoding circuit 2d is
The data is converted into actual transmission data and output to the transmitter 2f.

The distributor 2g distributes each transmission data output from the transmitter 2f to each transmission antenna 2h-1 to 2h-k arranged corresponding to the keys 1-1 to 1-n. , for example, at a frequency of 600 Hz. In addition, FSX encoder 2 is twice that for 600Hz transmission data,
Transmission data representing digital data is created by combining signals of 1200 Hz and 2400 Hz, which are four times the frequency.

Next, the receiving system includes each receiving device and each receiving antenna 4-1 to 4- built in each of the electronic wristwatches 3-1 to 31.
Consists of m. Here, the circuits of the electronic wristwatches 3-1 to 3-m are constructed as shown in FIG. That is, each of the electronic wristwatches 3-1 to 3-m includes a receiving device 50 and a timepiece circuit 51. The receiving device 50 includes receivers 5, F
SK decoder 6, frame synchronization circuit 7, BCH code demodulation circuit 8, timing generation section 9, calling code detection circuit 10
, reception control section 1, memory control section 12, power cutoff circuit 1
3 and a memory 14. The receiver 5 receives transmission data (6
00btt/sea) to the FSX decoder 6
Output to. This transmission data is BCH encoded data in units of 16 bits in total, with 8 bits of redundant pits added to 8 bits of data.

The FSX decoder 6 decodes the data amplified and detected by the receiver 5 and outputs it to the frame synchronization circuit 7 and the BCH code demodulation circuit 8 while maintaining bit synchronization. The frame synchronization circuit 7 detects frame synchronization data from the data from the FSK decoder 6, provides the detection signal to the timing generation section 9, and generates timing signals F0 to F3 to be described later.
to occur. The BCH code demodulation circuit 8 performs BHC decoding on the data from the FSK decoder 6 in synchronization with the frame synchronization signal FO from the timing generation section 9, and divides the decoded data into data of every 8 pits and outputs the data. The call code detection circuit 1o discriminates between a group code and an individual code from the call code data output from the BCH code demodulation circuit 8, and transmits the discrimination result to the reception control unit 11 and the memory control unit 12.
Output to. Further, the call code detection circuit 10 outputs the determination result to the buzzer drive circuit 23 of the clock circuit 51 as an alarm signal AL. The memory control unit 12 controls writing of message data output from the BCH code demodulation circuit 8 into the memory 14. Further, the memory control section 12 transfers the message data to the reception control section 11. The message data stored in the memory 14 is output to the display drive circuit 19 of the clock circuit 51. Based on the determination result of the calling code detection circuit 10 and the contents of the message data from the memory control unit 12, the reception control unit 11
Controls the operation of the power cutoff circuit 13 of the receiver 5.

Next, the clock circuit 51 includes an oscillator 15, a frequency dividing circuit 16, a counting circuit 17, a display control circuit 18, and a display drive circuit 19.
, display section 20, alarm time memory 21, coincidence circuit 22
, a buzzer drive circuit 23 and a speaker 24. The frequency dividing circuit 16 divides the frequency of the reference frequency signal generated from the oscillator 15 and outputs the divided signal to the reception control section 11 and the counter circuit 17 . Further, the frequency dividing circuit 16 has a frequency of 1200Hz or 2400Hz.
The Hz branch signal is outputted to the FSX decoder 6, frame synchronization circuit 7, and timing generation section 9 as respective operation signals. The counting circuit 17 counts the 1-second signal from the frequency dividing circuit 16 to create clock data for the current time. The display control circuit 18 outputs the clock data from the counting circuit 12 and the alarm time data from the alarm time memory 21 to the display drive circuit 19 to display them on the display section 20. The alarm time memory 21 stores alarm time data that is set in advance to a switch (not shown). The coincidence circuit 22 transmits the buzzer drive signal to the buzzer drive circuit 23 when the time measurement data from the counting circuit 17 and the alarm time data from the alarm time memory 21 match.
Output to. The buzzer drive circuit 23 generates a buzzer sound (alarm sound) from the switch circuit 24 in response to the buzzer drive signal from the coincidence circuit 22 .

FIG. 3 is a block diagram showing a specific configuration of the reception control section 11 and its peripheral circuits. In FIG. 3, the call code detection circuit 10 detects a group code in the call code data output from the BCH code demodulation circuit 8 by a latch circuit 25.
The individual code is latched by the latch circuit 26.

U, child circuits 25 and 26 are AND circuits 52 and 5, respectively.
Timing signal Fl output from 3.

Latch operation is performed in synchronization with F2. When the contents of the latch circuit 25 match the group code stored in advance in the call code RAM (read/write memory) 31, the match circuit 28 outputs a match signal E1 to the first input terminal of the AND circuit 32. On the other hand, when the content of the latch circuit 26 and the individual code stored in the call code RAM 31 match, the match circuit 30 outputs a match signal E2 to the second input terminal of the AND circuit 32. RAM J 1 stores the calling code at the address given by the counter 54 and outputs the calling code stored at that address. The pointer register 55 sets the start address in the counter 54 when the RAM 3J is accessed.

The memory control unit 12 includes an AND circuit 27, a FRI, PFLOZO 33, and a call code writing circuit 60. The AND circuit 27 is dart-controlled in accordance with the input of the output signal Q of the flip-flora f33, and the BCH code demodulation circuit 8
Message data output from the memory 14 is transferred to the memory 14.

The output signal of the AND circuit 32 of the call code detection circuit 10 is applied to the set terminal of the free-lag flow f33. The call code writing circuit 60 is a BCH code demodulation circuit 8
A specific code instructing code registration is detected from the message data outputted from the message data, and an operation is performed to store the registration call code in the call code RAM j 1 according to the detection result.

As shown in FIG. 3, the reception control section 1 includes a subtraction circuit 29.
, a detection circuit 41, a message end detection circuit 45, a coincidence circuit 39, a 2760-decimal conversion circuit 36, a 60/binary conversion circuit 38, a digitizer, a defroc f42, and a quinary counter 43.

In the subtraction circuit 29, the input terminal AK is the call code RAM 3.
The registration call code from J is input, and the registration call code and the latched contents of the latch circuit 26 are subtracted. The 2/sexagesimal conversion circuit 36 converts the operation result of the subtraction circuit 29 from t-binary data to sexagesimal data,
Set the second/minute counter 31. As a result, if the counting circuit 17 has a lead or lag in units of seconds, as will be described later, the time can be corrected within the range of +7 seconds to -8 seconds.

The 60/bin conversion circuit 38 converts the second/minute data from the second/minute counter 37 from sexagenary to binary data and outputs it to the matching circuit 39. The match circuit 39 outputs a match signal to the first input terminal of the AND circuit 40 when the binary data from the 60/bin conversion circuit 38 and the call code from the call code %AM 31 match. The AND circuit 40 is
The output signal of the detection circuit 41 which detects that the frequency dividing circuit 16 has reached a predetermined value is input to the second input terminal, and the output signal is outputted to the set terminal of the Pflog 42. 7s! 70 and 42 output an output signal Q, which is a set signal, to the power cutoff circuit 13 and the quinary counter 43, execute on/off control of the power cutoff circuit 13, and drive the quinary counter 43. The 5-ary counter 43 counts the 1 second signal from the frequency dividing circuit 16, and when it counts up, outputs a signal to the digital drive circuit 23 shown in FIG. As a result, the data drive circuit 23 generates an alarm sound indicating that reception is not possible.

The message end detection circuit 45 includes the BCH code demodulation circuit 8
The end of the message data is detected from the end code added to the end of the message data output from. The message end detection circuit 45 outputs a detection signal to the reset terminal of the flip 70 knob 33 and the first input terminal of the OR circuit 44. The OR circuit 44 has a second input terminal inputted with the output signal of the AND circuit 35, and outputs the output signal to the reset terminal of the "f frog" 42.The AND circuit 35 has a first input terminal The timing signal F is inputted to the input terminal 2, and the output signal of the AND circuit 32 is inverted by the inverter 34 and inputted to the second input terminal.

The hour counter 46 of the counting circuit 17 is a circuit that counts the carry signal from the second/minute counter 37 and outputs time data. Incidentally, when the corresponding call code is transmitted, the frequency divider circuit 16 is forcibly set to about 9/100 seconds (0.09 seconds) by the timing signal FO included in the call code. The time is corrected in synchronization with the reference clock circuit 2bK.

As shown in FIG. 4, the power cutoff circuit 13 includes a resistor R and a transistor TR, and is configured such that the output signal of the flip 70 tube 42 is supplied to the pace of the transistor TH via the resistor R. The receiver 5 is connected to the top of the transistor TR via grounding.

The supply of the power supply voltage V to the receiver 5 is controlled in accordance with the on/off operation of the transistor TR.

In the communication system configured as described above, the operation of this embodiment will be explained with reference to FIG.

First, the basic operation of this embodiment will be explained. For example, when contacting a certain user who owns an electronic wristwatch 3-1,
The user on the contacting side inputs the corresponding call code from key 1-1, and further inputs message data (for example, "Ude A device"). Here, the call code data is the IC when the receiving system is divided into predetermined groups.
(Consists of a group code (16 bits, G) indicating a group of - and an individual code (16 bits) in each group code.The input data from the key 1-1 is the time data of the reference clock circuit 2b. When becomes 00 seconds, the transmission control unit 2a
and is transferred to the BCH encoding circuit 2d. At this time, if communication is in a busy state, the input data will be temporarily stored in the memory 2c and then transmitted.

The input data is converted to B by the KBCH encoding circuit 2d as described above.
After being converted to CH encoded data, FSK encoder 2
・Given to. FSX encoder 2@ is 600H
z (600 bits/see) transmission data is created and transferred to the distributor 2g via the transmitter 2f. The transmission data is transmitted by the distributor 2g to the transmission antennas 2h-1 to ?
It is transmitted from h-k and received by receiving antennas 4-1 to 41 of electronic wristwatches 3-1 to 3-m.

Received signals from the receiving antennas 4-1 to 41 are input to the receiver 5 of each receiving device 50 shown in FIG. 2, amplified and detected, and then provided to the FSK decoder 6. Here, as shown in FIG. 6, for example, the receiving system consists of 16 groups, and each receiver 5 performs a receiving operation for 1 second at a cycle of 16 seconds.

That is, the reception system obtains a coincidence signal from the coincidence circuit 39 when the value of the seconds/minutes counter 37 matches its own group code.
When a detection output is obtained from the detection circuit 41 while this coincidence signal is being output, the flip-flop 42 is set by the AND circuit 40. For example, if the receiving system is in group 0, the value of the seconds counter is "0 seconds", "16 seconds", or "32 seconds".
When , that is, when the lower 4 bits are roooOJ, a match signal is output from the match circuit 39. Therefore, the receiver 5 detects that the output signal Q of the 7-lip floppy disk 42 shown in FIG.
During the HJ level period, the transistor T of the power cutoff circuit 13
When R is turned on and K is supplied with the stain source voltage V, a reception operation is performed.

The received data received by the receiver 5 is sent to the FSK decoder 6.
After being decoded, the signal is transferred to the frame synchronization circuit 7 and the BCH code demodulation circuit 8 as serial data synchronized with the division signal from the frequency division circuit 16.

By the way, the received data is specifically structured as shown in FIG. That is, the received data is for each group (group 0 to
Group 15) Both have the same configuration, meaningless pits for 18 bits from the beginning, pit synchronization data for 22 bits, pit synchronization data for 8 bits, frame synchronization data for 8 bits, and call code data for 32 bits, It consists of 16 bits of free data and message data.

The frame synchronization circuit 7 detects frame synchronization data from the received data (serial data), and causes the timing generation section 9 to generate a timing signal F (FO-Fj). Here, the timing signal FO is synchronized with the last pit of the frame synchronization data, and the timing signal F1 is a signal generated every 16 bits from this signal FO.

Further, timing signal F2 is a signal generated at the 16th bit from signal FO.

After executing the BCH decoding process, the BCH code demodulation circuit 8 transfers the output data to the calling code detection circuit 10, reception control section 11, and memory control section 12.

In the call code detection circuit 10, the call code RAM 31
A comparison is made between the registration call codes (group code and individual code P) stored in advance in the register and the call code data of the received data. If the comparison results do not match, the AND circuit 32 in FIG.
33 both remain in a reset state. As a result, the power cutoff circuit 13 shown in FIG. 4 is not turned on, and the supply of power supply voltage to the receiver 5 remains stopped. Therefore, writing of message data to the memory 14 of FIG. 3 is prohibited. On the other hand, if the comparison results match,
That is, when your own electronic wristwatch is called, AND circuit 3
2, the coincidence signal is sent to the reception control section 11 and the memory control section 12.
Output to. Accordingly, υ, 7 of the memory control unit 12,
The differential 0 output 33 is set, and the message data from the BCH code demodulation circuit 8 is written into the memory 14 through the AND circuit 27f.

In addition, the reception control unit 11 performs the following operations.
The buzzer drive circuit 23 shown in FIG. 2 drives the speaker 2.
An alarm sound is generated from 4, and the message data in the shift memory 14 is displayed on the display section 20 by the operation of the display drive circuit 19.

That is, when the second/minute counter 37 of the counting circuit 17 shown in FIG. Matching circuit 3 after being converted to binary data
Output to 9. On the other hand, the matching circuit 39 is given a group code corresponding to, for example, the 0 group from the call code RAM 31. As a result, the matching circuit 39 outputs the group code and the second
The rHJ data as shown in Figure 6 is detected.
The level matching signal is output to one input terminal of the AND circuit 40 of the reception control section 11. Furthermore, the detection circuit 41
When the frequency division data from the frequency dividing circuit 16 becomes data corresponding to 37100 seconds, a detection signal of the "■" level is outputted to one input terminal of the AND circuit 40. That is, when the time elapse detection circuit 4 finishes receiving meaningless data for 18 pits from the beginning of the transmission data of group 0, it detects this and outputs the detection signal to the AND circuit 40. At this time,
The frequency dividing circuit 16 receives a timing signal F every 16 seconds.
O is forcibly preset to 3/100 seconds so as to match the time of the reference clock circuit 2b in FIG. 1, so corrections of seconds or less are made.

Furthermore, a signal at the rHJ level is outputted from the coincidence detection circuit 39 to the other input terminal of the AND circuit 40. As a result, an output signal of the rHJ level is outputted from the AND circuit 40, the flip-flop 42 enters a set state, and a set output signal Q is outputted to the power cutoff circuit 13.

Further, the set output signal Q is output to the 5-ary counter 43, and this 5-ary counter 43 starts counting operation.

Furthermore, after about 6/100 seconds, when the frame synchronization data is detected by the frame synchronization circuit 7 as described above, the timing signal FO as shown in FIG. 6 is generated from the timing generation section 9.

The upper bit (group code) of the calling code received at the 16th bit after this signal FO is output is latched by the latch circuit 25 in synchronization with the timing signal F. Furthermore, after 16 bits, the lower bits (individual code) of the calling code are the timing signals F, ? latch circuit 2 in synchronization with
At 6, I get hit. The data latched in each latch circuit 25, 26 is compared with the call code from the call code RAM j 1 in a match circuit 28, 30, respectively. If the comparison results match, an rHJ level match signal is output from the AND circuit 32, and the 7-rig flop 33 is set.

As a result, message data for each 16 bits is written into the memory 14 through the AND circuit 27. Further, from the time when the AND circuit 32 outputs the match signal, the carry signal of the quinary counter 43 is transferred to the buzzer drive circuit 23, and an alarm sound is generated from the speaker 24. Note that the subtraction circuit 47 of the reception control section 11 includes a latch circuit 26.
The individual code from the call code RAM 31 and the individual code from the call code RAM 31 are input, and the result of subtraction is output to the 2/60 base conversion circuit 36.

Therefore, if the time is ahead or behind in the 0 group's clock, when another individual call code is received after the output of the timing signal FO, it is not the reception timing of the 0 group, so the number of seconds will be calculated according to the difference. The second/minute counter 37 is corrected by the following amount.

As a result, the next 0 group will be received correctly at the reception timing.

By the way, in the above-mentioned call code detection operation,
For example, as shown in FIG. 5, it is assumed that the RAM 31 stores n+1 2-byte registration call codes from addresses 0 to 2n+1. At this time,
A value n is set in the pointer register 55. When the value n of the pointer register 55 is set to the counter 54, the address A is stored in the RAM 31 from the counter 54.
1 to A1 are given. At the same time, the address AOK of the RAM 31 is given the timing signal F from the timing generator 9 of FIG. 2 through the OR circuit 58f. This is 4! l) The n + 1st registration call code ζ stored at addresses 2n and 2n+1 of the RAM 31 is read out and output to the matching circuit 28 .

Next, the counter 54 is counted down by 1, and the RAM
The n-th individual ;- codes stored at addresses 2n-2 and 2n-1 of 31 are read out and output to the matching circuit 30. In each match circuit 23.30, a comparison is performed between the respective registration call code and each call code latched in the latch circuit 25.26. This comparison operation is performed between the call code at each address in the RAM 31 and each call code loaded into the latch circuits 25 and 26 until the counter 54 becomes 0. When the match signals El and E2 are output from each match circuit 28.30, the AND circuit 32 outputs r.
A HJ level signal is output. Accordingly, the flip-flop 33 is set, and the message data is stored in the memory 14 from the AND circuit 27 as described above.

Next, in the operation of registering the registration call code to the RAM 32, the message data sent in advance includes a 1-byte specific code for instructing code registration and the registration call code. Assume that such message data is received by the receiving device 50 as described above and is applied to the calling code detection circuit 10 shown in FIG. When the call code writing circuit 60 detects the specific call rt' from the message data from the BCH code demodulation circuit 8, it performs a registration operation of a call code for registration. That is, the call code writing circuit 60 increments the value of the pointer register 55 and sets this value in the counter 54. At this time, the call code writing circuit 6θ is the OR circuit 57°5.
6 to output an enable signal and a set signal to the counter 54. Further, a write signal W and an enable signal are output to the call code RAM 31. Under the control of this call code loading circuit 60, RAM 3
1 has 2(n+1).

At address 2(n+1)+1, the two-note registration call code following the specific code is stored.

Next, when erasing the calling code registered in the RAM 31, the message data sent in advance includes the specific call r instructing code erasure and its registered calling code, as described above. Call code writing circuit 60
When detecting a specific code instructing erasure from the received message data, the counter 54 outputs a registration call code of the address set from the t-RAM 31 while counting down. RAM
The 2-byte registration call code output from 31 and the 2-byte call code following the specific code are sent to matching circuit 2.
8 for comparison. If the comparison result is a match, the matched registered call code in the RAM 31 is erased.

In this case, the call code writing circuit 60 decrements the value of the pointer register 55 so that it always points to the largest address where the call code is stored.

Here, the above-described call code registration and deletion operations may be performed by inputting from an input key device connected to the receiving device 50 instead of the method using transmitted message data. Even in this case, the nine data input from the input key device are outputted to the data bus in the call code detection circuit 10 through the call code convolution circuit 60, and registration of the call code in the RAM 31 or deletion of the registered call code is executed. will be done.

In this way, the receiving device 50 built into the electronic wristwatch
In a communication system using R in the receiving device 50,
It becomes possible to easily register, change, and delete a call code in AM j 1.

Therefore, even if the user of the receiving device 50 is changed or a new user joins, by changing or adding the corresponding call code, it is possible to easily communicate with the user who has changed or newly joined. Furthermore, by registering a plurality of call codes in the RAM 31 of each receiving device 50, communication (
Calls and sending messages) can be made. For example, if multiple users in a specific group register the same call code, it becomes possible to communicate with multiple users at once by transmitting the same call code. Therefore, when communicating with a specific group of users, it is not necessary to transmit the respective calling codes P, thereby simplifying the communication operation.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a communication system using a receiving device built into an electronic wristwatch or the like, it is possible to easily change, add, or delete the registered call code of the receiving device.

For Party B, for users who have changed or newly joined,
It becomes possible to start communication easily. Furthermore, by registering the same call code in each receiving device of one specific group, it becomes possible to easily communicate with a plurality of users of the specific group simply by transmitting the call code.

Therefore, flexible and highly efficient communication can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a transmitter according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a receiver according to the embodiment, and FIG. 3 is a diagram showing the configuration of a receiver according to the embodiment. FIG. 4 is a block diagram showing the configuration of the power cutoff circuit of the same embodiment, and FIG. 5 is an example of the memory contents of the call code RAM of the same embodiment. Figure 6 showing
The figure is a configuration diagram of received data and a timing chart for explaining the operating system of the same embodiment. 1-1 to 1-n...keyboard, 2...transmission device,
3-1 to 3-m...electronic wristwatch, 5...receiver, 1
0... Calling code detection circuit, 11... Reception control unit,
13...Power cutoff circuit, 3...Call code RAM
. 50... Receiving device, 60... Calling code writing circuit.

Claims (3)

[Claims] (1) A transmitting device that transmits a signal consisting of individual call data and message data by radio waves, a receiving means, and a storage means for individual call data, and the individual call data transmitted from the transmitting device is stored in the storage means. A communication device comprising a receiving device having means for notifying the message data transmitted from the transmitting device when the message data matches the individual calling data of the receiving device, and a storage device for storing the individual calling data of the receiving device. A communication device characterized in that the individual call data is configured to be rewritable. (2) The storage means is capable of storing a plurality of individual call data, and the individual call data transmitted from the transmission means is configured to perform a match detection operation with the plurality of individual call data. A communication device according to claim 1. (3) The communication device according to claim 1, wherein the storage means has means for storing data from the transmitting device as individual call data.