JPS61240722A - Communication equipment - Google Patents

Abstract

PURPOSE:To inform the contents of a message to be transmitted, to a user at a set time determined in advance, by transmitting a message data containing an alarm time data for indicating a notice time in advance. CONSTITUTION:In a communication system which has utilized a receiving device 50 contained in an electronic wrist watch, when a message data containing an alarm time data in advance is transmitted from a transmitting side, this message data is stored in a memory 14. When the alarm time data which has been stored in the memory 14 coincides with a time data of a clock circuit, an alarm sound is generated, and the contents of the message concerned are displayed on an indicator 20. Accordingly, a user is called by the alarm sound at the time indicated by the alarm time data, and the necessary message contents can be informed by a display or a voice. Also, plural memory circuits can be provided in the memory 14, and plural message data for designating the notice time by the alarm time data can be stored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a small communication device in which a receiving device is built into, for example, an electronic wristwatch.

[Prior art and its problems]

Is it traditionally well known in recent years? It has been considered to incorporate the Keratopel system into portable devices such as electronic wristwatches and small electronic calculators. In such a system, a receiving device is built into an electronic wristwatch, etc., and when the receiving device receives a corresponding call code sent from the transmitting device, an alarm sound is generated and each individual wearing the wristwatch receives a call. will be done. Further, a system has been considered that has a function of displaying the transmitted message data on the display section of the electronic wristwatch when the message data is transmitted together with the calling code from the transmitting device.

By the way, in such a system as described above, when a user receives message data such as a notification of a meeting that is required after a predetermined period of time has elapsed from the time of transmission, the user may forget the contents of the message data after the elapse of time. Therefore, message data can be sent when necessary.

It is often difficult for the sending side to manage the sending time.

[Purpose of the invention]

An object of the present invention is to provide a communication device that can notify a user of the contents of a message to be sent at a predetermined set time in a communication system using a built-in receiving device such as an electronic wristwatch.

[Key points of the invention]

The present invention provides a communication device in which the receiving device is built in, for example, an electronic wristwatch, and includes a detection means for detecting message data including alarm time data transmitted from the transmitting device. Depending on the detection result of the detection means, message data including alarm time data is stored in the memory means. Further, the coincidence detection means detects coincidence between the time data from the clock means and the alarm time data stored in the memory means. Based on the coincidence detection by the coincidence detection means, the control means executes an alarm process of the reception means, and the message data stored in the memory means is displayed on the display section of the reception means.

With the communication device having such a configuration, it is possible to display the content of the corresponding message on the display section of the receiving device and notify the user at a time corresponding to the alarm time data.

[Practice of the invention, examples]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the basic configuration of a communication device according to an embodiment. In FIG. 1, the transmission system includes key nodes 1-1 to 1-n.

It consists of a transmitting device 2 and transmitting antennas 2h-1 to 2h-k. The keys 1-1 to 1-n are input devices for manually inputting a calling code and message data to call the corresponding receiver and send the message data. Each of the keyboards 1-1 to 7-n is installed at, for example, a pill or a predetermined n location in a factory.

The transmitting device 2 includes a transmission control section 2&, a reference clock circuit 2b, a memory 2c, and a BCH encoding circuit Jd.

FSK (Frequ@ney 5hift K@yi
ng) It includes an encoder 26, a transmitter 2f, and a distributor 2g. The transmission control unit 2a controls the transmission operation in synchronization with the operation of the reception system based on the time data supplied from the reference clock circuit 2b. The transmission control unit 2s1 is
When the key inputs data from keys 1-1 to 1-n,
Each data is output to the BCH encoding circuit 2d and converted into BCH code data (shortened flange code data). At this time, if there are many transmission requests, the transmission control unit 2& temporarily stores the input data in the memory 2C. The FSK encoder 2 converts the BCH code data output from the BCH encoding circuit 2d into actual reception data and outputs it to the transmitter 2f. The distributor 2g sends each transmission data output from the transmitter 2f to the keyboards 1-1 to J-n.
Each transmitting antenna 2h-1 to 2h arranged corresponding to
-k, and transmit at a frequency of, for example, 600 Hz. Note that the FSK encoder 2 uses 1200 Hz, which is twice or four times the frequency of 600 Hz transmission data.
Hz and 2400 Hz signals are combined to create transmission data representing r-zotal data.

Next, the receiving system includes each receiving device built in each of the electronic wristwatches 3-1 to 3-m and each receiving device 7yf-)-4-1.
Consisting of ~4-m. Here, electronic wristwatches 3-1 to 3-m
The circuit is constructed as shown in FIG. That is,
The electronic wristwatches 3-1 to 3-m each include a receiving device 50 and a clock circuit 51. The receiving device 50 includes a receiver 5, an FSK decoder 6, a frame synchronization circuit 7, a BCH code demodulation circuit 8, a timing generation section 9, a calling code detection circuit 10, a reception control section 11, a memory control section 12, a power cutoff circuit 13, and It is equipped with a memory 14. The receiver 5 outputs the transmission data (transmitted at 600 blt/sea) received by the receiving antennas 4 (4-1 to 4-m) to the F'SK decoder C. This transmission data is BCH encoded data, and is data in units of a total of 16 pits, in which 8 redundant bits are added to 8 pit data.

The FSK decoder 6 decodes the data amplified and detected by the receiver 5 and outputs it to the frame synchronization circuit 7 and the BCH code demodulation circuit 8 while maintaining pit synchronization. The frame synchronization circuit 1 detects frame synchronization data from the data from the FSK decoder 6 and provides the detection signal to the timing generation section 9 to generate timing signals FO to F3. The BCH code demodulation circuit 8 includes a timing generation section 9
The data from the F'SK decoder 6 is t-BHC decoded in synchronization with the frame synchronization signal F0, and the decoded data is divided into data of every 8 bits and output. The calling code detection circuit 10 discriminates between a group code and an individual code from the calling code data output from the BCf (code demodulation circuit 8), and transmits the discrimination result to a reception control unit 11 and a memory control unit 12.
Output to. Further, the call code detection circuit lθ outputs the determination result to the data drive circuit 23 of the clock circuit 51 as an alarm signal AL. The memory control unit 12 controls writing of message data output from the BCI (code demodulation circuit 8) to the memory 14.Finally, the memory control unit 12 transfers the message data to the reception control unit 11.Memory The message data stored in 14 is output to the display drive circuit 19 of the clock circuit 51.The reception control section 11, based on the determination result of the call code detection circuit 100 and the contents of the message data from the memory control section 12, Controls the operation of the power cutoff circuit 13 of the receiver 5.

Next, the clock circuit 51 includes an oscillator 15, a frequency dividing circuit 16, a counting circuit 17, a display control circuit 18, and a display drive circuit 19.
, a display section 20, and a speaker 24. Frequency divider circuit 1
6 divides the frequency of the reference frequency signal generated from the oscillator IS and outputs it to the reception control section 11 and the counting circuit 11. Moreover, the frequency dividing circuit 16 is 1200 HS or 2400 H
The branch signal of z is outputted to the FSK 7' coder 6, the frame synchronization circuit 7, and the timing generation section 9 as respective operation signals. The counting circuit 17 counts the 1-second signal from the frequency dividing circuit 16 to create clock data for the current time. The display control circuit I8 outputs the clock data from the counting circuit 17 to the display drive circuit 19, and displays it on the display section 20. .

FIG. 3 is a block diagram showing a specific configuration of the reception control section 11 and its peripheral circuits. In FIG. 3, the call code detection circuit 10 detects a group code in the call code data output from the BCH code demodulation circuit 8 by a latch circuit 25.
The individual code is latched by the latch circuit 26.

The latch circuits 25 and 26 are AND circuits 52 and 5, respectively.
Timing signal FJ output from 3.

Latch operation is performed in synchronization with F2. When the content of the latch circuit 25 matches the detailed code stored in the call code ROM (read only memory) 31, the matching circuit 2B performs a matching circuit 2B.
The coincidence signal E1 is output to the first input terminal of the AND circuit 32. On the other hand, the coincidence circuit 30 uses the contents of the latch circuit 26 and the individual code P stored in advance in the call code ROM 3J.
If they match, a match signal T22 is output to the second input terminal of the AND circuit 32.

The memory control unit 12 receives the message data from the BCH code demodulation circuit 8, the output signal of the AND circuit 32, and the output signal of the message end detection circuit 45, and controls the memory 1.
Controls the operations of 4.

The memory 14 controls the BCH according to the control of the memory control unit 12.
Message data from the code demodulation circuit 8 is stored.

As shown in FIG. 3, the reception control section 11 includes a subtraction circuit 29.
, a detection circuit 41, a message end detection circuit 45, a coincidence circuit 39, a 2/sexagesimal conversion circuit 36, a 60/binary conversion circuit 38, a flip-flop f4x, and a quinary counter 43.

The subtraction circuit 29 has a call code ROM 3 at the input terminal B.
A call code from 1 is input, and a subtraction operation is performed between this call code and the contents latched by the latch circuit 25. 2/
The sexagesimal conversion circuit 36 converts the calculation result of the subtraction circuit 29 from binary data to sexagesimal data, and converts the calculation result of the subtraction circuit 29 from binary data to sexagesimal data and converts the result to the second/minute counter 3.
Set to 1. As a result, electronic wristwatches 3-1 to 3-
If m has a lead or lag in seconds, +7 seconds to -8
It is possible to adjust the time within seconds.

The 60/bin conversion circuit 38 converts the second/minute data from the 97 minute counter 37 from sexagenary to binary data and outputs it to the matching circuit 39. When the binary data from the 60/bin conversion circuit 38 and the call code from the call code ROM 31 match, the match circuit 39 outputs a match signal to the first input terminal of the AND circuit 40 . The AND circuit 40 is
The output signal of the time elapse detection circuit 41 is input to the second input terminal, and the output signal is sent to the flip-flop! Output to the 420 set terminal. The free-lag frog 42 outputs an output signal Qt to the power cutoff circuit 13 and the quinary counter 43, executes on/off control of the power cutoff circuit 130, and drives the quinary counter 43t. The quinary counter 43 counts the one second signal from the frequency divider circuit 16, and outputs a signal AL to the jib drive circuit 23 in FIG.

The message end detection circuit 45 includes the BCH code demodulation circuit 8
The end of the Metsu-1-2 data is detected from the end code added to the end of the message data output from. The message end detection circuit 45 outputs a detection signal to the memory control section 12 and the first input terminal of the OR circuit 44.

The OR circuit 44 receives the output signal of the AND circuit 35 at its second input terminal, and outputs the output signal to the reset terminal of the flip-flop f42. The AND circuit 35 is
The timing signal F3 is input to the first input terminal, and the output signal of the AND circuit 32 is inverted by the inverter 34 and input to the second input terminal.

The hour counter 46 of the counting circuit 12 is 1? from the 97 minute counter 31? This is a circuit that counts the signals and outputs time data. Incidentally, when the corresponding call code is transmitted, the frequency dividing circuit 16 responds to the timing signal FO included in the call code by about 9/100 seconds (0.09 seconds).
seconds), and the time is corrected in synchronization with the reference clock circuit 2b.

As shown in FIG. 4, the power cutoff circuit 13 includes a resistor R and a transistor TR, and is configured such that the output signal of the flip-flop f42 is supplied to the transistor TH via the resistor R. The transistor TR has a common emitter and a receiver 5 connected to its collector.

The supply of the power supply voltage V to the receiver 5 is controlled in accordance with the on/off operation of the transistor TH.

Here, the memory control section 12 and the memory 14 are configured as shown in FIG. That is, the memory control unit 12 includes the AND circuits 46, 54, 56, the match circuit 47, the flipflop! 52, 55, alarm memory 53 and 3
It is equipped with a 1-column counter/re57. The AND circuit 46 converts the received data from the BCH code demodulation circuit 168 inputted into a first input terminal into a coincidence circuit 47 controlled by the output signal of the frizzo 70f52 inputted into a second input terminal.
Output to. In the free-lag frog 52, a match signal from the match circuit 32 is outputted to a set terminal S, and a detection signal from a message end detection circuit is outputted to a reset terminal R. The matching circuit 41 detects a match between the alarm set character stored in advance in the alarm memory 53 and the alarm set character in the received data.

The coincidence signal from the coincidence circuit 47 is sent to the first one of the AND circuit 54.
output to the input terminal. The second input terminal of the AND circuit 54 is supplied with the output signal of the free-lag frog 52 . When the output signal of the AND circuit 54 is supplied to the set terminal, the free-lag frog 55 outputs a set output signal to the first input terminal of the AND circuit 56 . The AND circuit 56 is controlled by the set output signal outputted to the first input terminal, and outputs a frame clock signal t--vesical clock C as the frame clock signal t--the bladder-inclusive clock C, which is supplied to the second input terminal.
7 and memory 14. The 31-decimal counter 57 is
After counting 32 pulses of the read clock ct-, the set signal S is output to the reset terminal of the flip-flop f55 and the memory 14.

The memory 14 includes a plurality of memory circuits 6oa to 60c and an OR circuit 61. The memory circuit 60& includes a shift register 62. Matching circuit 63, free lag frog 64,
It includes AND circuits 65 to 68 and an AND circuit 69. The shift register 62 stores message data from the BCH code demodulation circuit 8 in synchronization with the clock signal output from the AND circuit 62. The AND circuit 62 has a first input terminal supplied with the read clock C from the method control section 12, and a second input terminal supplied with the output value number set by the flip-flop 640. The free-lag frog 64 has a set input terminal supplied with the coincidence signal of the coincidence circuit 63, and a reset terminal supplied with the output signal of the AND circuit 65. The AND circuit 65 has a first input terminal supplied with the set signal S from the memory control unit 12, and a second input terminal supplied with the set output signal of the free-lag frog 64. Here, the read clock C and the set signal S are outputted to the other memory circuit 60b through the AND circuits 6B and 66f.

On the other hand, the message data stored in the shift register 62 is output to a matching circuit 63 and an AND circuit 69, respectively. The coincidence circuit 63 performs a coincidence detection operation between the data from the shift register 62 and the time data from the counting circuit 17. The AND circuit 69 outputs the data from the shift register 62 to the display drive circuit 19 in response to the match signal from the match circuit 63. The coincidence signal from the coincidence circuit 63 is output to the speaker 24 through the OR circuit 6. Note that the other memory circuits 60b and 60c are also the same as the memory circuit 6.
It has the same configuration as 0h.

In the communication device configured as described above, the operation of this embodiment will be explained with reference to FIG. First, the basic operation of this embodiment will be explained. For example, when contacting a certain user who owns an electronic wristwatch s-i, the user making the contact inputs the corresponding call code from the keymate 1-1, and Furthermore, message data (for example, "User A iC please place") is input. Here, the call code data consists of a group code (16 pits) that indicates the group when the receiving system is divided into predetermined groups, and an individual code (16 bits) within each group. The input r-day from the key R-doard 1-1 indicates that the time data of the reference clock circuit 2b is o.
.

BCT(
It is transferred to the encoding circuit 2d. At this time, if the communication is in the Pinoy state, the input data will be transmitted after being temporarily stored in the memory 2c.

The input data is processed by the BCH encoding circuit 2d as described above.
After being converted to CH encoded data, FSK encoder 2
given to e. FSK encoder 2e is 600H
z (600 bits/5ee) is created and transferred to the distributor 2g via the transmitter 2ft. Transmission data is sent to transmission antennas 2h-1 to 2h-2 by a distributor 2g.
It is transmitted from h-k and received by receiving antennas 4-1 to 4-mK of electronic wristwatches 3-1 to 3-m.

Received signals from receiving antennas 4-1 to (-m) are input to the receiver 5 of each receiving device 50 shown in FIG. 2, amplified and detected, and then provided to the decoder 6 at F8.Here,
As shown in FIG. 6, for example, the receiving system consists of 16 groups,
Each receiver 5 performs a receiving operation for 1 second at a cycle of 16 seconds. At this time, the receiver 5 performs the receiving operation by being supplied with the power supply voltage V by turning on the power cutoff circuit 130 Toranozostar TR during the period when the output signal Q of the free-lag frog 42 shown in FIG. 3 is at the rHJ level. Do the following. receiver 5
After the received data is decoded by the FSX decoder 6, it is synchronized with the division signal from the frequency divider circuit 16 and sent to the frame synchronization circuit 7 and the BC as nine serial 1% data.
The received data is transferred to the H code demodulation circuit 8. Specifically, the received data is structured as shown in FIG. The received data has the same configuration for each group (groups 0 to 15), including 18 pits from the beginning of the data, pit synchronization data for 22 pits, frame synchronization data for 8 bits, and call codes for 32 pits. data, free data for 13 pits, alarm set character for 8 bits, and message data. The message data includes alarm time data.

The frame synchronization circuit 1 detects frame synchronization data from the received data (serial data), and causes the timing generation section 9 to generate timing signals FO-FJ. Here, the timing signal FO is synchronized with the last pit of the frame synchronization data, and the timing signal F1 is a signal generated every 16 pits from this signal FO. Further, the timing signal F2 is a signal generated at the 16th bit from the signal F0, and the timing signal F3 is a signal generated at the 32nd bit from the signal FO. After executing the BCH decoding process, the BCH code demodulation circuit 8 transfers the output data to the calling code detection circuit 10, reception control section 11, and memory control section 12.

In the call code detection circuit 10, the call code 9ROM 3
A comparison is made between the call codes (group code and individual code) stored in advance in 1 and the call code data of the received data. If the comparison results do not match, an "L" level signal is output from the AND circuit 32 in FIG.
2.52 are both reset. This allows the fourth
The power cutoff circuit 13 shown in the figure is turned off, and the supply of power supply voltage to the receiver 5 is stopped. Furthermore, writing of message data to the memory 14 in FIG. 3 is prohibited. On the other hand, if the comparison results match, that is, if the own electronic wristwatch is called, a match signal is output from the AND circuit 32 to the reception control section 11 and the memory control section 12. As a result, the 7-rig flag 52 of the memory control section 12 becomes set, and the message data from the BCf (code demodulation circuit 8) is supplied to the coincidence circuit 51 through the AND circuit 50.

In addition, the reception control unit 11 performs the following operations.
As shown in FIG. 2, the nap drive circuit 23 drives the speaker 2.
An alarm sound is generated from 4, and the message data in the shift memory 14 is displayed on the display section 20 by the operation of the display drive circuit 19.

That is, the 97 minute counter 31 of the counting circuit 11 shown in FIG.
8, the clock data is converted from this 60/binary conversion circuit 38 into binary data and then sent to the matching circuit 39.
Output to.

On the other hand, the matching circuit 39 is supplied with a group code corresponding to, for example, O detail from the call code ROM 31. As a result, the matching circuit 39 detects matching between the group code r and the binary data, and sends an "H" level matching signal as shown in FIG. Output to the terminal.

Furthermore, when the frequency division data from the frequency division circuit 16 becomes data corresponding to 3/100 seconds, the time elapse detection circuit 41 detects that
The rHJ level detection signal is output to one input terminal of the AND circuit 40. That is, when the time elapse detection circuit 41 finishes receiving the 18 pits worth of invalid data from the beginning of the transmission data of group 0, it detects this and outputs the detection signal to the AND circuit 40 . At this time, the frequency dividing circuit 16
Every second, the timing signal Fo is used to match the time of the reference clock circuit 2b in FIG. 1, and corrections are made to the second or less. Further, an “H” level signal is output from the coincidence detection circuit 39 to the other input terminal of the AND circuit 40. As a result, an "H" level output signal is output from the AND circuit 40, the free lag frog 42 is set, and the sector output signal Qt-power cutoff circuit 13
Output to. Also, the set output signal Q is output from the quinary counter 4.
3, and this quinary counter 43 starts counting operation t-.

Furthermore, after about 6/100 seconds, when frame synchronization data is detected by the 7L'-me synchronization circuit 7 as described above,
A timing signal FO as shown in FIG. 6 is generated from the timing generator 9.

The upper bit (group code) of the calling code received at the 16th bit after this signal FO is output is latched by the latch circuit 25 in synchronization with the timing signal F. Furthermore, after 16 bits, the lower bits (individual code) of the calling code are transferred to the latch circuit 26 in synchronization with the timing signal F2.
latched to. The data latched in each latch circuit 25, 26 is compared with the call code from the call code ROM 31 in match circuits 28, 30, respectively. If the comparison results match, an "H" level match signal is output from the AND circuit 32, and the free lag frog 52 is set. As a result, an 8-pit alarm set character is outputted to the matching circuit 51 through the AND circuit 50. Further, from the time when the match signal is output from the AND circuit 32, when the carry signal AL of the quinary counter 3 is transferred to the data drive circuit 23, the data drive circuit 23
becomes operational. Note that the subtraction circuit 29 of the reception control section 11
The group code and call code R from the latch circuit 25 are
The group code from OM J J is input, and the subtraction result is output to the 2/60 base conversion circuit 36. Therefore, if the time is ahead or behind on the 0 group's clock, when the call code of another group is received after the timing signal FO is output, the reception timing is not the 0 group's, so the number of seconds corresponding to the difference is calculated. The second/minute counter 31 is corrected by the following amount.

As a result, the next 0 group is correctly received at the reception timing.

By the way, in the above-mentioned call code detection operation,
Assume that received data is output from the AND circuit 46 of the memory control section 12 shown in FIG. 5 to the matching circuit 41. The matching circuit 47 executes matching detection between the alarm set character of the received data and the alarm set character stored in advance in the alarm memory 53. As a result, when a coincidence signal is output from the coincidence circuit 47 to the AND circuit 54,
The free lug frog 55 is set. As a result, the read clock C is applied from the AND circuit 56 to the AND circuit 67 of the memory 14, and the read clock C is output from the AND circuit 67 to the shift register 62. The read clock C is output until the set signal S is output from the 31-decimal counter 51, that is, 32.multidot.

Message data from the BCH code demodulation circuit 8 is stored in the shift register 62 in synchronization with the read clock C from the 7789 circuit 67.

When this storage is completed, the free lag frog 64 is in a reset state. The message data stored in the shift register 62 includes alarm time data in advance. This alarm time data is data that indicates the time at which the contents of the necessary message will be notified.

The alarm time data is output to the coincidence circuit 63. In the coincidence circuit 63, coincidence detection between the alarm time data and the time data from the counting circuit 17 is executed. As a result of this detection operation, when a match signal is output from the match circuit 63, this match signal is output to the pad drive circuit 23 through the OR circuit 61t-. As a result, an alarm sound is generated from the speaker 24 shown in FIG.

Further, the coincidence signal from the coincidence circuit 63 is output to the flip-flop f64, and the flip-flop 64 is set. As a result, the next message data is stored in the shift register 62. Here, frigfloc f64
In the reset state, the set signal S and the read clock C are supplied to the next stage memory circuit 60b by the operation of the AND circuits 66 and 611. On the other hand, in response to the match signal from the match circuit 63, the AND circuit 69 transfers the message data (data indicating message content other than the alarm time data) stored in the shift register 62 to the display drive circuit 19 in FIG. Forward. As a result, the content of the message is displayed on the display section 20 at the same time as the alarm sound is generated from the speaker 24.

In this way, the receiving device 50 built into the electronic wristwatch
In a communication system using , when message data including alarm time data is transmitted from the sending side in advance, this message data is stored in the memory 14 . When the alarm time data stored in the memory 14 matches the time data of the clock circuit, an alarm sound is generated and the contents of the corresponding message are displayed. Therefore, at the time indicated by the alarm time data, the user can be called with an alarm sound and the necessary message contents can be displayed and notified. Note that in this case, it is also possible to notify by voice instead of display. Further, by providing a plurality of memory circuits 601 to 60e in the memory 14, it is possible to store a plurality of message data specifying a notification time based on alarm time data.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a communication system using a receiving device built into an electronic wristwatch or the like, a message to be sent is transmitted by transmitting message data including alarm time data indicating a notification time in advance. The content can be notified to the user at a predetermined set time.

Therefore, even if the user forgets the contents of the message, he or she can reliably know all the necessary contents of the message at the necessary time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a transmitting device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a receiving device according to the same embodiment, and FIG. FIG. 4 is a block diagram showing the configuration of the power cutoff circuit of the same embodiment. FIG. 5 is a block diagram showing the specific configuration of the memory control unit 12 and memory 14 of the same embodiment. 6 are a configuration diagram of received data and a timing chart for explaining the operation of the same embodiment. 1-1 to 7-n...keyboard, 2...transmission device,
3-1~J-m...electronic wristwatch, 5...receiver, 1
0... Calling code detection circuit, 11... Reception control unit,
12... Mesori control unit, 13... Power cutoff circuit, 1
4...Memory, 31...Call code ROM, 5o.
...Receiving device.

Claims (1)

[Claims] A communication device comprising a transmitting device for transmitting a signal consisting of call data and message data, a receiving device having a clock means for creating time data, and a receiving means for receiving the signal transmitted from the transmitting device, the receiving device comprising: a detection means for detecting message data including alarm time data transmitted from the transmitting device; a memory means for storing message data including the alarm time data according to a detection result of the detection means; Coincidence detection means for detecting coincidence between time data and alarm time data stored in the memory means; and control means for notifying message data stored in the memory means based on the coincidence detection by the coincidence detection means. A communication device characterized by comprising: