JPS61191139A - Receiver - Google Patents

Abstract

PURPOSE:To obtain a receiver with high secrecy while not being intercepted easily by the 3rd party by providing plural scramble series and applying scrambling to a signal key to descrambling. CONSTITUTION:A reception data is fed to a bit clock extraction circuit 2 from a terminal 1, a bit clock synchronously with a reception data is recovered and fed to a decoder 3, where processing such as error correction is applied. On the other hand, the M series with a prescribed pattern is generated from an M series generating circuit 6 by the instruction from a microcomputer 7 and the M series is fed to a descrambler 5. In this case, a scramble synchronization detecting circuit 9 extracts a data corresponding to the scramble synchronous signal from one frame data to detect whether the said data is coincident with a fixed pattern of the scramble synchronous signal or not. When the circuit 9 detects the scramble synchronous signal, it is know that the reception data is descrambled correctly by the descrambler 5 by the output of the circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a receiving device used, for example, in an information transmission system using satellite communication, and particularly to a scrambling device for confidential communication.

[Conventional technology]

When information is transmitted using satellite communication, it is possible to instantly transmit information over a wide area. Therefore, an information transmission system using satellite communication is convenient, for example, when it is desired to instantly transmit information such as product pictures and inventory data from a head office to sales offices scattered over a wide area.

In an information system using satellite communication, a video signal F and audio and data signals F2 are transmitted as transmission information, as shown in FIG. The video signal F1 is an analog color video signal, and the highest frequency f1 is, for example, 4.5 MHz.
It is said that For example, the audio signal is 2 channels, and the PC
It is Mized. The sampling frequency f of the audio signal is, for example, 48 KHz, and the number of quantization bits is 16 bits. This PCM audio signal and additional data used for transmitting inventory information, for example, are transmitted in a predetermined data format. A subcarrier of, for example, 5.727 MHz frequency-division multiplexed on the video signal is subjected to four-phase PSK modulation using the audio and data signal F2.

A composite signal of the video signal F1 and the four-phase PSK modulated audio and data signal F2 is FM modulated, frequency converted to, for example, 14 GHz, and transmitted from the transmitting side on the ground to the artificial satellite. Radio waves sent from the transmitting side are received by an artificial satellite. Radio waves received in the artificial satellite are frequency-converted to, for example, 1.2 GHz, amplified to a power that can be directly received on the receiving side, and transmitted from the artificial satellite to a receiving station on the ground.

In an information transmission system using satellite communication, there is a need for confidential communication when providing information to people who have paid a certain amount through a pay service, or when transmitting highly important information. arise. For this reason, the information transmission system performs scrambling at the time of transmission and descrambling at the time of reception.

FIG. 8 shows an example of a receiving device that performs descrambling in an information transmission system using satellite communication.

An antenna 51 receives radio waves from an artificial satellite, and the radio waves are supplied to a receiving circuit 52. This radio wave is, for example, a 12GH2 SHF band radio wave. The receiving circuit 52 is a double superheterodyne type receiving circuit.

After the SHF band radio wave is converted to an intermediate frequency and amplified by the receiving circuit 52, this intermediate frequency signal is supplied to the FM demodulation circuit 53.

The output of the FM demodulation circuit 53 is supplied to a low pass filter 54 and a band pass filter 55. An analog color video signal is obtained from the output of the low-pass filter 54. This color video signal is scrambled during transmission. The output of the low-pass filter 54 is supplied to a descrambling circuit 56.
A color video signal is taken out to an output terminal 57 of the .

Four-phase PSK modulated audio and data signals are obtained from the bandpass filter 55. The output of the bandpass filter 55 is supplied to a four-phase PSK modulation circuit 58 and demodulated. The demodulated voice and data signals are scrambled during transmission. The output of the demodulation circuit 58 is supplied to a descrambling circuit 59, and the output of the descrambling circuit 59 is supplied to a signal processing circuit 60. A signal processing circuit 60 performs processing such as error correction. An output terminal 61 is extracted from the signal processing circuit 60, and audio and data signals are taken out from the output terminal 61.

Conventionally, methods such as inverting the video signal, reducing the level of the synchronizing signal, or adding an offset to the synchronizing signal have been used to scramble analog video signals.
This scrambling was done so that it could not be received under normal conditions. Furthermore, conventionally, as a slump for digital audio and data signals, unnecessary information such as M-sequence (maximum long period sequence) data has been superimposed on the audio and data signals.

[Problem that the invention seeks to solve]

A key signal for descrambling is added to conventional digital voice and data scrambling. This key signal is not scrambled. Therefore, if the correspondence between the key signal and the scramble pattern is decoded, confidentiality can no longer be maintained and the signal can be easily received by a third party.

Therefore, an object of the present invention is to provide a system that has multiple scramble sequences and also scrambles the key signal for descrambling, so that it is difficult for a third party to eavesdrop on the information and the information is highly confidential. The object of the present invention is to provide a receiving device used in the system.

[Means for solving problems]

According to the present invention, one frame of data consisting of a birosoto signal with a predetermined bit pattern, a scramble code indicating one pattern of a plurality of scramble sequences, and digital data is processed by a scramble sequence specified by the scramble code of the previous frame. A receiving device that receives scrambled data includes a descrambler 5 to which received data is supplied, a means 9 for detecting a pilot signal from the output of the descrambler 5, and a predetermined scramble sequence that is initially set. is,
A new scramble code is set when the pilot signal is detected, a scramble sequence specified by the set scramble code is generated, and the descrambler
5 and a scramble sequence generation circuit 6.7 for supplying the scramble sequence.

[Effect]

(2) Frame data consists of a pilot signal with a predetermined bit pattern, a scramble code indicating one pattern among a plurality of scramble sequences, and digital data.

A predetermined scramble sequence is initially set in the M sequence generation circuit 6. The scramble series pattern is
It is changed by random numbers during scrambling, and there is always a frame scrambled with a pattern corresponding to the initial code, so when one frame of data scrambled with a pattern corresponding to the initial code arrives, the pilot signal is scrambled to the sync detection circuit. Detected at 9. The M sequence pattern for the next frame is newly set using the scrambling code when the pilot signal is detected.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The present invention is suitable for use, for example, in a receiving device in an information transmission system using artificial hygiene.

The transmission data in this embodiment is transmitted in units of (1) frames. As shown in Figure 2, one frame consists of data transmitted as information, a scrambling code indicating a scramble sequence pattern, and a fixed 8-bit signal, for example, which becomes a biloft signal to detect whether descrambling is performed correctly. It consists of a bit pattern scramble sync and a frame sync added to the beginning of the frame.

The scramble code indicates the pattern of the scramble sequence of the next frame. The scramble sequence pattern can be obtained from, for example, 10th-order and 11th-order generator polynomials. Twenty types of M sequences are used.

A PN sequence (pseudo-noise sequence) is used as a two-level sequence for scrambling.The M sequence is one of the PN sequences, and is relatively easy to use because of a shift register circuit with a feedback loop and an exclusive OR gate.
It can easily occur. If the degree of the generator polynomial g (x) is k, the period of the generated M sequence is (n=2.'
, -1).

These M-sequence patterns are associated with respective scramble codes (8 bits), as shown in FIG. 3, for example. In the scramble code, for example, OA~
No pattern is defined for OF and IA to IF. These scrambling codes mean that the same M-sequence pattern as specified by the scrambling code of the previous frame is used. In this way, since the scramble code that does not correspond to the pattern is included, the correspondence between the scramble code and the pattern becomes complicated. Therefore, this correspondence relationship cannot be easily understood by a third party.

One of the M-sequence patterns is selected for each frame using, for example, random numbers, and this pattern of M-sequences is superimposed not only on the data but also on the scramble code and scramble sync.

In this way, not only the data but also the scramble code, which is the key to descrambling, is scrambled, so this data has a known correspondence between the scramble code and the pattern. too·
It is not easily readable and is highly confidential.

Here, the scrambling process on the transmitting side will be explained. FIG. 4 shows an example of a scrambling device on the transmitting side. In FIG. 4, reference numeral 31 indicates an input terminal, and data to be transmitted is supplied from the input terminal 31 to an adder circuit 32. The addition circuit 32 is supplied with a scramble sync of a fixed focus pattern from a scramble sync generation circuit 33. An adder circuit 32 adds a scramble sync to a predetermined position.

The output of the adder circuit 32 is supplied to an adder circuit 34. The output of the scramble code generation circuit 35 is supplied to the adder circuit 34 . The scramble code generation circuit 35 is controlled by a controller 36. One scramble code is designated by the controller 36, and the designated scramble code is sent to the scramble code generation circuit 3.
5 to an adder circuit 34, and a scramble code is added to a predetermined position.

The output of the adder circuit 34 is supplied to a scrambler 37. The scrambler 37 is, for example, an exclusive O
It is composed of R gates.

The output of the M-sequence generation circuit 38 is supplied to the scrambler 37.

The M-sequence generation circuit 38 selectively generates one M-sequence out of 20 types of M-sequences, each corresponding to the generating polynomial shown in FIG. This generated M series is
According to the command from 6, the pattern corresponding to the scramble code added to the previous frame is set. M
Data to which a scramble sync and a scramble code are added is scrambled by the output of the sequence generation circuit 38.

The output of the scrambler 37 is supplied to an adder circuit 39. The output of the frame sync generation circuit 40 is supplied to the adder circuit 39 . An adder circuit 39 adds a frame sync to a predetermined position.

The output of the adder circuit 39 is supplied to the encoder 41. The encoder 41 adds parity of the error correction code. The thickness ratio of the output terminal 42 from the encoder 41 is
Transmission data (see FIG. 2) is obtained from the output terminal 42.

An embodiment of the present invention is applicable to a receiving device in an information transmission system in which data is transmitted as described above.

FIG. 1 shows an embodiment of the present invention.

In FIG. 1, 1 indicates an input terminal, and received data from the input terminal 1 is supplied to the bit clock extraction circuit 2.

The bit clock extracting circuit 2 reproduces a bit clock synchronized with the received data, and the output of the bit clock extracting circuit 2 is supplied to the decoder 3. The decoder 3 corresponds to the encoder 41 provided on the transmitting side, and processes such as error correction are performed by the decoder 3.

The output of the decoder 3 is supplied to a descrambler 5 via a frame sync detection circuit 4.

The descrambler 5 is composed of, for example, an exclusive OR gate. An M-sequence of a predetermined pattern is generated from an M-sequence generation circuit 6 according to a command from the microcomputer 7, and this M-sequence number sequence is supplied to a descrambler 5. The M-sequence generation circuit 6 selectively generates one M-sequence from among 20 types of M-sequences, each corresponding to the generating polynomial shown in FIG. The command from the microcomputer 7 specifies the generating polynomial.

The output of the descrambler 5 is supplied to a data processing circuit 8, as well as a scramble sync detection circuit 9 and a gate circuit 10. The gate circuit 10 extracts data corresponding to a scramble code from one frame of data. The output of the scramble sync detection circuit 9 and the output of the gate circuit 10 are supplied to the microcomputer 7. Further, a signal indicating 0N10FF of the power supply is supplied from the terminal 11 to the microcomputer 7.

The scramble sync detection circuit 9 extracts data corresponding to a scramble sync from one frame of data and detects whether this data matches a fixed pattern of the scramble sync. If the scramble sync can be detected by the scramble sync detection circuit 9, it can be seen from the output of the M-sequence generation circuit 6 that the received data has been correctly descrambled by the descrambler 5. The output of the scramble sync detection circuit 9 is supplied to the display device 12, and the display device 12 informs whether or not scramble sync is detected.

The scramble sync detection circuit 9 is configured as shown in FIG.

In FIG. 5, reference numeral 15 indicates an input terminal, and the output of the descrambler 5 is supplied from the input terminal 15 to the gate circuit 16. A gate pulse is supplied from a terminal 17 to the gate circuit 16 for extracting a portion corresponding to the scramble sync, and data corresponding to the scramble sync is extracted by the gate circuit 16 in the (2) frame.

The output of the gate circuit 16 is supplied to a shift register 18. A bit clock is supplied to the shift register 18 from a terminal 19. The shift register 18 converts serial data into parallel data, and the output of the shift register 18 is supplied to the comparator 20.

A fixed bit pattern of scramble sync is supplied to the comparator 20 from a scramble sync pattern generation circuit 21. By comparator 20, shift register 1
It is detected whether the output of 8 matches a fixed bit pattern, and this detection output is supplied to the majority logic circuit 22.

The majority logic circuit 22 makes a majority logic decision regarding the detection results of, for example, five consecutive frames output from the comparator 20. For example, if scramble sync is detected in 3 or more frames out of 5 consecutive frames, it is determined that scramble sync has been detected,
This determination result is taken out from the output terminal 23.

The microcomputer 7 determines an M-sequence pattern for descrambling from the output of the scramble sync detection circuit 9, the output of the gate circuit 10, and a signal indicating 0N10FF of the power supplied from the terminal 11. A command is given from the microcomputer 7 to the M-sequence generation circuit 6 to generate the determined pattern. Descrambling is performed using M sequences of patterns set by instructions from the microcomputer 7.

The data processing circuit 8 is given information from the microcomputer 7 indicating whether descrambling is being performed correctly. The data processing circuit 8 detects and corrects errors regarding the descrambled data. Frame data that has not been descrambled correctly is treated as invalid data. In the case of audio data, the data processing circuit 8 performs data interpolation using, for example, pre-hold. Data processing diagram! An output terminal 13 is derived from the output terminal 8, and received data is taken out from the output terminal 13.

The descrambling control performed by the microcomputer 7 will be explained below with reference to the flowchart of FIG.

First, the scramble code is an initial code (for example, 00)
, and a pattern corresponding to the initial code is generated from the M-sequence generation circuit 6 (step 2).

With the initial code set, it is determined whether the scramble sync detection circuit 9 can detect a scramble sync (step 2). ``The fact that the scramble sync has been detected means that the received data has been descrambled by the M sequence of the pattern corresponding to the initial code. Therefore, when a scramble sync is detected, the scramble code for the next frame can be detected from the received data supplied via the gate circuit IO.

If the scramble sync cannot be detected, the process returns to step (3) and the initial code is set again.

If the scramble sync can be detected, the scramble code for the next frame is detected from the received data supplied via the gate circuit 10 (step (2)).

A scrambling code for the next frame is set from the detected scrambling code, and a pattern corresponding to the set code is generated from the M-sequence generation circuit 6.

(Step ■).

In this state, it is determined whether the scramble sync of the next frame has been detected (step ■), and if the scramble sync has been detected, the scramble code is detected (step ■), and the detected scramble code is A scrambling code for the next frame is further set based on the information (step 2).

The M-sequence pattern is changed by random numbers during scrambling, and there is a pattern corresponding to the initial code for each access time. Therefore, usually step
A scramble sync is detected within a predetermined access time.

”Unlike the embodiment described in 1 above, if the scramble sync cannot be detected after descrambling has been performed correctly, the previous correct scramble code is held without setting the same initial code as when the power was turned on. You may also do so.

〔Effect of the invention〕

According to this invention, predetermined scramble sequences are initially set. The pattern of the scramble sequence is changed by random numbers during scrambling, and since there is always a frame scrambled with a pattern corresponding to the initial code, a pilot signal is detected in this frame. Detection of the pilot signal means that it has been descrambled correctly. The scrambling code for the next frame can be set from the scrambling code used when the pilot signal is detected. Therefore, the present invention can realize an information transmission system with extremely high confidentiality by having a plurality of scrambling sequences and also performing scrambling on a signal that is a key to unscrambling.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a route map of an example of transmission data in an embodiment of this invention,
Fig. 3 is a route diagram showing the correspondence between scramble codes and scramble sequences, Fig. 4 is a block diagram of an example of a scrambling device in a transmission system to which this invention can be applied, and Fig. 5 is a scramble sync detection circuit. A block diagram of an example, FIG. 6 is a flowchart used to explain descrambling control, FIG. 7 is a spectrum diagram used to explain a transmission system using conventional satellite communication, and FIG.
The figure is a block diagram of an example of a receiving device having a descrambling function in a conventional transmission system using satellite communication. 1: Input terminal, 5: Descrambler, 6: M-series generation circuit, 7: Microcomputer, 8: Data processing circuit, 9 Niscrumple zinc detection circuit, 13
: Output terminal.

Claims (1)

[Claims] One frame of data consisting of a pilot signal with a predetermined bit pattern, a scramble code indicating one pattern among a plurality of scramble sequences, and digital data is specified by the scramble code of the previous frame. A receiving device that receives data scrambled by a scramble sequence, comprising: a descrambler to which the received data is supplied; means for detecting the pilot signal from the output of the descrambler; and a means for detecting the pilot signal from the output of the descrambler; The scramble code that is initially set and is used when the pilot signal is detected is newly set, and a scramble sequence specified by the set scramble code is generated;
A receiving device comprising: a scramble sequence generation circuit that supplies the scramble sequence to the descrambler.