JPS61131637A - Scramble device - Google Patents

Abstract

PURPOSE:To reduce the access time in case of descrambling by using a scramble series corresponding to an initial code at each prescribed period in scrambling periodically data by plural scramble series. CONSTITUTION:Transmission data is constituted in the unit of frames, consists of a scramble synchronizing signal discriminating correctness of descrambling, a scramble code representing the scramble series of the next frame and data is scrambled by using a scramble series corresponding to a scramble code of the preceding frame depending on the scramble synchronizing signal. An initial code FC is inserted to a scramble code of the frame series at a prescribed period and the frame next to the FC is scrambled by the scramble series corresponding to the FC. The data is descrambled by using the series corresponding to the FC at the reception side and a scramble code is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a scrambling device for confidential communication used in an information transmission system using, for example, 1st communication.

[Conventional technology]

When information is transmitted using satellite communication, it is possible to instantly transmit information over a wide area. For this reason, an information system using satellite communication is convenient, for example, when it is desired to instantly transmit information such as product pictures and inventory data from a head office to sales offices scattered over a wide area.

In an information transmission system using satellite communication, a video signal F and audio and data signals F are transmitted as transmission information, as shown in FIG. The video signal F+ is an analog color video signal, and the highest frequency f is, for example, 4.5M.
It is said to be Hz. For example, the audio signal has two channels,
It is converted into PCM. Sampling frequency f of audio signal
For example, s is 48 KHz and the number of quantum bits is 16 bits. This PCM audio signal and additional data used for transmitting inventory information, for example, are transmitted in a predetermined data format. The video signal is frequency-division multiplexed, and a subcarrier of, for example, 5.727 MHz is subjected to four-phase PSK modulation from this audio and data signal F2.

A composite signal of the video signal F and the four-phase PSK modulated audio and data signal F2 is FM modulated, frequency converted to, for example, 14 GHz, and transmitted from the transmitting side on the ground to the artificial satellite. Radio waves sent from the transmitting side are received by an artificial satellite. In the artificial satellite, received radio waves are frequency-converted to, for example, 12 GHz, amplified to a power that can be directly received on the receiving side, and transmitted from the artificial satellite to a receiving station on the ground.

Paype is an information transmission system using satellite communication.

When providing information targeted at a person who has paid a predetermined amount for a service, or when transmitting highly important information, it becomes necessary to perform confidential communication. For this reason,
In an information transmission system, scramble is performed at the time of transmission.
Descrambling is performed when receiving.

FIG. 8 shows an example of a receiving device that performs descrambling in an information transmission system using satellite communication.

An antenna 51 receives radio waves from an artificial satellite, and the radio waves are supplied to a receiving circuit 52. This radio wave is, for example, a 12 GHz SHF band radio wave. The receiving circuit 52 is a double superheterodyne receiving circuit.

After the SHF band radio wave is converted to an intermediate frequency and amplified by the receiving circuit 52, this intermediate frequency signal is supplied to the FM demodulation circuit 53.

The output of the FMfi adjustment circuit 53 is supplied to a low pass filter 54 and a band pass filter 55. An analog color video signal is obtained from the output of the low-pass filter 54. This color video signal is scrambled during transmission. The output of the low-pass filter 54 is supplied to a descrambling circuit 56.
A color video signal is taken out to an output terminal 57 of 6.

Four-phase PSK modulated audio and data signals are obtained from the bandpass filter 55. The output of the bandpass filter 55 is supplied to a four-phase PSK modulation circuit 58 and demodulated. The demodulated voice and data signals are scrambled during transmission. The output of the demodulation circuit 58 is supplied to the descrambling circuit 59.
The output of 9 is supplied to a signal processing circuit 60. A signal processing circuit 60 performs processing such as error correction. An output terminal 61 is led out from the signal processing circuit 60, and audio and data signals are taken out from the output terminal 61.

Conventionally, methods such as inverting the video signal, reducing the level of the synchronizing signal, or adding an offset to the synchronizing signal have been used to correct rumble in the analog video signal.
This scrambling prevents reception under normal conditions. Furthermore, in scrambling digital audio and data signals, unnecessary information such as M-sequence (maximum long period sequence) data has conventionally been superimposed on the audio and data signals.

[Problem that the invention seeks to solve]

Conventional digital voice and data scrambling includes an additional signal that is the key to descrambling. This key signal is not scrambled. Therefore, if the correspondence between the key signal and the scramble pattern is decoded, confidentiality can no longer be maintained and the signal can easily be received by a third party.

Therefore, in order to improve confidentiality, it is conceivable to have a plurality of scrambling sequences and also scramble the key signal for descrambling to prevent a third party from easily eavesdropping. However, if the number of scramble patterns is increased, the time required for the next appearance of the same scramble code becomes longer, and as shown in FIG. A scramble sequence pattern (specified by an 8-bit scramble code in hexadecimal notation in FIG. 9) appears at a predetermined pattern period, and 1
If the same patterns are arranged so that there are no identical patterns within each pattern period, the time until the next initial code FC appears will be equal to the pattern period in which the scramble code changes. When an initialization code FC is set on the receiving side to detect a scramble sequence pattern, the access time until descrambling is determined by the time until the initial code appears next. Therefore,
In order to improve privacy, the problem arises that the more types of scramble sequences are increased, the longer the access time until descrambling becomes possible.

Therefore, an object of the present invention is to provide a scrambling device that can be used in an information transmission system with extremely high confidentiality and that can shorten the access time during descrambling even if there are many types of scrambling sequences. It is about providing.

[Means for solving problems]

The present invention provides a scrambling device that scrambles transmission data with a plurality of scramble sequences having different patterns, in which one pattern of the plurality of scramble sequences is generated and the scramble sequence of this pattern is scrambled together with the transmission data. a scramble sequence generation circuit 11 for supplying the scramble sequence generation circuit 11 to the scramble sequence generation circuit 11; means 4.6 for generating in advance a scramble code indicating the pattern of the scramble sequence outputted from the scramble sequence generation circuit 11 and adding it to the output of the scrambler; Means for generating a predetermined scramble code representing one predetermined scramble sequence of the scramble sequences at a set period, and controlling the scramble sequence generation circuit 6 to generate the predetermined scramble sequence after the predetermined scramble code.5. 7.8.9 A scrambling device characterized by comprising: It is.

[Effect]

A scramble code indicating a plurality of scramble sequence patterns is generated from the scramble code generation circuit 6,
An initial code, which is one of the scramble codes corresponding to a predetermined scramble sequence, is generated from the initial code generation circuit 7, and these scramble codes are selectively added prior to scrambling. The access time counter 9 adds a scramble code of a predetermined initial code at predetermined intervals prior to scrambling.

Data for each predetermined period is scrambled using a pattern corresponding to a predetermined initial code.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This invention is suitable for use in, for example, an information transmission system using artificial hygiene.

The transmission data in this embodiment is transmitted in units of one frame. As shown in Figure 2, one frame consists of data transmitted as information, a scrambling code indicating a scramble sequence pattern, and a fixed signal of, for example, 8 bits, which serves as a pilot signal to detect whether descrambling is performed correctly. The frame consists of a bit pattern scramble sync and a frame sync added to the beginning of one frame.

The scramble code indicates the pattern of the scramble sequence of the next frame. As scramble sequence patterns, for example, 20 types of M sequences obtained from 10th-order and 11th-order generator polynomials are used.

A PN sequence (pseudo-noise sequence) is used as a two-level sequence for scrambling. The M sequence is one of the PN sequences, and can be generated relatively easily using a shift register circuit having a feedback loop and an exclusive OR gate. If the degree of the generator polynomial g (x) is k, then the period of the generated M sequence is (n=2”−
1).

These M-sequence patterns are associated with respective scramble codes (8 bits), as shown in FIG. 3, for example. In the scramble code, for example, 0A-
No pattern is defined for OF and IA-IF. These scramble codes mean that the same M-sequence pattern as specified by the previous frame's scramble code is used. In this way, since the scramble code that does not correspond to the pattern is included, the correspondence between the scramble code and the pattern becomes complicated. Therefore, this correspondence relationship cannot be easily understood by a third party.

(2) One of the M-sequence patterns is selected for each frame, and the M-series of this pattern is superimposed not only on the data (but also on the scramble code and scramble sync).

In this way, not only the data (but also the scramble code, which is the key to descrambling) is scrambled, so this data has a known correspondence between the scramble code and the pattern. However, it cannot be easily deciphered (it is highly confidential).

FIG. 1 shows an embodiment of the present invention. 1st
In the figure, 1 indicates an input terminal, and data to be transmitted is supplied from input terminal 1 to adder circuit 2 . The adder circuit 2 is supplied with a scramble sync having a fixed bit pattern from the scramble sync generating circuit 3. The adder circuit 2 adds a scramble sync at a predetermined position, for example, after the frame sync of one frame.

The output of the adder circuit 2 is supplied to the adder circuit 4.

The adder circuit 4 is selectively supplied with a scramble code outputted from a scramble code generation circuit 6 and an initial code FC, for example "00", outputted from an initial code generation circuit 7 via a switch circuit 5.

The scramble code generation circuit 6 randomly generates one scramble code according to a command from the controller 8. The switch circuit 5 is controlled by the output of the access time counter 9 to select the output of the initial code generation circuit 7 at every predetermined access time.

Therefore, in the scramble code extracted from the output of the switch circuit 5, an initial code FC, for example, "00" appears at every predetermined access time. A scramble code is added at a predetermined position, for example after one frame of scramble sync, by the output of the switch circuit 5.

The output of the adder circuit 4 is supplied to a scrambler 10.

The scrambler 10 is composed of, for example, an exclusive OR gate. The output of the M-sequence generation circuit 11 is supplied to the scrambler 10.

The M-sequence generation circuit 11 selectively generates one M-sequence out of 20 types of M-sequences, each corresponding to the generating polynomial shown in the third tooth. This generated M series is
The pattern is set to correspond to the scramble code added to the previous frame. An initial code FC is added to a frame every predetermined shift time. Therefore, an M sequence of a pattern corresponding to the initial code 'FC is generated from the M sequence generation circuit 11 at every predetermined access time. One frame of data consisting of a scramble sync, a scramble code, and data is scrambled by the output of the M-sequence generation circuit 11.

The output of the scrambler 10 is supplied to an adder circuit 12. The output of the frame sync generation circuit 13 is supplied to the adder circuit 12, and a frame sync is added to a predetermined position (the beginning of one frame).

The output of adder circuit 12 is supplied to encoder 14 . The encoder 14 adds parity of the error correction code. An output terminal 15 is derived from the encoder 14,
Transmission data (see FIG. 2) is obtained from the output terminal 15.

FIG. 4 shows an example of a descrambling device on the receiving side. In FIG. 4, 21 indicates an input terminal, and the data received from the input terminal 21 is sent to the pit clock extraction circuit 2.
2. The pit clock extraction circuit 22 reproduces a pit clock synchronized with the received data, and the output of the pit clock extraction circuit 22 is supplied to the decoder 23.

The decoder 23 is the encoder 1 provided on the transmitting side.
4, and this decoder 23 performs processing such as error correction. The output of the decoder 23 is supplied to a descrambler 25 via a frame sync detection circuit 24.

The descrambler 25 is, for example, an exclusive OR
It is made up of gates. microcomputer 2
7 generates an M sequence of a predetermined pattern from the M sequence generation circuit 26, and this M sequence is sent to the descrambler.
25.

The M-sequence generation circuit 26 selectively generates one M-sequence from among 20 types of M-sequences, each corresponding to the generator polynomial shown in FIG. The command from the microcomputer 27 specifies the generating polynomial.

The output of the descrambler 25 is supplied to a data processing circuit 28, as well as a scramble sync detection circuit 29 and a gate circuit 30. The gate circuit 30 extracts a portion of data corresponding to the scramble code from the l-frame data. The output of the scramble sync detection circuit 29 and the output of the gate circuit 30 are supplied to the microcomputer 27. Also, the power supply 0N10
A signal indicating FF is sent from the terminal 31 to the microcomputer 2.
7.

The scramble sync detection circuit 29 extracts data corresponding to a scramble sync from one frame of data and detects whether this data matches a fixed pattern of the scramble sync. If the scramble sync is detected by the scramble sync detection circuit 29, it can be seen from the output of the M sequence generation circuit 26 that the received data has been correctly descrambled by the descrambler 25. Scramble sync detection circuit 2
The output of 9 is supplied to a display device 32, and the display device 32 informs whether or not scramble sync is detected.

The scramble sync detection circuit 29 is configured as shown in FIG.

In FIG. 5, 35 indicates an input terminal, and the output of the descrambler 25 is supplied from the input terminal 35 to a gate circuit 36. A gate pulse is supplied from a terminal 37 to the gate circuit 36 for extracting a portion corresponding to the scramble sync, and data corresponding to the scramble sync is extracted by the gate circuit 36 within one frame.

The output of the gate circuit 3G is supplied to the shift register 38. A pit clock is supplied to the shift register 38 from a terminal 39. The shift register 38 converts serial data into parallel data, and the output of the shift register 38 is supplied to the comparator 40.

A fixed bit pattern of scramble sync is supplied to the comparator 40 from a scramble sync pattern generation circuit 41. Comparator 40 causes shift register 3
It is detected whether the output of 8 matches a fixed bit pattern, and this detection output is supplied to the majority logic circuit 42.

The majority logic circuit 42 makes a majority logic decision regarding the detection results of, for example, five consecutive frames outputted from the comparator 40. If scramble sync is detected in, for example, three or more frames out of five consecutive frames, it is determined that scramble sync has been detected, and the determination result is output from the output terminal 43.

The microcomputer 27 outputs the output of the scramble sync detection circuit 29, the output of the gate circuit 30, and the terminal 31.
The M-sequence pattern for descrambling is determined based on the signal indicating 0N10FF of the power supplied from the oscilloscope. A command is given from the microcomputer 27 to the M-sequence generation circuit 26 to generate the determined pattern.

Descrambling is performed using M sequences of patterns set by instructions from the microcomputer 27.

The data processing circuit 28 is given information from the microcomputer 27 indicating whether descrambling is being performed correctly. The data processing circuit 28 detects and corrects errors in the descrambled data. Frame data that has not been descrambled correctly is treated as invalid data. In the case of audio data, the data processing circuit 28 performs data interpolation using, for example, pre-hold. Data processing circuit 2
An output terminal 33 is derived from the output terminal 8, and received data is taken out from the output terminal 33.

The descrambling control performed by the microcomputer 27 will be explained below with reference to the flowchart of FIG.

First, the scramble code is an initial code (for example, 00)
is set, and a pattern corresponding to the initial code is generated from the M sequence generation circuit 26 (step 2).

With the initial code set, it is determined whether the scramble sync detection circuit 29 can detect a scramble sync (step 2).

The fact that the scramble sync has been detected means that the received data has been descrambled by the M sequence of the pattern corresponding to the initial code. Therefore, when a scramble sync is detected, the scramble code for the next frame can be detected from the received data supplied via the gate circuit 30.

If the scramble sync cannot be detected, the process returns to step (3) and the initial code is set again.

If the scramble sync can be detected, the scramble code for the next frame is detected from the received data supplied via the gate circuit 30 (step 2).

A scrambling code for the next frame is set from the detected scrambling code, and a pattern corresponding to the set code is generated from the M-sequence generation circuit 26. (Step ■).

In this state, it is determined whether the scramble sync of the next frame has been detected (step ■), and if the scramble sync has been detected, the scramble code is detected (step ■), and the detected scramble code is A scrambling code for the next frame is further set based on the information (step 2).

There is one M-sequence pattern, and there is a pattern corresponding to the initial code for each access time. Therefore, normally, a scramble sync is detected within a predetermined access time in step (2).

〔Effect of the invention〕

According to this invention, the scrambled data always includes a scramble sequence corresponding to the initial code at every predetermined period. Therefore, as shown in FIG. 10, the period at which the initial code appears is always a predetermined period, regardless of the type of scramble sequence or the pattern period at which the scramble code changes. Therefore, by setting a predetermined initial code on the receiving side, the scrambling pattern can always be detected at predetermined intervals.
Access time during descrambling can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a route map of an example of transmission data in an embodiment of this invention,
FIG. 3 is a route diagram showing the correspondence between scrambling codes and scramble sequence generating polynomials, FIG. 4 is a block diagram of an example of a descrambling device on the receiving side in a transmission system to which the present invention can be applied, and FIG. 5 6 is a block diagram of an example of a scramble sync detection circuit, FIG. 6 is a flowchart used to explain descrambling control, and FIG.
The figure is a spectrum diagram used to explain a transmission system using conventional satellite communication, Figure 8 is a block diagram of an example of a receiving device having a descramble function in a transmission system using conventional satellite communication, and Figure 9 is a conventional FIG. 10 is a route map used to explain an example of the scramble code arrangement, and FIG. 10 is a route map used to explain in detail the present invention. input terminal, 3 scramble synchro path, 5: switch circuit, 6: scramble code generation circuit, 7
: initial code generation circuit, 8: controller, 9:
Access time counter, 10niscrambler, 1
1: M series generation circuit, 15: Output terminal.・Frame sync Figure 3 Figure 4 Figure 5 FIJ Figure 6 Figure 10vA

Claims (1)

[Scope of Claims] A scrambling device that scrambles transmission data using a plurality of scramble sequences having different patterns, wherein one pattern of the plurality of scramble sequences is generated and the above-mentioned scramble sequences of the above-mentioned pattern are generated together with the transmission data. a scramble sequence generation circuit that supplies a scramble sequence to a scrambler; means for generating in advance a scramble code indicating a pattern of the scramble sequence output from the scramble sequence generation circuit and adding it to the output of the scrambler; The predetermined scramble code representing one predetermined scramble sequence among the plurality of scramble sequences is generated at a set cycle, and the scramble sequence generation circuit generates the predetermined scramble sequence after the predetermined scramble code. A scrambling device characterized in that it is equipped with means for controlling.