JPS61167994A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a display device controlled based on a CRT interface.

(Prior Art) CRT display devices have become more widespread than ever before, and because no display device has emerged that can replace them based on comprehensive value judgments such as cost, display capacity, reliability, and display quality, CRT display devices are still the mainstay of display devices. It is used as an input/output terminal device for home TVs, computers, etc. For this reason, one-chip CRT controllers have become widespread and readily available at low prices to control CRT display devices in response to CRT demand.

On the other hand, since it is easy, inexpensive, and highly expandable for controlling display devices other than CRTs, such as plasma display devices and fluorescent display tubes,
There are many fists that use controllers. However, some CRT controllers cannot make the vertical synchronizing signal pulse corresponding to the vertical retrace period of the CRT shorter than the period used for displaying one line. Therefore, when such a CRT controller is used to control, for example, a plasma display device, there is a drawback that the brightness is reduced because the lighting prohibition period occupies a large proportion.

FIG. 3 is a plan view of a conventional three-line display plasma display device. It is assumed that each row 10 in this figure is composed of eight rasters (scans). Fourth
The figure shows a conventional display method. Each data 13 (dl, d2...d,) in Fig. 4 is 1
This is DATA corresponding to the 1st raster, 2nd raster, 3rd raster, and 8th raster in the row.

Furthermore, each row 10 corresponds to the first row, second row, and
Input each data d□ to d8 as shown in the third line. Also,
tl is the horizontal synchronization period, t2 is the vertical synchronization pulse period, t3
indicates a vertical synchronization period, and the vertical synchronization pulse period t2 is a lighting prohibition period. Note that the actual lighting prohibition period is shifted to the right by the horizontal synchronization period t0 from the position of the vertical synchronization pulse period t2.

As described above, since the lighting prohibition period (t2) occupies 25% of the vertical synchronization period t3, there is a drawback that the brightness of the display section decreases by that amount.

(Object of the Invention) The object of the present invention is to eliminate such drawbacks and to display the vertical synchronizing pulse that is input after inputting data for one screen as an intermittent pulse that is input only once after inputting data for multiple screens. An object of the present invention is to provide a display device in which brightness can be increased by generating synchronous pulses within a circuit.

(Configuration of the Invention) The configuration of the present invention provides a display device that displays data on a screen using a horizontal synchronization signal, a vertical synchronization signal, data, and a clock signal input from the outside based on an OR, T interface. The input of the vertical synchronization signal can be achieved by inputting the synchronization signal only once intermittently after inputting the synchronization signal for multiple screens, and synchronizing the vertical synchronization signal for each screen using an internal vertical synchronization signal generated internally. It is characterized in that the data is displayed during the vertical synchronization pulse period when the vertical synchronization pulse is not performed.

(Example) FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is a plasma display panel, 2 is a scan side driver, 3 is a data side driver, 4 is a scan side shift register, 5 is a data side shift register, 6
is a toggle generator necessary to light up the plasma display panel 1, and 7 is an intermittent vertical synchronization signal (v6Y
N) 16 and internal vertical synchronization signal mo. and a delay circuit.

FIG. 2 is a waveform diagram illustrating the operation of FIG. 1.

Reference numeral 17 denotes an internal vertical synchronizing signal generated within the plasma display apparatus and produced by the scan side shift register 4. Further, 14 is a clock, 13 is data, 12 is a horizontal synchronization signal, and 16 is an intermittent vertical synchronization signal.

The intermittent vertical synchronization period t4 by the intermittent vertical synchronization signal 16 of this embodiment is an intermittent vertical synchronization signal that is once for five screens of data, and each one screen of data is input five times. ing.

The operation of this circuit is such that the data signal 13 is first stored bit by bit in the data side shift register 5 by the clock 14. When all the data signals 13 for one rask are input, the data is latched by the next horizontal synchronizing signal 12, and the data d8 for one rask is transferred to the data side driver 3. Furthermore, the output of the data side driver 3 is sent to the plasma display panel 1 and stopped. At the same time, the scan-side data signal generated by the delay circuit 7 is input to the scan-side shift register 4 in response to the horizontal synchronization signal 12. Upon receiving the data from the scan-side shift register 4, the scan-side driver 2 outputs the data to the plasma display panel 1 in order to turn on the 12th star. While the first rask is lit, data d2 of the next second rask is input to the data side shift register 5. When all the data d2 of the 22nd star is input to the data side shift register 5, the data d2 is transferred to the data side driver 3 by the next horizontal synchronization signal. After that, do the same, line 1, line 2
Data is input in rows and rows 3 and 3, and the lights are lit.

The internal vertical synchronizing signal 17 is at the rlJ level during the period 1 when the data of 8 rasks in the third row is input. This internal synchronization signal 17 is input to the scan side shift register 4 at the timing of the horizontal synchronization pulse after one raster data is input via the delay circuit 7, and becomes new scan signal data. That is, by generating the internal vertical synchronizing signal 17 inside the display device, scan signal data can be automatically generated even if the intermittent vertical synchronizing signal 16 is not input. In this embodiment, after inputting the same data for one screen five times, intermittent vertical synchronization pulses are input to establish synchronization.

Therefore, the ratio of the lighting inhibition period due to the intermittent vertical synchronization pulse 16 to the period t4 is 6.25%.

That is, in the conventional circuit, the ratio of the lighting inhibit period to the intermittent vertical synchronization period was 25%, but in this embodiment it is 6.25%, so the brightness of the display circuit is reduced by 1% compared to the conventional method. .25 times, which is K.

(Effects of the Invention) As described above, according to the present invention, the lighting prohibition period can be shortened compared to the conventional system, so there is an advantage that the brightness can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a plan view showing the display area of a general display device, and FIG. 4 is a timing chart showing the conventional operation. In the figure, 1...Plasma display panel, 2...Scan side driver, 3
...Data side driver, 4...Scan side shift register, 5...Data side shift register,
6--Toggle generator, 7--Delay circuit, 10--Row, 11--Vertical synchronization signal (V8YN), 12--Horizontal synchronization Signal (H
8YN), 13... Data signal, 14...
・Clock, 16... Intermittent vertical synchronization signal, 17.
...This is an internal synchronization signal. Agent: Susumu Uchihara, patent attorney. 1-□□□ Thatch / Concave $ 3 sides

Claims (1)

[Claims] In a display device that displays data on a screen using a horizontal synchronization signal, a vertical synchronization signal, data, and a clock signal input from the outside based on a CRT interface, the vertical synchronization signal is intermittent only once after inputting the vertical synchronization signal for multiple screens. By synchronizing the vertical synchronizing signal for each screen using an internal vertical synchronizing signal generated internally, the data is displayed during a vertical synchronizing pulse period in which the vertical synchronizing signal is not input. A display device characterized by: