JP2578996B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (hereinafter abbreviated as LCD), and more particularly to a signal system for controlling an initial state of the device.

2. Description of the Related Art In recent years, in the field of information devices centering on computers, demand for large-screen, thin LCDs has been increasing, and techniques relating to control methods thereof have become important.

 Hereinafter, a conventional LCD will be described.

FIG. 9 is a circuit block diagram of a conventional LCD.
Is a liquid crystal display panel, 2 is a CPU, 3 is a power supply for the liquid crystal display panel, 4 is VRAM, 5 is a main circuit block of a conventional LCD, 6
Is a display address counter, 7 is a data converter, 8 is a vertical counter, 9 is a vertical register, 10 is a first comparator for comparing the vertical counter 8 and the vertical register 9, 11 is a horizontal counter, 12 is a horizontal register, and 13 is a horizontal register. The second comparator compares the horizontal counter 11 with the horizontal register 12.

Next, the operation of the thus configured LCD will be described.

First, the liquid crystal display panel power supply 3 is turned off. The CPU 2 sets the vertical register 9 and the horizontal register 12 to appropriate values for display. 8 vertical counters, 11 horizontal counters
Are counted up by the horizontal synchronizing signal and the pixel clock, respectively, and if they match the values of the vertical register 9 and the horizontal register 12, they are cleared by the coincidence signals generated from the first comparator 10 and the second comparator 13, and again horizontal. It is counted up by the synchronization signal and the pixel clock. First comparator 10
Is a vertical synchronizing signal, which is input to the liquid crystal display panel 1. The coincidence signal from the second comparator 12 becomes a horizontal synchronization signal and is input to the liquid crystal display panel 1.

The VRAM 4 is a memory for storing display data. The data of the VRAM 4 is read by the display address counter 6, converted into display data of the liquid crystal display panel 1 by the data conversion unit 7, and output. After the display timing signal is stabilized, the CPU 2 outputs a power-on signal to the power supply 3 for the liquid crystal display panel to start displaying.

The reason why the power supply 3 for the liquid crystal display panel is turned on after the register setting is completed is to avoid displaying unnecessary data on the liquid crystal display panel 1.

FIG. 10 is a configuration diagram of a liquid crystal display panel, and 14 is m × n
(M, n are positive integers) dot liquid crystal panel, 15 is the first shift register, 16 is the row side drive circuit, 17 is the second shift register, 18 is the latch, 19 is the column side drive circuit, 20 is the vertical synchronization A first clock which is a signal indicating a signal, 21 is a second clock which is a horizontal synchronizing signal, 22 is display data to be input to the second shift register 17, 23 is display data 22 which is
Is a third clock which is shifted and transferred.

The normal operation timing is as shown in FIG. 11, and the display data 22 is output from the second shift register by the third clock 23.
It is shifted and transferred in 17. When the data is transferred by one line in the horizontal direction, the data is transferred to the latch 18 by the second clock 21. At this time, when the first clock 20 is input, the first clock of the first shift register 15 is latched by the second clock 21 and the first row of the row driving circuit 16 is enabled. The image is displayed on the liquid crystal display panel by the drive circuit 19. Thereafter, when data is transferred, the data is latched by the second clock 21, and the first clock data latched by the first shift register 15 is sequentially shifted and displayed on the liquid crystal display panel 14. When the transfer and display to the last line are completed, the first clock is applied again, and the display on the first line is started.

In an initial state immediately after the power is turned on or the like, the first shift register 15, the second shift register 17, and the latch 18 receive undefined data, and the undefined data is displayed at the undefined display position. Will be displayed.

In order to prevent this, in the conventional LCD shown in FIG. 9, after the CPU 2 sets all necessary register settings, the display data,
After the synchronization signal is determined, the power supply 3 for the liquid crystal display panel is turned on.

Problems to be Solved by the Invention However, the above-described conventional configuration has a problem that a control signal of a power supply for a liquid crystal display panel must be performed by a CPU in order to prevent a noise such as a striped pattern from being displayed on the liquid crystal display panel. I was

An object of the present invention is to solve the above-mentioned conventional problems and to provide an LCD that does not require control of a power supply for a liquid crystal display panel.

Means for Solving the Problems In order to achieve this object, the LCD of the present invention comprises a generating means for generating an appropriate display timing signal before setting correct data in a display setting register.

Operation With this configuration, an appropriate display timing signal is generated when the power is turned on, so that unnecessary display signals are not displayed on the panel, and there is no need to supply a control signal to the liquid crystal display panel power supply. .

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display device according to an embodiment of the present invention.

In FIG. 1, reference numeral 24 denotes a power supply for a liquid crystal display panel that cannot be externally controlled, 25 denotes a main circuit block of the LCD, 26 denotes a vertical synchronization generation unit, 27 denotes a horizontal synchronization generation unit, 28 denotes a reset signal,
29 is a vertical synchronizing signal, and 30 is a horizontal synchronizing signal. Also, 1
Is a liquid crystal display panel, 2 is a CPU, 4 is a VRAM, 6 is a display address counter, 7 is a data converter, 8 is a vertical counter,
9 is a vertical register, 10 is a first comparator for comparing the vertical counter 8 and the vertical register 9, 11 is a horizontal counter, 12 is a horizontal register, 13 is a second comparator for comparing the horizontal counter 11 and the horizontal register 12, These are the same as the conventional example.

Next, the operation of the liquid crystal display device of the present embodiment thus configured will be described with reference to the timing chart of FIG. First, at the same time when the power is turned on,
A reset signal 28 is input and then released. At this time, undefined data is input to the vertical register 9 and the horizontal register 12, and the operations of the vertical counter 8 and the horizontal counter 11 are also undefined. Therefore, both the signal output from the first comparator 10 and the signal output from the second comparator 13 are uncertain signals.

When the reset is released, the vertical synchronization generator 26
As shown in FIG. 2, the vertical synchronizing signal 29 of low level "L"
Is output. As shown in FIG. 2, the horizontal synchronization generator 27 generates a horizontal synchronization signal 30 as a clock corresponding to the number of vertical dots on the display screen. With this signal, in the liquid crystal display panel shown in FIG. 10, the first shift register 15 on the row side is cleared, so that the display data is not displayed on the liquid crystal panel 14. Vertical sync signal 29, horizontal sync signal 3
When the output of 0 is completed, the output from the first comparator 10 is output from the vertical synchronization generator 26, and the output from the horizontal synchronization generator 27 is
The output from the second comparator 13 is output, and thereafter, as in the conventional example, an appropriate value is set in the register and a normal display operation is performed. That is, for a certain period after reset release, the vertical synchronization generator 26 and the horizontal synchronization generator 27 transfer “L” to all bits of the first shift register 15 of the liquid crystal display panel shown in FIG. The circuit 16 is not operated, and no display is made on the liquid crystal panel. After that, a synchronization signal corresponding to the set value from the CPU 2 is generated. With this configuration, the initial state of the display screen can be determined without controlling the power supply 24 for the liquid crystal display panel.

According to this embodiment, the control of the power supply for the liquid crystal display panel is provided by including the synchronization signal generation unit that outputs the synchronization signal for a certain period after the reset signal is released and clears the shift register in the liquid crystal display panel. The initial state of the display screen can be determined without performing.

FIG. 3 is a block diagram showing a circuit configuration of an LCD according to another embodiment of the present invention.

In FIG. 3, reference numeral 31 denotes a main circuit configuration block of the LCD of this embodiment, 32 denotes a first external synchronization counter that generates a signal in accordance with the cycle of an external signal, and 33 generates a signal in accordance with the cycle of an external signal. The second external synchronization counter, 34 is the first comparator 10
, A vertical synchronization signal, 36 is a second synchronization signal from the second comparator 13, and 37 is a horizontal synchronization signal. 1 is a liquid crystal display panel, 2 is a CPU, 4 is a VRAM, 6 is a display address counter, 7 is a data converter, 8 is a vertical counter, 9 is a vertical register, and 10 is a comparison between the vertical counter 8 and the vertical register 9. The first comparator, 11 is a horizontal counter, 12
Is horizontal register, 13 is horizontal counter 11 and horizontal register 12
These are the same as the conventional example. Reference numeral 24 denotes a power supply for the liquid crystal display panel, which is the same as that of the embodiment shown in FIG.

The operation of the LCD of this embodiment will be described with reference to the timing chart of FIG. First, the first synchronizing signal 34 as an output of the first comparator 10 is “L” before data is set in the vertical register 9 from the CPU 2, and when the vertical register 9 is set, the synchronizing signal of the cycle t 1 becomes the first synchronizing signal. It is output from the comparator 10.
The first external synchronization counter 32 receives the output 34 of the first comparator 10 and generates a vertical synchronization signal 35. Similar second comparator 13
Before setting data in the horizontal register 12 from the CPU 2,
This is “L”, and when the horizontal register 12 is set, a synchronizing signal with a period t2 is output. The second external synchronization counter 33 receives the output 36 of the second comparator 13 and generates a horizontal synchronization signal 37. At this time, when the output of the second comparator 13 is "L", the second external synchronization counter generates t3 having a period longer than t2, and when the synchronization signal 36 is input, the second external synchronization counter synchronizes with t2 to synchronize the horizontal synchronization. Generate signal 37. Subsequent operations are the same as in the conventional example. As described above, the output of the first external synchronization counter 32 is “L” unless a signal from the first comparator 10 comes, and the second external synchronization counter 33 outputs
Since a constant horizontal synchronizing signal is output unless a signal from the second comparator 13 is received, "L" is transferred to all bits of the first shift register 15 of the liquid crystal display panel shown in FIG.
The row side drive circuit 16 does not operate, and nothing is displayed on the liquid crystal panel. Therefore, it is not necessary for the CPU to control the power supply for the liquid crystal display panel.

According to this embodiment, the CPU is provided with an external synchronization counter for generating horizontal and vertical synchronization signals in synchronization with signals from the horizontal and vertical synchronization signal generators, which can set the period of the horizontal and vertical synchronization signals. As a result, after turning on the power and before the CPU sets the data in the register, a synchronization signal is output to the liquid crystal display panel to clear the shift register of the liquid crystal display panel, without controlling the power supply for the liquid crystal display panel. The initial state of the display screen can be determined.

FIG. 5 is a block diagram showing a circuit configuration of an LCD according to another embodiment of the present invention.

In FIG. 5, reference numeral 38 denotes a main circuit configuration block of the LCD of the embodiment, 39 denotes a synchronization switching register which can be set by the CPU 2 and switches the synchronization signal, and 40 denotes a vertical output which outputs a synchronization signal at a cycle t4. Synchronization generator 41, first comparator 10
And a first selector for switching the vertical synchronization generator 40, a horizontal synchronization generator for outputting a synchronization signal at a period t6, a second selector 43 for switching between the second comparator 13 and the horizontal synchronization generator,
44 is a switching signal from the synchronization switching register 39, 45 is a synchronization signal of a period t4 generated from the vertical synchronization generator 40, 46 is a first synchronization signal from the first comparator 10, and 47 is input to the liquid crystal display panel 1. A vertical synchronizing signal, 48 is a synchronizing signal with a period t6 generated from the horizontal synchronizing generator 42, 49 is a second synchronizing signal from the second comparator 13, and 50 is a horizontal synchronizing signal input to the liquid crystal display panel 1. 1 is a liquid crystal display panel, 2 is a CPU, 4 is V
RAM, 6 is a display address counter, 7 is a data converter,
8 is a vertical counter, 9 is a vertical register, 10 is a first comparator for comparing the vertical counter 8 and the vertical register 9, 11 is a horizontal counter, 12 is a horizontal register, and 13 is a second comparator for comparing the horizontal counter 11 and the horizontal register 12. These are the same as the conventional example in the two comparators. 24 is a power supply for the liquid crystal display panel,
This is the same as the embodiment shown in FIG.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. After turning on the power first,
The vertical synchronization generator 40 generates a clock with a period t4, and the horizontal synchronization generator 42 generates a clock with a synchronization axis t6. At this time, since data is not set in the vertical register 9 and the horizontal register 12, the synchronization signal which is the output of the first comparator 10 is output.
46, the value of the synchronization signal 49, which is the output of the second comparator 13, is undefined. When the switching signal 44 output from the synchronization switching register 39 is “L”, the first selector 41 outputs the vertical synchronization
The synchronizing signal 45 from the first comparator 10 is output as a vertical synchronizing signal 47 when the synchronizing signal 45 is output at a high level “H”. Similarly, the second selector 43
Is a switching signal 44 which is the output of the synchronization switching register 39
Is "L", the sync signal 48 from the horizontal sync generator 42 is output as the horizontal sync signal 50, and when "H", the sync signal 49 from the second comparator 13 is output as the horizontal sync signal 50. . Assuming that the output 44 of the synchronization switching register 39 becomes “L” after the power is turned on, the vertical synchronization signal 47 outputs the synchronization signal of the period t4 from the vertical synchronization generation unit 40, and the horizontal synchronization signal 50 is the horizontal synchronization signal. The synchronizing signal 48 of the cycle t6 is output from the generator 42. At this time, even if power is input to the liquid crystal display panel 1, the appropriate vertical synchronizing signal 47 and horizontal synchronizing signal 50, that is, the first comparator after the setting from the CPU 2 is completed as shown in FIG. 10, the first synchronizing signal 46 outputted from the second comparator 13, the period t _5, t ₇ from the longer period t _4, the vertical synchronizing signal generated 45 t ₆ of the second synchronizing signal 49, a horizontal sync generating signals 48 The vertical synchronization signal 47 and the horizontal synchronization signal 50 are input to the liquid crystal panel.
After the power is turned on, the LCD panel displays the vertical synchronization generation signal 4 with periods t ₄ and t ₆ longer than the correct data set by the CPU.
5, horizontal sync signal 48 is vertical sync signal 47, horizontal sync signal 5
Since it is input as 0, it is possible to prevent the display of a striped pattern caused by the selection of the next line before the display of one line of the liquid crystal panel.

Correct data from CPU2 in vertical register 9, horizontal register
By setting it to 12, and then setting the synchronization switching register 39 to "H", the intended correct display can be performed.

According to this embodiment, by providing a register for switching between a synchronization generation unit whose cycle cannot be set externally and a synchronization generation unit whose cycle can be set externally, the liquid crystal display panel can be set before the register is set. Since an appropriate synchronization signal is output, unnecessary stripe patterns are not displayed, and the initial state of the display screen can be determined without controlling the power supply for the liquid crystal display panel.

FIG. 7 is a block diagram showing a circuit configuration of an LCD according to still another embodiment of the present invention. In FIG.
51 is a main circuit block, 52 is a register access detection unit that detects completion of setting of a register from the CPU 2, 53
Is a vertical synchronization generator that outputs a synchronization signal at period t8, 54 is a first selector that switches between the first comparator 10 and the vertical synchronization generator 53, 55 is a horizontal synchronization generator that outputs a synchronization signal at period t10, and 56 is A second selector for switching between the second comparator 13 and the horizontal synchronization generator 55; 57, a switching signal from the register access detector 52; 58, a cycle t8 generated from the vertical synchronization generator 53;
59, a first synchronizing signal from the first comparator 10, 60 a vertical synchronizing signal input to the liquid crystal display panel 1, 61 a signal of a period t10 generated from the horizontal synchronizing generator 55, and 62 a second comparing signal. Vessel 1
The second synchronization signal from 3; 63 is a horizontal synchronization signal input to the liquid crystal display panel 1; 1 is the liquid crystal display panel;
Is a VRAM, 6 is a display address counter, 7 is a data conversion unit, 8 is a vertical counter, 9 is a vertical register, 10 is a first comparator for comparing the vertical counter 8 and the vertical register 9, 11 is a horizontal counter, and 12 is a horizontal counter. Register 13 is horizontal counter 11
And a second comparator for comparing the horizontal register 12 with the horizontal register 12. These are the same as the conventional example. Reference numeral 24 denotes a power supply for the liquid crystal display panel.

The operation will be described with reference to the timing chart of FIG. First, after the power is turned on, the vertical synchronization generator 53 generates a clock having a period t8, and the horizontal synchronization generator 55 has a period t1.
0 clock is being generated. At this time, the vertical register
9, since no data is set in the horizontal register 12, the values of the synchronization signal 59, which is the output of the first comparator 10, and the synchronization signal 62, which is the output of the second comparator 13, are undefined. When the switching signal 57 output from the register access detection unit 52 is "L", the first selector 54 outputs a synchronization signal 58 from the vertical synchronization generation unit 53.
Is output as a vertical synchronization signal 60, and when it is “H”, the first comparator
The synchronization signal 59 from 10 is output as the vertical synchronization signal 60.
Similarly, when the switching signal 57, which is the output of the register access detection unit 52, is "L", the second selector 56
The synchronization signal 61 from 55 is output as a horizontal synchronization signal 63,
At the time of “H”, the synchronization signal 62 from the second comparator 13 is output as a horizontal synchronization signal 63. Assuming that the output 57 of the register access detection unit 52 becomes “L” after the power is turned on, the vertical synchronization signal 60 outputs the synchronization signal 58 of the cycle t8 from the vertical synchronization generation unit 53, and the horizontal synchronization signal 63 is the horizontal synchronization signal. Period t1 from generator 55
The synchronization signal 61 of 0 is detected. At this time, even if power is input to the liquid crystal display panel 1, an appropriate vertical synchronizing signal
47, since the horizontal synchronizing signal 50 is input, no unnecessary stripe pattern is generated on the liquid crystal display panel 1.

Correct data from CPU2 in vertical register 9, horizontal register
When set to 12, the register access detection unit 52 operates,
Set the switching signal 57 to “H”. Then, the intended correct display can be performed.

As described above, according to the present invention, the initial state of the display screen can be determined without controlling the power supply for the liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a circuit configuration block diagram of an LCD according to an embodiment of the present invention,
FIG. 2 is a timing chart of the LCD of the embodiment, FIG. 3 is a block diagram of a circuit configuration of the LCD of another embodiment of the present invention, FIG. 4 is a timing chart of the LCD of the embodiment, and FIG. FIG. 6 is a timing chart of the LCD of the embodiment, FIG. 7 is a block diagram of a circuit configuration of the LCD of still another embodiment of the present invention, and FIG. 8 is a block diagram of the LCD of the embodiment. FIG. 9 is a block diagram of a circuit configuration of a conventional LCD, FIG. 10 is a configuration diagram of a liquid crystal display panel,
FIG. 11 is a timing chart of the conventional LCD. 1 ... LCD panel, 2 ... CPU, 3 ... Power supply for LCD panel, 4 ... VRAM, 5 ... LCD, 6 ... Display address counter, 7 ... Data converter, 8 ... Vertical counter , 9 vertical register, 10 first comparator, 11 horizontal counter, 12 horizontal register, 13 second comparator, 14
... M × N (M and N are positive numbers) dot liquid crystal panel, 15... First shift register, 16... Row side drive circuit, 17... Second shift register, 18... Latch, 19. Side drive circuit, 20
... First clock, 21... Second clock, 22... Data, 23... Third clock, 24... Liquid crystal display panel power supply, 25.
27 vertical sync generator, 28 reset signal, 29 vertical sync signal, 30 horizontal sync signal, 31 main circuit block of LCD, 32 first external sync counter, 33 Second
External synchronization counter, 34 ... synchronization signal from first comparator 10, 35 ... vertical synchronization signal, 36 ... synchronization signal from second comparator 13, 37 ... horizontal synchronization signal, 38 ... required for LCD Circuit block, 39: synchronization switching register, 40: vertical synchronization generator, 41: first selector, 42: horizontal synchronization generator,
43 second selector, 44 switching signal, 47 vertical synchronizing signal, 50 horizontal synchronizing signal, 51 LCD, 52, register access detecting section, 53 vertical synchronizing generating section, 54 …
First selector, 55: horizontal synchronization generator, 56: second selector, 57: switching signal, 60: vertical synchronization signal, 63:
... horizontal synchronization signal.

Claims (2)

(57) [Claims] 1. A first vertical synchronizing signal generator that can be set by a CPU, a second vertical synchronizing signal generator that generates a signal without using the CPU, and a first horizontal synchronizing signal that can be set by the CPU. A synchronization signal generator, a second horizontal synchronization signal generator that generates a signal independently of the CPU, and an output of the first vertical synchronization signal generator or an output of the second vertical synchronization signal generator. A first selector for selecting and outputting one of them, and a second selector for selecting and outputting one of the output of the first horizontal synchronizing signal generator and the output of the second horizontal synchronizing signal generator Wherein the cycle of the vertical synchronization signal output from the second vertical synchronization signal generator is longer than the cycle of the vertical synchronization signal output from the first vertical synchronization signal generator, and the second horizontal synchronization Of the horizontal sync signal output from the signal generator Longer than the period of the horizontal synchronizing signal period is output from the first horizontal synchronizing signal generation unit,
When the power is turned on, the CPU controls the first and second selectors to select an output from the second vertical synchronizing signal generator and the second horizontal synchronizing signal generator. When the setting of the first vertical synchronizing signal generator and the first horizontal synchronizing signal generator is completed, the CPU controls the first and second selectors so that the first vertical synchronizing signal generator and An output from the first horizontal synchronizing signal generator is selected. A register access detecting section for detecting completion of setting of a first vertical synchronizing signal generating section and a first horizontal synchronizing signal generating section by a CPU; The liquid crystal display device according to claim 1, wherein the liquid crystal display device controls a selector and a second selector.