JPS6031391B2 - Multiple image screen composition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiple image screen compositing device, and more particularly to a multiple image screen composing device for composing a plurality of television image screens onto a screen divided vertically and horizontally.

Conventionally, as shown in the system diagram of FIG. 1, an asynchronous image two-input signal screen synthesizing device uses a frame for synchronizing each of the two input signals 1 and 1' with a timing reference signal 19 for vertical and horizontal co-extraction.・Synchronizer device 29, 2
It consisted of two 9' units and a mix-and-key amplifier device 30.

In other words, a different type of synchronous input television image signal enters the video signal input terminal 1, and the frequency components of 5.38 MHz or higher in the input signal are band-limited by the input side low-pass filter 2, and then sent to the analog-to-digital (A/D) converter. 4 and is sampled at a frequency of 10.7 MHz and converted into PCM parallel n=(=8) bit data 5. Further, a write clock pulse 12 synchronized with the color burst of the input signal is generated by a write clock generator 11, and a write address signal 14 synchronized with the synchronization signal of the input signal is generated by a write address generator 13. The information for one field period of parallel n-bit data 5 is approximately 2.4 megabytes.
Each bit of data is written into the elastastic digital memory 6 at a location determined by the write address signal 14. On the other hand, a read clock pulse 12' synchronized with the color burst of the start timing reference signal (color black signal) 19 is generated by the read clock generator 11', and a read address signal 14 synchronized with the synchronization signal of the start timing reference signal 19. ' is generated by the proposed address generator 13'. Then, the PCM data in the memory 6 is read out using these read address signals and the read clock, and converted into a PAM signal by the D/A converter 8. The output side low-pass filter 2' removes spurious signals of 5.39 MHZ or more. A television signal 10 synchronized with the output timing reference signal, that is, synchronously converted, is obtained. Now, in the write address generator 13, a horizontal synchronization (H) pulse 21 is generated from the input signal 1 by an H pulse separator 20, and a vertical period (V) pulse 25 is generated from the input signal 1.
is produced by the V-pulse separator 24.

Then, from H pulse 21 and write clock pulse 12, H
In the address counter 22, the H address signal 23 is made to alternate from 0 to 227 or from 0 to 226 every day. Further, the V address counter 26 generates a V address signal 27 from 0 to 262 or from 0 to 261 using the V pulse 25 and the H pulse 21.

The H address signal 23 and the V address signal 27 are mixed by a horizontal/vertical (Japanese/V) address mixer 28 to produce a write address signal 14. On the other hand, a readout clock pulse 12' synchronized with the color burst of the readout timing reference signal (color black signal) 19 is generated by the readout clock generator 11'.
An output address 14' synchronized with the synchronization signal of is generated by an output address generator 13' and an H/V address mixer 28'. Then, the PCM data in the memory 6 is extracted by these input addresses and read clocks, converted into a PAM signal 9 by the ○/A converter 8, and the output side low-pass filter (LPF) 2' removes spurious signals of 5.39MH2 or higher. As a result, a television signal 10 synchronized with the read timing reference signal, that is, synchronously converted, is obtained from the frame synchronizer device 29. Furthermore, a horizontal synchronizing pulse separation circuit 20' is provided on the readout side in FIG.
, horizontal synchronizing pulse 21', horizontal address counter 22'
, horizontal address signal 23', vertical synchronization pulse separation circuit 2
4', vertical synchronization pulse 25', vertical address counter 2
6' and a vertical address signal 27' are shown. Also related to the memory 6 are a write/read control circuit 15, a write/read control signal 16, and a memory address selection circuit 1.
7, address signal 18 is shown. Similarly, another heterogeneous synchronous input television image signal 1' is also -
It enters another frame synchronizer device 29', and from the frame synchronizer 29' a synchronously converted television signal 10' is obtained.

Output signals 10 and 10' obtained from the two frame synchronizers 29 and 29' are combined by a mix-and-key amplifier 30 to obtain a combined output signal 31.

On the other hand, in FIG. 1, the mix-and-key amplifier 30, the D/A converter 8 in the second frame synchronizer 29', and the low-pass filter 2'
, the read clock generator 11' and the output address generator 13' are shared, and the first
FIG. 2 shows a system of a screen compositing device that can be provided at a lower cost than the device shown in the figure.

In FIG. 1, both H and V signals from each of the two 1-frame memories 6 and 6' are synchronously converted to a timing reference signal, converted to an analog signal, and then synthesized in a mix-and-key amplifier 30. In contrast, in FIG. 2, newly added data is a digital signal that has been output from devices 77 and 77' each containing one frame memory, and has been synchronously converted to a timing reference signal from both H/V. This device synthesizes screens using a selector 32 and a signal selection controller 33, and then converts the images into analog signals. However, both of the asynchronous image two-input signal screen synthesizing devices shown in FIGS. 1 and 2 have the disadvantage that they must have two 1-frame memories 6, 6' with a large capacity of 2.4 megabits. In order to realize a four-input asynchronous image reduction/screen compositing device, each one frame memory 6 in FIG. 1 or FIG. 2 is used as a thinning memory for reduction and as an elastic memory for synchronous conversion. Both had the disadvantage of requiring four 2.4 megabit large-capacity one-frame memories. The purpose of the present invention is that even when the number of asynchronous image inputs is n, there is only one large capacity memory, and the rest is of a small capacity (1
An object of the present invention is to provide a multiple image screen composition device that can be realized by using a memory of 9 kilobits.

The present invention includes a write address generator that generates synchronized vertical and horizontal addresses for each of a plurality of asynchronous images, and a write address generator that simultaneously writes both the image input and its vertical address and first synchronizes them simultaneously in the horizontal direction. A first elastic memory group characterized in that the plurality of horizontally synchronized images obtained from the first elastic memory group and their plurality of vertical addresses are synthesized by time sharing. By using the selection circuit and the selectively synthesized vertical address as the write address of the second elastic memory, and writing the selectively synthesized image to the Z second elastic memory, By providing a synchronizing circuit, it becomes possible to synthesize a plurality of asynchronous images into a synchronized screen both horizontally and vertically. In the above configuration, there is also a screen position variable setting data generator that generates position setting data that controls both the vertical and horizontal positions of each Z screen after multiple screens are combined, and a vertical address generator for each of the multiple asynchronous images. and a write horizontal address generator of the first elastic memory. Both the rustic memory can serve as a screen reducer and a synchronized conversion screen synthesizer.

In the present invention, when synthesizing n asynchronous image inputs without processing such as image reduction, it is possible to synthesize images using one large-capacity memory and (n-1) small-capacity memories. Synthesis is possible. Furthermore, if processing such as image reduction is involved, one large capacity memory and n small capacity memo IJs are required. The input number n of asynchronous images are all horizontally synchronized in the small-capacity first elastic memory, but
Vertically, everything is asynchronous. However, if you send out a large capacity second elastic memo with a vertical address instead of a writing destination display label for those asynchronous PCM data, you can easily find the vertical address to be written to. Since PCM data is written, vertically synchronized PCM data is also obtained from the second elastic memory. Let me explain the first thing. FIG. 3 is a system diagram of the asynchronous image two-input signal vertically split screen synthesizer. Asynchronous image 2 inputs 1, 1'
From A/D converter 4 write clock generator 1 1,
PCM data 5, 5' and vertical address 2 synchronized with 2 inputs 1, 1', respectively, in A/D converter & write address generator 35, 35' including write address generator 13, etc.
7, 27', horizontal address 23, 23', horizontal pulse 2
1,21' is obtained. The PCM data 5' synchronized with the second asynchronous image input 1' and the vertical address 27' are input as write data to the small capacity cape buffer memory 36 of 19 kilobits as the first error stick memory, and the horizontal address If 23' is used as the write address of the H buffer memory and the horizontal address 23 is used as the starting address of the Yamahi buffer memory, the first asynchronous image input 1 is horizontally synchronized from the 4-day buffer memory. PCM data 38 and vertical address 39 are obtained. Here, input image 1 is placed on the left of the screen after compositing,
When the input image 1' is to the right, the signal selection controller 3
Switching control may be performed at step 3'. In other words, the data selector 32 selects the PCM data 38 and the address selector 32' selects the vertical address 39 for a period corresponding to the right half of the screen.
Conversely, in the period corresponding to the left half of the screen, the data selector 32
may select PCM data 5, and address selector 32' may select vertical address 27. Selection section 32, 3
2' is in the selection section 34. These controls are controlled by control pulse 3.
It is done by 7. The PCM data 40' selectively combined in this way is input as write data to the one frame memory 6 as the second elastic memory, while the selectively combined vertical address 41 is input to the H/V The address mixer 26 further mixes the horizontal address 23 and supplies it to the one frame memory 6 after passing through the memory address selector 17 as the write address 14 of the one frame memory 6. During the period when the PCM data 38 corresponding to the second image input is being input as the write data of the one frame memory, the vertical address 39 corresponding to the second image input is also the write address of the one frame memory. After writing to this 1 frame memory, the PCM data in the memory 6 is read out using the start clock 12' synchronized with the read timing reference signal 19 and the start address 14', and the D/ A converter 8
, LPF2', the first and second asynchronous images 1,1
A television signal output 10 is obtained in which the left and right halves of the signal ' are combined and synchronously converted in both the horizontal and vertical directions.

FIG. 4 is a specific system diagram of the day buffer memory 36 in FIG.

The write/issue date control circuit 45 prevents the memory of any day in the cape memory 43 from performing a write operation and an issue operation at the same time. That is, a writing mountain day counter 46, a reading 4-day counter 46', and writeable pulses 55, 55', 55 from these 4-day sequences are used to independently create a 4-day sequence on the writing side and on the sending side.
'', 55''' and arguable pulses 56, 56', 56
A writeable date decoder 47, a readable date decoder 47' for producing ``, 56...'', and a write/read date phase coincidence detector 48 for detecting the approach of the writeable pulse 55 and the readable pulse 56. and an exclusive OR circuit 52 for exchanging each bear on the writing side by detecting a detection pulse 57. Here, exchanging every single bear is based on NTSC. There is a relationship between the sub-carrier frequency $c of the color television signal and the horizontal synchronization frequency fH as fSC = 455 x K fH, and since the number of sub-carriers is an integer in the pan-period, it is possible to prevent phase changes during exchange. This is because the write/read address selector 44 selects the write date address 23' of the IH memory during the period when the write enable pulse 55 exists in the IH memory 42, and selects the write date address 23' of the IH memory during the period when the write enable pulse 56 exists in the IH memory 42. Select the start date address 23 of the memory 42 and send it as the address of the IH memory 42.In the 4th day memory 43, PCM data 5'
and vertical address 27' at the same time, in synchronization with the write date pulse 21'', that is, the second image input 1', and the readout H
If read in synchronization with the pulse 21, that is, the first image input 1, the PCM data 3 synchronously converted to the first image input 1
8, each of the vertical addresses 39 can be obtained.

FIG. 5 is a system diagram showing an embodiment of an apparatus for reducing four asynchronous image input signals to 1/2 both vertically and horizontally and synthesizing the screen.

The first asynchronous image input 1' is converted into PCM data 5 via the LPF 2 and the A/D converter 4, and then input to the image reduction control circuit 75. First, both length and width are 1'2
If you only want to reduce the size to
This can be realized by thinning out PCM data one by one for every two subcarriers in the horizontal direction. However, in this embodiment, before the PCM data 5 is thinned out horizontally in the H buffer memory 36 and vertically in the one frame memory 6, first, two scanning lines located vertically adjacent to each other are first thinned out. Vertical interpolation data 6 containing information on both
2 is generated by the vertical interpolation circuit 61, and then horizontal interpolation data 64 is generated in the horizontal direction by the horizontal interpolation circuit 63, so that a reduced image with good continuity and linearity in both the vertical and horizontal directions can be obtained. The horizontal thinning method is to double write within the same address in the 4-day memory by slowing down the change speed of the write horizontal address 74 of the calm buffer memory 36 to 1/2 with the H slow address generator 73. This is done by In other words, by double writing, PCM data 38 reduced in size to 1/2 in the horizontal direction is obtained. Similarly, the vertical thinning method uses a vertical countable pulse thinning generation circuit 67 and a vertical address generator 26 to change the speed of change of the write vertical address 39 of one frame memory 6 to 1.
'2, double writing is performed within the same address in the 1-hum memory, and as a result, the vertical direction is also reduced by 1/2.
PCM data 7 reduced to 2 is obtained. 2nd, 3rd,
Similarly, for the fourth asynchronous image input 1', 1'', 1 river, an A/D converter/write address generation section 35, an image reduction control section 75, and a 4-day buffer memory 36 are constructed. Write-side circuit blocks 76', 76'', 76 are provided, horizontally reduced from the circuit blocks 76', 76'', 76''' and synchronously converted to the first input signal 1. The resulting PCM data 38', 38'', 38''' are synchronously converted to the first input signal 1 with the change speed delayed to 1/2, and the vertical addresses 39', 39'',
39 skin is obtained. Here, the regular size screen before reduction is divided into four parts vertically and horizontally, and the upper left, upper left, lower left, and lower right screens are named A, B, C, and D, respectively, and the first input signal 1 is A, the second input signal is The third input signal 1' is B, and the third input signal 1'' is C.
, the case where one fourth input signal is synthesized at the screen position D will be described. In this case, the signal selection controller 33' includes the PCM data 4 inputs 38, 38', 38'', 38''' and the vertical address 4 inputs 39, 39', 39'', 39 river selector 3.
4' outputs a control pulse 37' so as to cycle through the four input signal selections every two days. In other words, the control pulse 37' selects A for the left half of the first day of the phantom cycle, B for the right half of the first day, C for the left half of the second day, and D for the right half of the second day. a horizontal pulse 21 synchronized with the first input signal;
Created from vertical pulse 25. On the other hand, in this case, in order to position the horizontally reduced effective PCM data 38, 38' on the left half of the screen, and position 38', 38''' on the right half of the screen, horizontal position variable setting data is generated. The setting data 70 from the device 69 is controlled to be sent to the H slow address generator 73.

Similarly, PCM data 38, 38' are displayed in the upper half of the screen.
8'', 38 controls sending setting data 66 from the vertical position variable setting data generator 65 to the vertical address generator 26 in order to set the lower half position of the screen. If the data 40, selectively synthesized vertical address 41 and horizontal address 23 are sent to the six hummum memory and readout side circuit blocks, a television signal output 10 which has been reduced and screen synthesized will be obtained.

Note that the writing side circuit blocks 76, 76', 76'' in FIG.
, 76''', the horizontal pulse 21 synchronized with the first input signal 1 and the horizontal address 23 are used as the read timing reference signals for all 4H buffer memories in the 4H buffer memories in the 4H buffer memories in the 4H buffer memories 76''', and the horizontal pulse 21 and the horizontal address 23 synchronized with the first input signal 1 are used as the control reference signal for the signal selection controller 33''. 21,
By using the vertical pulse 25 and the horizontal address 23 as the horizontal write reference address of the frame memory & readout side circuit block 60, the PCM from the second, third, and fourth input signals 1', 1'', and 1 river is A method of synchronizing all data and vertical addresses with the first input signal has been described for the sake of continuity and ease of explanation from FIGS. 1 to 5. In this method, the first input signal 1 is If a so-called "cut change primary synchronization signal discontinuity occurs, A, B, C, D
All of these have the disadvantage of introducing shock noise.
However, the writing side circuit blocks 76, 76', 76'', 7
The horizontal pulse 21' horizontal address 23' synchronized with the output timing reference signal 19 is used as the output timing reference signal for all the 4-day buffer memories in the six streams, and the horizontal address 23' is also used as the control reference signal for the signal selection controller 33''. By using the pulse 21', the vertical pulse 25', and the horizontal address 23' as the horizontal write reference address of the frame memory & read-out side circuit block, the first, second, third, fourth input signals 1, 1', It is clear that the PCM data and vertical address from the 1'', 1 river can all be synchronized with the read timing reference signal 19, and the device eliminates the drawback of the shock noise mixed in. As explained above, the present invention uses (n-1) small-capacity memories together even when the number of asynchronous signal inputs is n, and synchronizes data and addresses simultaneously, so that only one large-capacity memory is required. This has the effect of providing an inexpensive and simple screen compositing device.

Furthermore, by using n small-capacity memories, it can serve both horizontally and vertically as a thinning buffer memory for reduction and as an elastic memory for synchronization, which has the effect of providing an inexpensive and simple reduction and screen compositing device. .

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a conventional asynchronous image 2 input signal screen synthesis device, FIG. 2 is a system diagram of a screen synthesis device that can be provided at a lower cost than that in FIG. 1, and FIG. A system diagram of the input signal vertically split screen synthesizer, Fig. 4 is a specific system diagram of the 4-day buffer memory in Fig. 3, and Fig. 5 is a system diagram of the asynchronous image 4.
FIG. 1 is a system diagram showing an embodiment of an input reduction/screen synthesis device. Ship map to Tsugou map - Female map of a small shrimp ball

Claims (1)

[Claims] 1 A device that synthesizes multiple input television signals with undefined synchronization relationships on a screen, which includes an A/D converter that converts each of the multiple input television signals into digital image signals, and an A/D converter that converts each of the multiple input television signals into digital image signals. vertical address generating means for generating synchronized vertical addresses, horizontal address generating means for generating horizontal addresses synchronized with the converted digital image signals, and converting the digital image signals and their vertical addresses at their horizontal addresses; a first elastic memory group for simultaneously writing and reading at a predetermined horizontal address; a control means for reducing changes in at least one of the predetermined horizontal address and the vertical address; and a control means for reading from the first elastic memory group. a selection circuit that selects the output digital image signal and its vertical address by time sharing; and a selection circuit that stores the digital image signal from the selection circuit according to the predetermined horizontal address and the vertical address from the selection circuit. a second elastic memory; a read control means for reading out the second elastic memory in synchronization with a reference; 1. A multiple image screen compositing device comprising screen position control means for determining the position of a signal on a screen.