JPS60245055A - Decision device for write area of main storage device - Google Patents

Abstract

PURPOSE:To speed up retrieval for a blank area in the main storage device and write processing by providing a main storage controller with a stack and a CPU with a holding device for the size of an area. CONSTITUTION:When a request to write data in a blank area of the main storage device MM1 is generated nearly, the main storage controller MMC2 writes the head address of the blank area 4 of the MM1 in the stack 6 through a pointer 10. A CPU13 stores a register 15 with the total of the size of the blank area stored in the stack 6 and the size of a blank area whose that address is indicated by the pointer 10. At this time, when a request to write (n) byte data is generated, the CPU3 sends it to a buffer 12 and it is compared with the contents of the register 15. When the comparison result (n) is less than the said contents, writing operation is started immediately and when (n) is larger than the said contents a blank area is reconstituted in the MM1 having unnecessary areas, and the value of the register 15 is varied to a value larger than (n); and the writing of a data quantity (n) is started and (n) is subtracted from the value of the register 15, so that next operation is held in readiness.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a write area determination device that can search and write to a blank area in a main memory of an information processing system at high speed.

(2) Prior art and problems In FIG. 1, which shows the basic configuration of an information processing system, a main memory controller 2 connected between a main memory 1 and a central processing unit 3 receives instructions from the central processor 3. Correspondingly, the operation of the main storage device 1 is controlled.

The conventional main memory control device 2 has a large number of registers called pointers 21, 22-, and areas 101, 102-, and 102-, where new data can be written in the main memory 1.
- indicates the address. This area 101, 102=
* may be not only an area in which no data has been written, but also an area for data that has already been written and will not be reused. Pointer 21 indicates the start address of area 101,
Since each area is usually equal in size, the end address of area 101 is a value associated with pointer 21. If area 1.02 follows area 101, write at the end of area 101 that the pointer to which the start address of the next area 102 is set is "22" (. Pointer "22" points to the start address of area 102 in advance.

Further, at the end of the area 102, it is written that the start address of the area 103 exists at the pointer "23".

When writing this amount of data to the main storage device 1, the central processing unit 3 first reads the value of the pointer 21, specifies the address of the main storage device 1, and uses the blank area 101 sequentially. Write data.

At the end of the area 101, data is read out, the start address of the next usable area 102 is obtained by the 6 pointer 22 pointed to by the pointer 22, and the writing operation is repeated. In this method, it is necessary to repeatedly read the pointer as the area changes with writing, resulting in an operational overhead for the central processing unit 3 and a decrease in efficiency.

(3) Object of the Invention An object of the present invention is to provide a write area determination device which can improve the above-mentioned drawbacks and can perform a search for the existence of a blank area in a main storage device and a writing process at high speed.

(4) Configuration of the Invention The configuration of the present invention for achieving the above-mentioned object is that a central processing unit and a main storage device are connected via a main storage control device,
In a main memory of an information processing system in which write areas in the main memory are controlled to be linked by pointers, a stack is provided in the main memory control device, an area size holding device is provided in the central processing unit, The former involves the main memory controller searching for a blank area in the main memory and retaining the address of part or all of the blank area, and the latter retaining the size of the usable blank area. .

(5) Embodiment of the Invention FIG. 2 is a block diagram showing the configuration of an embodiment of the invention. ■ is the main memory, 2 is the main memory control unit, 3 is the central processing unit, 4 is the blank string area in the main memory (meaning that the writable area is continuous), 5 is the main memory control unit 2 a control unit, 6 a stack of write area addresses, 7 a write register, 8 a read register, 9
is a main memory address register, and 10 is a register for a pointer indicating the beginning of the blank string area 4.

11 is a central processing unit 30 control unit, 12 is a write data buffer, 13 is a write register, 14 is a read register, 15 is a register that holds the size of the blank string area 4, 16 is a register, and 17 is an arithmetic unit. ,1
8 is a second stack, 19 is a stamp counter, and 20 is a byte number register. The line connecting the control unit 5 of the main storage control device 2 and the control unit 11 of the central processing unit 3 is a signal transmission line, and the content and explanation of the signal will be described later.

As the operation in FIG. 2, a write operation to a known address will first be explained. The central processing unit 3 has a write register 13
After setting the address to MSCRQ.

The ADW signal is sent to the main memory control device 2.

MSCRO is a signal that is always sent at the beginning when the central processing bag M3 starts processing for the main memory control device 2, and ADW is a signal indicating that data such as an address has been set in a register. The main memory controller 2 then sets d data in the register 13 for writing. At this time, the central processing unit 3 sends the MSC to the main memory control unit 2.
Sends RQ, MS, and W signals. MS is a signal indicating current writing/reading to the main memory device 1, W
follows the MS signal (means a write enable signal. Next, the main memory controller 2 transfers the data set in the register 13 to the write register 7, and writes the data to the main memory 1 according to the address indicated in the address register 9. Write to.

When the writing is completed, the main memory control device 2 sends a MEND signal to the central processing unit 3. Next, in the case of reading, after the address is set in the address register 9, the central processing unit 3 sends the MSCRQ,
Sends M S and R signals.

Here, R is a signal meaning read, and the data at the designated address is read to the read register 8. Next, the data is transferred to the register 14, and upon completion, a MEND signal is sent to the central processing unit 3.

Next, an explanation will be given of the operation when a new data write request is made to a blank area of the main storage device 1.

Prior to the start of operation, the main memory control device 2 uses its control unit 5 to sequentially write the start address of each of the blank areas 4 in the main memory device 1 into the stack 6 via the pointer 10 . At this time, the step counter 19 is used to sequentially change the addresses of the stack 6. For example, a blank area is searched for from small to large in terms of addresses and stacked on a stack 6, and if there is any remaining space, a pointer 10 is made to point to the start address of the blank area. The central processing unit 3 stores in the register 15 the sum of the size of the blank area stacked on the stack 6 (unit number of bytes x number of areas) and the size of the blank area with the pointer 10 as the top address. If a write request for n bytes of data occurs here, the central processing unit 3 transfers the data to the write data buffer 12 and compares the value of n with the contents of the register 15. If the result of the comparison is that n is smaller, the write operation is started immediately. If n is larger, there is a shortage of writeable area in the main storage device l, so the garbage collector is activated. A garbage collector is a program that reorganizes files in the main storage device 1 that has so-called unnecessary areas, such as used data stored in gaps between blank areas. The central processing unit 3 starts this program, reorganizes the blank area, and performs 1. As a result, the value in register 15 is changed to a larger value. Normally, at this stage, n is smaller than the value of the blank area. Therefore, the operation moves to write the data amount n, so n is subtracted from the value of the register 15, and the process waits for the next operation. In the conventional device, the size relationship between the amount of data and the size of the blank area could not be determined at the beginning, and the writing operation was started. For this reason, it was sometimes necessary to interrupt processing and perform garbage collection in the middle of data writing, but according to the present invention, the initial judgment can be made.

For a write operation to the main memory device 1, the central processing unit 3 sends MSCRQ, S TW to the main memory control device 2.
, transmits LNG signals. STW indicates a write control signal to a blank area, and LNG indicates the number of bytes of data to be written.

The main memory controller 2 sends the data length to the byte number register 20 in the controller 5 using the signal LNG, and sends LIST-WR to the central processor 3 to match the operation timing.
Sends ITE signal.

When the central processing unit 3 receives this signal, it transfers the words from the buffer 12 to the register 13 one by one, and starts transferring the words to the register 7. The main memory controller 2 sets an address from the stack 6 to the address register 9, and writes the data transferred to the register 7 from the original blank area of the main memory 1 accordingly. Furthermore, the control section 5 of the main memory control device 2 subtracts the value of the register 20 by the word length when writing is completed. When this operation is repeated and the register 20 becomes zero, the write process is completed and the control unit 5 of the main memory control device 2 notifies the central processing unit 3 of the MEND signal. It is normal operation that some addresses remain in the stack 6. Thereafter, in order to return to the initial state, the main memory controller 2 searches for a blank area in the main memory 1, reorganizes the contents of the stack 6, and sets the pointer value of the register 10 if necessary. The above operation timing chart is shown in FIG. In FIG. 3, the upper half shows the operation of the central processing unit 3, and the lower half shows the operation of the main memory control device 2. That is, when the central processing unit 3 performs a write operation to the main memory device 1, it issues the MSCRQ, STW, and LNG signals at the times indicated by the arrows and sends them to the main memory control device 2. The main storage control device 2 sets the data length n in its byte number register 20, and sends a LIST-WRITE signal from the main storage control device 2 to the central processing unit 3. Thereafter, the central processing unit 3 sends the data one word at a time and sequential addresses to the main memory control unit 2, so that the data is written to the predetermined address one word at a time. When the process is finished, a MEND signal is sent to the central processing unit 3.

While the main storage controller 2 is being set to the initial state, the central processing unit 3 may start the next write operation. At this time, when the main memory control device 2 receives the MSCRQ signal, it immediately interrupts the setting operation, and because the timing matches, the LI
It is sufficient to send the ST-WRITE signal to the central processing unit 3.

Furthermore, if the next write processing request occurs immediately after the values stored in the register 15 of the central processing unit 3 have been sorted out after the write is completed, the address reset in the stack 6 of the main memory control unit 2 is completed. However, the write process is restarted. In that case, the addresses accumulated on the stack 6 of the main memory control device 2 may be used up during the write operation to the main memory device 1. In that case, you cannot continue the operation as before, and the pointer 10
As in the case of the conventional device shown in FIG. 1, the blank area in the main memory device 1 indicated by is searched and written to. Therefore, the cycle of the write operation must be slower than the cycle described with respect to FIG. That is, as shown in the timing chart of FIG. 4, the main memory controller 2 is sending the address of the stack 6 to the address register 9, and when the address is exhausted at address i, it sends the signal ^ST-HMPTYT to the central processing unit 3. . The central processing unit 3 interrupts the transfer of data after data (i+1) in response to the signal, and restarts the operation by sending a signal MCG that matches the predetermined timing to the main memory control unit 2. After receiving the signal MCG, the main storage control device 2 performs an operation corresponding to the timing. That is, data (i+
2) and moves to writing at a slower timing cycle than before.

Note that although a real storage device is used as the main storage device in the above description, the same operation can be performed for a virtual storage device.

(6) Effects of the Invention In this manner, according to the present invention, a register provided in the central processing unit that holds the size of the area can determine whether or not there is sufficient blank area for data to be written in the main memory. You can make a decision just by looking at it. Furthermore, there is no need to access the main memory each time to know the address of the area to be written. Therefore, when writing data into a blank area of the main memory, determination and writing operations after data arrival can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a conventional information processing system, FIG. 2 is a block configuration diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a timing chart explaining the normal operation of FIG. FIG. 4 is a timing chart illustrating the operation to be changed when the stack is used up during the operation in FIG. 2. - Main memory device 2 - Main memory control device 3 - Central processing unit 4 - Blank area 6 - Blank area address stack lO - Pointer register 15 - Blank area size holding device Patent applicant Fujitsu Limited Agent Patent attorney Eisuke Suzuki 1 2 3 Figure 1

Claims (1)

[Claims] In the main memory of an information processing system in which the central processing unit and the main memory are connected via the main memory controller, and the write areas in the main memory are controlled to be linked by pointers, The central processing unit is provided with a stack, and the central processing unit is provided with an area size holding device, and in the former, the main memory controller searches for blank areas in the main memory and holds the addresses of some or all of the blank areas. A write area determining device in a main memory of an information processing system, wherein the latter holds the size of a usable blank area.