JPH0376501B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Examples Effects of the Invention [Summary] At least central processing Controls the device (CPU), channel processing unit (CHP), main storage unit (MSU), expanded storage unit (ESE), and the interface between storage control and central processing unit (CPU)/channel processing unit (CHP). In a computer system consisting of a storage control unit (MCU), we focused on the fact that data transfer between the extended storage unit (ESE) and the main storage unit (MSU) is in page units. ESE) and a data buffer (for example, 1 page/4 KB) are provided, and a data buffer of a certain size (for example, 64 bytes) is provided on the memory control unit (MCU) side to control the memory. After the device (MCU) starts the extended storage device (ESE) (sends the activation signal S), the ESE control section on the storage control device (MCU) side starts the data buffer on the storage control device (MCU) side. After confirming that it is not full or that data has been loaded from the main storage unit (MSU), send a data transfer request (SYNC DATA) again, and respond to the sent data transfer request (SYNC DATA). By transferring data between the respective data buffers in the extended storage device (ESE) and the storage control unit (MCU), it is possible to transfer data in units of, for example, 8 bytes.

[Industrial application field]

The present invention consists of a main memory unit (MSU) made up of relatively high-speed elements, and an expanded storage unit (ESE) made up of elements that sacrifice high speed to some extent because they are required to be low cost. It relates to a control method for transferring data in page units (for example, 4KB) between

With the recent trend of online computer systems, the construction of so-called TSS systems in which many users share and use one computer system has become popular, and depending on the response content,
Slow response times from the user's perspective have become a problem.

Generally, in a TSS system, the user's memory usage area is in the file memory (DASD), and even if the fastest file memory (DASD) is used at present, the memory usage area for the user is in the channel processing unit (CHP). Therefore, the data transfer speed is limited to a maximum of 3MB/S.

Therefore, an economical and large-capacity storage device (expanded storage device (ESE)), which is slower than the main storage device (MSU) but is economical, is provided, and the user area is divided into file memory (DASD) and the expanded storage device (ESE). ESE).

And usually the file memory (DASD)
Only initial loading of data from the file memory (DASD) to the expanded storage device (ESE) is performed, and subsequent data transfer between the file memory (DASD) and the expanded storage device (ESE) is avoided as much as possible.

Therefore, data from the main storage unit (MSU) is stored in the expanded storage device (ESE) rather than the file memory (DASD), and when data stored in a certain file memory (DASD) is needed, By reading data from an extended storage device (ESE), it has become possible to improve the response time seen by the user by one to two orders of magnitude.

However, controlling access to the extended storage device (ESE) in the same way as the main storage device (MSU) is difficult in terms of hardware due to the difference in access time and cycle time. There is a growing demand for effective data transfer methods.

[Conventional technology]

FIG. 5 shows an example of the system configuration of a general data processing device. MSU #1) 4 (hereinafter referred to as MSU #0 to #3)
1 or the expanded storage device (hereinafter referred to as ESE) 6, the storage control unit (hereinafter referred to as
In the MCU (MCU) 2, after being received at a port corresponding to each device, it is prioritized and processed. Incidentally, a service processor (SVP) 5 is a device in charge of maintenance and operation of this system.

FIG. 6 shows the data processing device in FIG.
This is a block diagram showing the main memory access control section within the MCU 2.

First, CPU (#0, #1) 3 or CHP (#0,
#1) An access request (REQ) to MSU 4 (#0 to #3) 1 is sent to the corresponding port 2.
1, 22, priority circuit (P) 2
3 selects one of them, and MSU (#0 to #3) 1
Activate access to.

Control information related to the activated access (for example, operation code, lock flag, valid bit, request source number, etc.), address, and if the access is a partial write, the write data is sequentially composed of N stages of shift registers. It is held in the pipeline 240 and used to control main memory access.

The access that started MSU (#0 to #3) 1 is
For fetch operation, start from MS ADDR250.
After a certain timing after the address for MSU (#0 to #3) 1 is sent, MSU (#0 to #3)
Fetch data is read from 1 through FETCH DATA 252, passed through DATA MERGE 254, checked and corrected by ECC FCH 253, and then sent to each CPU (#0, #1) 3, CHP.
(#0, #1) is sent to 4.

The access that started MSU (#0 to #3) 1 is
During store operation, start from MS ADDR250 above.
After the address for MSU (#0 to #3) 1 is sent, the store data is stored in ECC ST253.
ECC code is added and after a certain timing,
Through STORE DATA251, MSU (#0~
#3) Sent to 1.

When the above store operation is a partial write, the partial write data held in the pipeline 240 is sent to the MSU through the FETCH DATA 252.
(#0 to #3) The data read from 1 and
After being merged with DATA MERGE254, ECC
ECC code is added in ST253 and STORE
Stored in MSU (#0 to #3) 1 through DATA 251.

When the above store operation for MSU (#0 to #3) 1 is performed, each
Buffer memory (BS) in CPU (#0, #1) 3
The invalidation processing request for each CPU (#0, #1)
Sent on 3rd.

Also, when a 1-bit error, etc. is detected in the ECC FCH253, the address is stored in the register.
Each CPU through FSAR260 and GPBR262
(#0, #1) 3 and operates to enter machine check interrupt processing.

The above explanation was given as an access operation for MSU (#0 to #3) 1, but ESE6 mentioned above also
As is clear from Fig. 6, MSU (#0~
#3) Connected to the same location as 1, MSU
(#0 to #3) The only difference from 1 is the address, access time, and cycle time.

Therefore, for data transfer from MSU (#0 to #3) 1 to ESE 6, for example, a page transfer instruction is issued from CPU (#0, #1) 3, accepted by port 21, and transferred to the priority circuit. By selecting (P)23, MSU (#0 to #3)1 and ESE
6 each, MS ADDR250, ESE
Address information is sent via ADDR250', and the data read from FETCH DATA252 is sent to DATA MERGE254, ECC FCH
It was transferred through 253.

Similarly, from ESE6 to MSU (#0 to #3) 1
Data transfer to FETCH DATA252,
DATA MERGE254, ECC ST253,
This was done through STORE DATA251.

[Problem that the invention seeks to solve]

Therefore, in the conventional method, two types of storage devices are connected to the MCU 2 at the same location, and their access times, cycle times, and therefore busy times are different, making data transfer control complicated.

Access requests to the MSUs (#0 to #3) 1 and the ESE 6 undergo unpredictable "waiting" due to their respective busy states, making it difficult to perform efficient data transfer.

There was a problem.

In view of the above-mentioned conventional drawbacks, the present invention has been proposed to improve the appearance of ESE.
The purpose of this invention is to provide a method for efficiently transferring data without being concerned with the access time, busy time, etc. of 6.

[Means for solving problems]

FIG. 1 is a principle block diagram of the ESE access unit of the present invention, in which data transfer between MSU (#0 to #3) 1 and ESE 6 is performed in blocks of pages that are continuous in the forward direction of addresses. Focusing on the following points, (1) the ESE6 has a sufficient number of banks 60 and a data buffer (4KB/page) 61, (2) the MCU2 has the following functions for data transfer with the ESE6:
A data buffer 27 of a certain size (for example, 64 bytes) and an ESE control unit (ESE CTL) 28
(3) First, based on instructions from the pipeline 240, the ESE control unit (hereinafter referred to as ESE CTL)
28 sends a signal S that activates access to ESE 6, after a certain period of time (depending on the access time for each bank 60 of ESE 6)
The configuration is such that a data transfer request (SYNC DATA) is sent to the MSU (#0 to #3) so that data transfer can be performed with attention only to the state of the MSU (#0 to #3) 1 side.

Specifically, (a) In the case of page-in (ESEMSU): 1 The ESE CTL 28 of the MCU 2 sends the access activation signal S and the page address to the ESE 6. The ESE 6 sends the page address to the address register ( After setting the address register (AR) 62 to +1,
The data addressed to 8 bytes is stored in the data buffer 61.

2 The ESE CTL 28 in the MCU 2 confirms that the data in the data buffer 27 is not full and sends a data transfer request (SYNC DATA) to the ESE, taking into account the maximum access time of the ESE 6.
Send on 6.

3 In ESE6, from the data buffer 61, 1
For each SYNC DATA, data is transferred to the data buffer 27 of the MCU 2, addressed to 8 bytes.

4 When the 8-byte data is transferred, the data buffer 27 of the MCU2 handles the corresponding data.
Send to CPU port 21.

At this time, if the priority (P) cannot be obtained, the data buffer in the MCU 2 becomes full, and the sending of the above-mentioned "SYNC DATA" is interrupted.

After that, 1 page (4KB) of data will be transferred to ESE.
The same operation is repeated until the data is transferred from the data buffer 61 of No. 6 to the data buffer 27 of MCU 2.

(b) In the case of page out (MCUESE): 1 Based on the instructions from the pipeline 240,
The MCU 2 sends a store access activation signal S to the ESE 6, and the start address of the storage page is sent to the address register (AR) 6.
2, and issues a load request to MSU1.

The data fetched from MSU1 by the load request is stored in data buffer 27 in MCU2.

2 Every time 8 bytes of data is stored from MSU1 to the data buffer 27, ESE CTL2
8 is the data buffer 61 of ESE6 = SYNC
DATA” and sends 8 bytes of data to the corresponding
Transfer to data buffer 61 of ESE6.

3 On the ESE6 side, unless the data buffer 61 is empty, the address registers (AR) 62 are
1, activate each bank and store the data.

After that, in the same way, 1 page (4KB) of data is transferred from the data buffer 21 of MCU 2 to ESE.
The same operation is repeated until the data is transferred to the data buffer 61 of No. 6.

Therefore, (a) In the case of page-in, the write data to MSU1 is always
It will exist in the data buffer 27 of the MCU 2.

(b) In case of page-out, each time data is stored from MSU1, ESE
6, the above data transfer request (SYNC
DATA) and the contents of the data buffer 27 are transferred to the data buffer of the ESE6, so the data buffer 27 of the MCU2 has the following information:
There is always "vacancy" and the fetch data from MSU1 can be set.

There is a characteristic called.

[Effect]

That is, according to the present invention, at least a central processing unit (CPU), a channel processing unit (CHP), a main storage unit (MSU), an expanded storage unit (ESE), and a storage control and central processing unit (CPU)/channel In a computer system consisting of a storage control unit (MCU) that controls the interface between processing units (CHP), data is transferred between the expanded storage unit (ESE) and the main storage unit (MSU) in page units. Focusing on the fact that the expansion storage device (ESE)
A sufficient number of banks and a data buffer (e.g.
1 page/4KB), and a data buffer of a certain size (for example, 64 bytes) is provided on the storage control unit (MCU) side, and when a data transfer request is received from the central processing unit, the storage control unit an activation signal S that activates access for data transfer from the (MCU) to the expanded storage device (ESE);
Data transfer request after a certain period of time (SYNC DATA)
In the case of data transfer from the extended storage device (ESE) to the main storage device (MSU), that is, page-in, after sending out the activation signal (S), the storage control device ( Check that the data buffer in the MCU is not full, and
The above data transfer request (SYNC DATA) is sent to the extended storage device (ESE), and the expanded storage device (ESE) performs its own operations in response to the sent data transfer request (SYNC DATA). For example, 8-byte data is transferred from the data buffer to the data buffer in the storage control unit (MCU), and data is transferred from the main storage unit (MSU) to the expanded storage device (ESE), that is, page out. In this case, the storage control unit (MCU)
Every time data is stored from the main storage device (MSU) into the data buffer in the data buffer, the data transfer request (SYNC DATA) is sent to the extended storage device (ESE), and the data in the data buffer is stored, for example, in Bytes are transferred to the data buffer in the expanded storage device (ESE) mentioned above, so it appears that the ESE side access time and bank busy time are ignored, allowing for effective data processing with simple control. This has the effect of enabling transfer.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings with reference to FIG. FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a page data transfer means (sequence) according to the present invention.
FIG. 4 is a time chart showing the operation when page-in is taken as an example, and the same reference numerals as in FIGS. 5 and 6 indicate the same objects. ESE CTL28 in Figure 1 above
, data buffers 27, 61, and access signal S to ESE 6, data request signal,
SYNC DATA" are the functional blocks and control signals necessary to implement the present invention.

In the following explanation, the data bus width between each device is 8 bytes, the capacity of data byte 61 in ESE6 is 4KB, and the capacity of the data buffer in MCU2 is
Set to 64 bytes.

The page data transfer related to the present invention is
Data transfer is in units of 4KB, and the following 2
There are two operations.

(1) Page-in: Transfer 4KB of data in ESE6 specified by the page transfer instruction to
Move to a location within MSU1.

(2) Page out: The 4KB data in MSU1 specified by the page transfer instruction is
Move to position within ESE6.

In such page data transfer processing,
In order to implement the present invention, it is necessary to prepare a sufficient number of banks 60 and data buffers 61 for the ESE 6. That is, by establishing the relationship: a ESE access throughput ≧ MSU access (page data transfer only) throughput, MCU2
(b) The ESE 6 can continue reading data from the data buffer 61 during a page-in operation regardless of the state of the MSU 1.

Also, the data buffer 27 in the MCU 2 is
Because of the data transfer between MCUESEs, this has the effect of eliminating the negative impact on MSU1 access (due to page data transfer).

The page data transfer when the present invention is implemented will be described below, focusing on the page data transfer sequence shown in FIG. 3, with reference to the block diagrams shown in FIGS. 1 and 2, and the time chart shown in FIG. Explain the operation.

(1) For page-in (ESEMSU) operation: When the CPU port 21 receives a fetch request from CPU 1 to ESE 6, the access is propagated to the CPU port 21 priority circuit (P) 23 pipeline 240 ESE CTL 28, and In the process, an address exception check for ESE6 is performed, and if an address corresponding to ESE6 does not exist, it is reported to CPU1 and the process is terminated.

Next, when a store request for MSU1 is received from CPU1, an address exception check for MSU1 is performed in the same manner.

After confirming that there are no address exceptions in both of
is set in the address register (AR) 62.

When the ESE 6 receives the fetch request S, it interrupts the processing currently being executed, such as patrol processing, enters the ESE BANK GO state, and transfers data from the bank 60 to the data buffer 6.
Start data transfer to 1. At this time, each time 8 bytes of data is transferred, the address register (AR) 62 is incremented by 1, and the separately provided bank counter (BANK CT) is also incremented by 1 (see Figure 4). ESE The CTL 28 starts the fetish access and after a certain period of time T (specifically,
ESE access time x 2), and sends a data transfer request 'SYNC DATA' to ESE6.
The corresponding 8 bytes of data are loaded into the data buffer 27 of the MCU 2 after three machine cycles.

This data transfer is performed using the data buffer 2 mentioned above.
This process continues until 7 becomes 32 bytes, and is interrupted when the number exceeds 32 bytes. After the interruption, already ESE6
Data transfer request sent to 'SYNC
Even if there is DATA, the capacity of the data buffer 27 will not exceed 64 bytes because of the 3 machine cycle shift mentioned above.

Further, the above-mentioned interruption can be determined by calculating the values of the in pointer and out pointer provided in the data buffer 27, for example.

The data loaded into the data buffer 27 of MCU 2 is sequentially transferred to the corresponding CPU port 2.
1 store data register (WD) (not shown) to activate store access (MSU GO, MSU WD) to MSU1.

Although this store access to the MSU 1 is not shown, it is performed while changing the address of the CPU port 21 by +8''.

The above store access to MSU1 is
If the port is made to wait by another port, the corresponding
Data transfer between the MCU 2 and the ESE 6 may be interrupted, but when the content of the data buffer 27 of the MCU 2 becomes 32 bytes or less, the interruption is canceled and data transfer is performed again.

The above data transfer request 'SYNC DATA,
is sent 512 times, the page-in process ends. (Refer to Figure 4) When the operations from above are completed, the CPU
Release the busy state of port 21 and ESE CTL 28, and transfer the result of the page-in process to the corresponding page-in process.
Report to CPU1.

(2) In case of page out (MSUESE) operation: ~ is the same operation as in (1) except that the store/fetch is reversed.

Fetch access to MSU1,
Start up sequentially while changing the address of CPU port 21 by +8".

The data read from MSU1 is
2's data buffer 27, and each time a data transfer request "SYNC DATA" is sent.
At the same time as sending data to ESE6
data buffer 61.

On the ESE6 side, as mentioned above, unless the data buffer 61 is "empty",
The address register (AR) 62 is
1, activate each bank and store the data.

Fetish access to MSU1 is
When the page-out process reaches 512 times, the page-out process ends.

This is the same as (1).

In this way, in the present invention, MSU2
After sending the access activation request S to the ESE6, after a certain period of time T or when the MSU
Every time 8 bytes of data is loaded into the data buffer 27 in 2, a data transfer request is made.
The feature is that page data transfer between MSU1 and ESE6 is performed simply by sending ``SYNC DATA'' to ESE6.

〔Effect of the invention〕

As described above in detail, the page data transfer control method of the present invention includes at least a central processing unit (CPU), a channel processing unit (CHP), a main storage unit (MSU), an expanded storage unit (ESE), In a computer system consisting of a storage control unit (MCU) that performs storage control and interface control between a central processing unit (CPU)/channel processing unit (CHP), the expanded storage device (ESE) and the main storage device Focusing on the fact that data transfer to and from (MSU) is in page units, the expansion storage device (ESE) is provided with a sufficient number of banks and a data buffer (for example, 1 page/4KB), and the storage control device ( A data buffer of a certain size (for example, 64 bytes) is provided on the MCU) side, and when there is a data transfer request from the central processing unit, data is transferred from the storage control unit (MCU) to the expanded storage device (ESE). activation signal S that activates access for
and a data transfer request (SYNC) after a certain period of time.
DATA), and in the case of data transfer from the expanded storage device (ESE) to the main storage device (MSU), that is, page-in, the data buffer in the storage control unit (MCU) is not full. Make sure that the expanded storage device (ESE)
The data transfer request (SYNC DATA) is sent to the extended storage device (ESE), and the expanded storage device (ESE) transfers data from its own data buffer to the storage control device (MCU) in response to the sent data transfer request (SYNC DATA). ), for example,
In the case of data transfer from the main storage unit (MSU) to the expanded storage unit (ESE), that is, page-out, data is transferred to the data buffer in the storage control unit (MCU). Every time data is stored from a storage device (MSU),
The data transfer request (SYNC DATA) is sent to the expanded storage device (ESE), and the data in the data buffer is transferred to the data buffer in the expanded storage device (ESE), for example, to 8 bytes. Therefore, it appears that effective data transfer is possible with simple control, ignoring the access time on the ESE side and the busy time of the bank.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the ESE access unit of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing a page data transfer sequence according to the present invention. FIG. 4 is a time chart showing the operation when page-in is performed by implementing the present invention, FIG. 5 is a diagram showing the system configuration of a general data processing device, and FIG. 6 is based on the conventional technology. FIG. 3 is a block diagram showing a main memory access control unit. In the drawing, 1 is the main storage unit (MSU#0~
#3), 2 is a storage control unit (MCU), 3 is a central processing unit (CPU#0, #1), 4 is a channel processing unit (CHP#0, #1), 21 and 22 are main memory access request ports , 23 is a priority circuit (P), 24
0 is pipeline, 27 is data buffer, 28
is the ESE control unit (ESE CTL), 6 is the expansion storage device (ESE), 60 is the bank, 61 is the data buffer,
62 is the address register (AR), ~ is each processing step of page data transfer, S, 〓SYNC
DATA" indicates a control signal, respectively.

Claims (1)

[Claims] 1. At least a central processing unit (CPU) 3;
Performs interface control between the channel processing unit (CHP) 4, the main storage unit (MSU) 1, the expanded storage unit (ESE) 6, and the storage control and central processing unit (CPU)/channel processing unit (CHP). In a computer system configured with a storage control unit (MCU) 2, when data is transferred in page units between the main storage unit (MSU) 1 and the expanded storage unit (ESE) 6, the expanded storage unit (ESE) 6 and a storage control unit (MCU) 2, respectively, are provided with data buffers 61 and 27 of different sizes, and data transfer commands issued by the central processing unit (CPU) 1 are transferred to the storage control unit When the MCU) 2 receives and sends an access request for data transfer to the expanded storage device (ESE) 6, it sends a startup request (S) to the expanded storage device (ESE) 6 and after a certain period of time. Data transfer request (SYNC DATA) 2
The data transfer request is configured to send two signals to the expanded storage device (ESE) 6.
In the case of data transfer (page-in) from to the main storage unit (MSU) 1, after sending the startup request (S), confirm that the data buffer 27 in the storage control unit (MCU) 2 is not full. Then, the above data transfer request (SYNC DATA) is sent to the expanded storage device (ESE) 6, and the expanded storage device (ESE) 6 responds to the sent data transfer request (SYNC DATA). , from its own data buffer 61 to the storage control unit (MCU) 2
A specific number of bytes of data is transferred to the data buffer 27 in the main storage unit (MSU) 1.
In the case of data transfer (page out) from the main storage unit (MSU) 1 to the expanded storage unit (ESE) 6, each time data is stored from the main storage unit (MSU) 1 to the data buffer 27 in the storage control unit (MCU) 2. Then, the data transfer request (SYNC DATA) is sent to the expanded storage device (ESE) 6, and a specific number of bytes of data is transferred from the own data buffer 27 to the data buffer 61 in the expanded storage device (ESE) 6. A page featuring control to perform
Data transfer control method.