JP2679440B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA processing device and an information processing device using the same, and more particularly to a temporary storage means for temporarily holding data relating to data transfer between a storage device and an input / output device. DMA processing device and this D
The present invention relates to an information processing device that uses an MA processing device to transfer data between a storage device and an input / output processing device.

[0002]

2. Description of the Related Art In an information processing apparatus, a DMA processor is used to reduce the input / output processing overhead of a central processing unit.

FIG. 8 shows a block diagram of an information processing apparatus using a general DMA processing apparatus. The information processing apparatus of FIG. 8 is a central processing unit 81 that controls the entire information processing apparatus.
And a readable / writable storage device 84, and an input / output processing device 83 for executing data transfer processing with an input / output device (not shown).
And a DMA processing device 8 for performing data transfer between the storage device 84 and the input / output processing device 83 without going through the central processing device 81.
2 and an interrupt processing unit 85 that arbitrates the input / output interrupt request that the input / output processing unit 83 requests when the processing of the central processing unit 81 is required and requests the central processing unit 81 to perform a specific interrupt processing. .

The signal 201 is the central processing unit 81 or DM.
A processing device 82 outputs and is input to the storage device 84,
It is a series of address signals indicating the address of the storage device 84 to be processed.

The signal 202 is output from the DMA processor 82 and input to the central processor 81.
Reference numeral 2 is a bus hold request signal for requesting control right to the storage device 84 and the input / output processing device 83.

The signal 203 is output by the central processing unit 81,
This is a bus hold permission signal that is input to the DMA processor 82 and indicates that the central processing unit 81 has released the control line between the storage device 84 and the input / output processing device 83.

The signal 204 is the central processing unit 81 or DM.
A storage device to be processed, which includes a signal output from the A processing device 82 and input to the storage device 84 and a signal output from the storage device 84 and input to the central processing device 81 or the DMA processing device 82 This is a series of storage device control signals for controlling reading / writing from / to 84.

The signal 205 is output from the input / output processing device 83 and input to the DMA processing device 82. A DMA transfer request indicating that the input / output processing device 83 requests the DMA processing device 82 for data transfer by DMA. It is a signal.

A signal 206 is a DMA transfer permission signal output from the DMA processor 82 and input to the input / output processor 83, which indicates that the DMA processor 82 permits DMA data transfer to the input / output processor 83. is there.

The signal 207 is output from the DMA processing device 82 and input to the input / output processing device 83, which indicates that the data transfer between the storage device 84 and the input / output processing device 83 by the DMA processing device 82 has reached a specified amount. It is a terminal count signal shown.

The signal 208 includes a signal output from the DMA processor 82 and input to the input / output processor 83, and a signal output from the input / output processor 83 and input to the DMA processor 82. Target input / output processing device 83
It is a series of input / output device control signals for controlling reading / writing from / to.

The signal 211 is output from the central processing unit 81 or the input / output processing unit 83 and input to the storage unit 84, or output from the storage unit 84 and input to the central processing unit 81 or the input / output processing unit 83. Is a series of data signals indicating the data to be processed.

The signal 213 is output by the interrupt processing unit 85 and input to the central processing unit 81.
Is an interrupt request signal for the.

A signal 214 is an interrupt request signal output from the input / output processing unit 83 and input to the interrupt processing unit 85, which indicates that the input / output processing unit 83 requests the processing of the central processing unit 81.

The information processing apparatus shown in FIG. 8 is an input / output processing apparatus 8
3 activates the DMA transfer request signal 205 when the DMA data transfer is required,
2 requests DMA transfer.

The DMA processor 82 is an input / output processor 83.
When the DMA transfer request signal 205 is activated, the bus hold request signal 202 is activated to request the central processing unit 81 to control the storage device 84 and the input / output processing device 83.

When the bus hold request signal 202 becomes active, the central processing unit 81 makes a series of address signals 2
01 and a series of storage device control signals 204 and a series of data signals 211 are passed to the DMA processing device 82, and the bus hold permission signal 20 indicating the passing
Activate 3

When the bus hold enable signal 203 becomes active, the DMA processor 82 outputs a series of address signals 2
01, a series of storage device control signals 204, and a series of data signals 211 are started to control, and in the case of writing to the storage device 84, the state of the data signal 211 is written to the address of the storage device 84 indicated by the address signal 201. The control is executed, and in the case of reading from the storage device 84, the control is executed such that the data stored in the address of the storage device 84 indicated by the address signal 201 is output to the data signal 211. DMA transfer enable signal 206
And a series of input / output device control signals 208 are activated.

The input / output processor 83 responds to the DMA transfer permission signal 206 and a series of input / output device control signals 208.
In the case of writing to the storage device 84, that is, in the case of reading from the input / output processing device 83, control for outputting the data inside the input / output processing device 83 to the data signal 211 is executed,
Further, in the case of reading from the storage device 84, that is, in the case of writing to the input / output processing device 83, control is performed such that the content of the data signal 211 is written inside the input / output processing device 83.

In this case, the storage device control signal 204 controlled by the DMA processing device 82 and the input / output device control signal 208 are in synchronism with each other, and read from the storage device 84, that is, write to the input / output processing device 83. In this case, the data of the storage device 84 at the address indicated by the address signal 201 is output to the data signal 211 at the timing of the storage device control signal 204 and propagated to the input / output processing device 83, and the input / output device control signal 208 is set as described above. Control is performed so that the data in the storage device 84 is taken into the input / output processing device 83 at the timing when the data has propagated to the input / output processing device 83.

Further, in the case of writing to the storage device 84, that is, reading from the input / output processing device 83, the data inside the input / output processing device 83 is output to the data signal 211 at the timing of the input / output device control signal 208. Storage device 84
The storage device control signal 204 is controlled so as to be taken into the address indicated by the address signal 201 at the timing when the data of the input / output processing device 83 is propagated to the storage device 84.

The input / output processing unit 83 makes the DMA transfer request signal 205 inactive when the DMA transfer becomes unnecessary.

When the DMA transfer request signal 205 becomes inactive, the DMA processor 82 makes the DMA transfer permission signal 206 inactive and ends the DMA transfer. After that, the DMA processing device 82 passes a signal line for transmitting the series of address signals 201, the series of storage device control signals 204, and the series of data signals 211 to the central processing unit 81, and then makes the bus hold request signal 202 inactive. To do.

When the bus hold request signal 202 becomes inactive, the central processing unit 81 makes the bus hold permission signal 203 inactive, and makes a series of address signals 201, a series of storage device control signals 204, and a series of data signals 211. Is activated to regain control of the storage device 84.

As described above, the DMA data transfer in which the storage device 84 and the input / output processing device 83 are accessed at the same time is called a fly-by transfer.

During the DMA data transfer, when the data transfer between the storage device 84 and the input / output processing device 83 by the DMA processing device 82 reaches a specified amount, the DMA processing device 82 activates the terminal count signal 207. The I / O processor 83 is notified that the specified amount of DMA data transfer has been completed.

When the terminal count signal 207 is activated, the input / output processing unit 83 suspends the data transfer with the input / output device and activates the interrupt request signal 214 to activate the DMA data transfer completion interrupt to the central processing unit 81. Request processing.

When the interrupt request signal 214 becomes active, the interrupt processing unit 85 determines the priority order of the interrupt request signal (not shown) for the other central processing units and the above-mentioned interrupt request signal 214, and determines the highest priority. The high interrupt request is transmitted to the central processing unit 81 by the interrupt request signal 213. When the interrupt request signal 214 has the highest priority, the DM of the input / output processing device 83 described above is used.
The central processing unit 81 executes the A data transfer completion interrupt process.

The interrupt request signal 214 is DMA
It may become active not only when the data transfer is completed, but also when the processing of the central processing unit 81 becomes necessary such as the occurrence of an error in the input / output processing unit 83.

In the fly-by transfer described above, since the central processing unit 81 cannot use the storage device 84 during the DMA transfer, the system performance is slightly deteriorated, but the circuit scale is small and the information processing device is relatively slow. Suitable for

However, the central processing unit 81 and the storage unit 84
If the processing speed is high and the processing speed difference with the input / output device is too large, or if there are many input / output devices that use DMA data transfer, the central processing unit 81 stores the storage device in the central processing unit 81 during the DMA transfer. The time that cannot be used cannot be ignored and leads to deterioration of system performance.

Therefore, in these information processing devices, a DMA processing device having a temporary storage means is interposed between the storage device 84 and the input / output processing device 83, and a data signal system separated by the temporary storage means is provided. The storage device 84 is provided and the access to the storage device 84 and the access to the input / output processing device 83 are executed at their own timing.
Alternatively, by temporarily storing the data output from the input / output processing device 83 in the internal temporary storage means and then outputting the data from the temporary storage means to the input / output processing device 83 or the storage device 84, a high-speed central processing unit is provided. The speed difference between the processor system and the input / output processor system, which is relatively slow, is absorbed. Such data transfer requires two cycles (2-Cyc).
le) transfer method, and a dedicated DMA processor is used. Another example of the 2-cycle transfer method is byte width conversion.

FIG. 9 shows the D according to the 2-cycle data transfer method.
The block diagram of the information processing apparatus which uses MA processing apparatus is shown.

The information processing apparatus shown in FIG. 9 is a central processing unit 91 for controlling the entire information processing apparatus, a readable / writable storage device 94, and an input / output processing apparatus for executing data transfer processing with an input / output device (not shown). 93, a data signal system for accessing the data of the temporary storage means and the storage device 94, and a data signal system for accessing the data of the input / output processing device 93, and read from the above-mentioned one data signal system. Data is temporarily stored in the internal temporary storage means, and when the data stored in the temporary storage means reaches a specific amount, the data is output from the other data signal system described above, and The DMA processing device 92 for performing data transfer between the input / output processing devices 93 without passing through the central processing device 91 and the input / output processing device 93 are the central processing devices 91.
And an interrupt processing unit 95 that arbitrates the input / output interrupt request that is requested when the above process is required and requests the central processing unit 91 to perform a specific interrupt process.

The signal 301 is the central processing unit 91 or DM.
The A processing device 92 outputs and the storage device 94 inputs,
It is a series of address symbols indicating the address of the storage device 94 to be processed.

The signal 302 is output from the DMA processing unit 92 and input to the central processing unit 91.
Reference numeral 2 is a bus hold request signal for requesting the control right of the storage device 94.

The signal 303 is output by the central processing unit 91,
This is a bus hold permission signal that is input to the DMA processing unit 92 and indicates that the central processing unit 91 has given up the control right of the storage device 94.

The signal 304 is the central processing unit 91 or DM.
A storage device to be processed, which includes a signal output from the A processing device 92 and input to the storage device 94, and a signal output from the storage device 94 and input to the central processing device 91 or the DMA processing device 92 It is a series of storage device control signals that control reading and writing to 94.

The signal 305 is output from the input / output processor 93 and input to the DMA processor 92. A DMA transfer request indicating that the input / output processor 93 requests the DMA processor 92 to transfer data by DMA. It is a signal.

The signal 306 is a DMA transfer permission signal output from the DMA processing unit 92 and input to the input / output processing unit 93, which indicates that the DMA processing unit 92 permits the data transfer by DMA to the I / O processing unit 93. is there.

The signal 307 is a terminal count signal output from the DMA processor 92 and input to the input / output processor 93, which indicates that the data transfer of the input / output processor 93 by the DMA processor 92 has reached a specified amount. is there.

The signal 308 includes a signal output from the DMA processing unit 92 and input to the input / output processing unit 93, and a signal output from the input / output processing unit 93 and input to the DMA processing unit 92. Is a series of input / output device control signals for controlling reading / writing from / to the input / output processing device 93.

The signal 311 is sent to the central processing unit 91 or DM.
The A processing unit 92 outputs and is input to the storage unit 94, or the storage unit 94 outputs and the central processing unit 91.
Alternatively, it is a series of data signals indicating the data to be processed, which is input to the DMA processing device 92.

The signal 312 is output from the input / output processing unit 93 and input to the DMA processing unit 92, or DM
A series of data signals output from the A processing unit 92 and input to the input / output processing unit 93 that represent data to be processed.

The signal 313 is output by the interrupt processing unit 95 and input to the central processing unit 91.
Is an interrupt request signal for the.

The signal 314 is an interrupt request signal output from the input / output processing unit 93 and input to the interrupt processing unit 95, which indicates that the input / output processing unit 93 requests the processing of the central processing unit 91.

The signal 315 is an interrupt request signal output from the DMA processing unit 92 and input to the interrupt processing unit 95, which indicates that the DMA processing unit 92 requests the processing of the central processing unit 91.

The information processing apparatus of FIG. 9 is the input / output processing apparatus 9
3 makes the DMA transfer request signal 305 active when the DMA data transfer is required by the DMA processor 3
2 requests DMA transfer.

The DMA processor 92 is an input / output processor 93.
When the DMA transfer request signal 305 from the CPU becomes active, and when the transfer direction is reading from the storage device 94, that is, writing to the input / output processing device 93, valid data is stored in the temporary storage means inside the DMA processing device 92. That is, it is checked that there is data that can be output to the input / output processing device 93, and if the transfer direction is writing to the storage device 94, that is, reading from the input / output processing device 93, then DMA It is checked whether the read data from the input / output processing device 93 can be stored in the temporary storage means inside the processing device 92.

When the transfer direction is reading from the storage device 94 and valid data does not exist in the temporary storage means inside the DMA processing device 92, or when the transfer direction is writing to the storage device 94. When the read data from the input / output processing device 93 cannot be stored in the temporary storage means inside the DMA processing device 92, the DMA processing device 92 activates the bus hold request signal 302 to the central processing unit 91. In response, the control right of the storage device 94 is requested.

When the bus hold request signal 302 becomes active, the central processing unit 91 makes a series of address signals 3
01, a series of storage device control signals 304, and a series of data signals 311 are passed to the DMA processing device 92, and a bus hold permission signal 30 indicating the passing
Activate 3

When the bus hold enable signal 303 becomes active, the DMA processor 92 makes a series of address signals 3
01, a series of storage device control signals 304, and a series of data signals 311 are started, and in the case of writing to the storage device 94, the storage device 94 indicated by the address signal 301
Control such that the state of the data signal 311 is written in the address of the memory device 94, and in the case of reading from the memory device 94, the data stored in the address of the memory device 94 indicated by the address signal 301 is set in the data signal 311. In the case of writing to the storage device 94, that is, when reading from the input / output processing device 93, the data stored in the temporary storage means inside the DMA processing device 92 is executed as a data signal. In the case of executing control to output to 311 and writing from the storage device 94, that is, writing to the input / output processing device 93, the data signal 311
The control is executed so that the contents of the above are stored in the temporary storage means inside the DMA processing device 92.

In this case, the storage device control signal 304 controlled by the DMA processing device 92 and the control signal of the temporary storage means inside the DMA processing device 92 are in synchronization with each other, and read from the storage device 94, that is, input / output processing. In the case of writing to the device 93, the data in the storage device 94 at the address indicated by the address signal 301 is output to the data signal 311 at the timing of the storage device control signal 304 and propagated to the DMA processing device 92, and the DMA processing device 92 The data in the above-mentioned storage device 94 is used as the control signal of the internal temporary storage means in the DMA processor 92.
It is controlled so as to be taken into the temporary storage means inside the DMA processing device 92 at the timing when it is propagated to the internal temporary storage means.

Writing to the storage device 94, that is,
When reading from the I / O processor 93, DMA
The storage device 9 outputs the data stored in the temporary storage means of the DMA processing device 92 to the data signal 311 at the timing of the control signal of the temporary storage means of the processing device 92.
4 and the storage device control signal 304 is transmitted to the above-mentioned DMA.
The control is performed so that the data stored in the temporary storage means inside the processing device 92 is taken into the address indicated by the address signal 301 at the timing when the data is propagated to the storage device 94.

When the transfer direction is reading from the storage device 94, the valid data is the DMA processing device 92.
The data output from the input / output processing device 93 can be stored in the temporary storage device inside the DMA processing device 92 when it exists in the internal temporary storage device or when the transfer direction is writing to the storage device 94. In some cases, DMA processor 92 activates DMA transfer enable signal 306 and a series of I / O device control signals 308.

The input / output processing device 93 responds to the DMA transfer permission signal 306 and the series of input / output device control signals 308 according to
In the case of writing to the storage device 94, that is, in the case of reading from the input / output processing device 93, control for outputting the data inside the input / output processing device 93 to the data signal 312 is executed,
Further, in the case of reading from the storage device 94, that is, in the case of writing to the input / output processing device 93, control such that the content of the data signal 312 is written inside the input / output processing device 93 is executed.

At this time, when the DMA processing device 92 is writing to the storage device 94, that is, reading from the input / output processing device 93, the data inside the input / output processing device 93 is output to the data signal 312. At this point, control is executed to store the state of the data signal 312 in the temporary storage means inside the DMA processing device 92, and the storage device 94 is also operated.
In the case of reading from, that is, writing to the input / output processing device 93, valid data stored in the temporary storage means inside the DMA processing device 92 is output to the data signal 312, and the input / output processing device 93 outputs. Control is performed so that this valid data can be taken into the input / output processing device 93.

The input / output processing device 93 makes the DMA transfer request signal 305 inactive when the DMA transfer is no longer required.

When the DMA transfer request signal 305 becomes inactive, the DMA processor 92 makes the DMA transfer permission signal 306 inactive and ends the DMA transfer.

In this data transfer method, the data transfer is D
Since it is executed between the temporary storage means inside the MA processing device 92 and the input / output processing device 93, or between the temporary storage means inside the DMA processing device 92 and the storage device 94, it can be connected to the temporary storage means inside the DMA processing device 92. During the data transfer period between the output processing devices 93, it is not necessary to use the storage device 94, and the DMA processing device 92 does not need to request the central processing unit 91 to control the storage device 94. Therefore, the central processing unit 91 includes the input / output processing unit 93 and the DMA processing unit 92.
Even during the period in which the data transfer is executed with the internal temporary storage means, the storage device 94 is used and the central processing unit 9 is used.
1 can continue its own processing. In addition, the DMA processor 92
During a period in which DMA data transfer is executed between the internal temporary storage means and the storage device 94, that is, during a period in which the central processing unit 91 hands over the control right of the storage device 94 to the DMA processing device 92, input / output is relatively slow. Since it can be shortened by using the temporary storage means inside the DMA processing device 92, which is relatively high speed, instead of the processing device 93, it has a feature that the system performance is less deteriorated by the DMA data transfer.

As described above, the DM that executes the access between the storage device 94 and the input / output processing device 93 at its own different time
A data transfer is called 2-cycle transfer.

During the DMA data transfer, when the data transfer between the storage device 94 and the input / output processor 93 by the DMA processor 92 reaches a specified amount, the DMA processor 92 activates the terminal count signal 307. Then, the I / O processor 93 is notified that the specified amount of DMA data transfer is completed.

When the terminal count signal 307 is activated, the input / output processing unit 93 suspends the data transfer with the input / output device and activates the interrupt request signal 314 to make the central processing unit 91 DMA data transfer completion interrupt. Request processing.

When the interrupt request signal 314 becomes active, the interrupt processing unit 95 determines the priority order of the interrupt request signal 314 and the interrupt request signal (not shown) for the other central processing units, and determines the highest priority interrupt. The request is transmitted to the central processing unit 91 using the interrupt request signal 313. When the interrupt request signal 314 has the highest priority, the processing of the DMA data transfer completion interrupt of the input / output processing device 93 described above is performed by the central processing unit 9.
1 executes.

The interrupt request signal 314 is DMA
It may become active not only when the data transfer is completed, but also when the processing of the central processing unit 91 becomes necessary, such as an error in the input / output processing unit 93.

Here, the input / output processing device 93 has a specified amount of D
When the MA data transfer is completed, or when the processing of the central processing unit 91 is required such as the occurrence of an error in the input / output processing unit 93, the interrupt request signal 314 is activated to the central processing unit 91. On the other hand, the interrupt processing for the input / output processing device 93 is requested. At this time, in the temporary storage means inside the DMA processing device 92, the DMA data transfer direction is written to the storage device 94, that is, read from the input / output processing device 93. In the case of a soup, there is a high possibility that there is a period in which the data read from the input / output processing device 93 is still stored and the stored data has not yet been written to the storage device 94.

This is because the DMA processing device 9 is operated at the time of terminal counting, that is, when the prescribed data transfer is completed.
2 can detect the condition and execute a process of writing the data stored in the temporary storage means inside the DMA processing device 92 to the storage device 94, but it can be avoided to some extent, but it is difficult to avoid it completely. Further, the input / output processing device 93
If the processing of the central processing unit 91 is necessary due to the occurrence of an error or the like in the DMA processing unit 92, the DMA processing unit 92 sets the condition that the processing of the central processing unit 91 is necessary due to the occurrence of an error in the input / output processing unit 93. DM because it cannot be detected
The DMA processing device 92 cannot execute the processing such as writing the data stored in the temporary storage means inside the A processing device 92 to the storage device 94.

In such a state, data consistency cannot be maintained between the storage device 94 and the input / output processing device 93. That is, since all the data transferred by the input / output processing device 93 is not stored in the storage device 94, a state occurs in which the data determined to be transferred by the input / output processing device 93 is not transferred to the storage device 94.

Therefore, the central processing unit 91 uses an interrupt by the interrupt request signal 315 from the DMA processing unit 92 in order to ensure data consistency. This will be described below.

The interrupt request signal 315 indicates that the DMA processing unit 92 has completed the DMA transfer of the specified transfer amount, and
It becomes active when all the data read from the input / output processing device 93 stored in the temporary storage means inside the MA processing device 92 is written in the storage device 94.

When the interrupt request signals 314 and 315 are activated, the interrupt processing unit 95 determines the priority order of the interrupt request signals 314 and 315 (not shown) for the other central processing units and determines the highest priority. A high frequency interrupt request is transmitted to the central processing unit 91 using the interrupt request signal 313. When the interrupt request signal 314 has the highest priority, the central processing unit 91 executes the interrupt processing of the input / output processing device 93 described above, and when the interrupt request signal 315 has the highest priority, the above-mentioned DMA processing. The central processing unit 91 executes the interrupt processing of the device 92.

The central processing unit 91 is a DMA processing unit 92.
It is checked whether the interrupt request from the DMA processor 92 or the interrupt request from the input / output processor 93 is accepted, and whether or not the data stored in the temporary storage means inside the DMA processor 92 is written in the storage device 94. to decide.

For example, in the interrupt processing from the input / output processing device 93, if the interrupt from the DMA processing device 92 has already been accepted, the data stored in the temporary storage means inside the DMA processing device 92 has already been stored in the storage device. It is determined that the data has been written in 94. In the interrupt processing from the input / output processing device 93, the DMA
If the interrupt from the processing device 92 is not accepted, it is determined that the data stored in the temporary storage means inside the DMA processing device 92 has not yet been written in the storage device 94, and the central processing device 91 determines that the DMA processing is performed. The state of the temporary storage means inside the device 92 is checked, and a process for writing valid data stored in the temporary storage means to the storage device 94 is executed, and the storage device 94 and the input / output processing device 93 are executed.
Ensure data consistency between.

[0074]

As described above, in the information processing apparatus for performing the DMA data transfer by the conventional 2-cycle transfer method, the data transfer is executed through the temporary storage means inside the DMA processing unit 92. In addition, the timing of access to the input / output processing device 93 and the timing of access to the storage device 94 are different, and the DMA data transfer direction is writing to the storage device 94, that is, the input / output processing device 9
In the case of reading from 3, the central processing unit 91 uses the interrupt request from the DMA processing unit 92 and the I / O processing unit in order to ensure data consistency between the storage unit 94 and the I / O processing unit 93. It is necessary to check the acceptance status of the interrupt request from 93 to determine whether or not the data stored in the temporary storage means inside the DMA processing device 92 has been written in the storage device 94. That is, as described above, for example, in the interrupt processing from the input / output processing device 93, if the interrupt from the DMA processing device 92 has already been accepted, the data stored in the temporary storage means inside the DMA processing device 92 is Already storage device 9
4 is already written, and in the interrupt processing from the input / output processing device 93, if the interrupt from the DMA processing device 92 has not been accepted yet, DMA
It is determined that the data stored in the temporary storage means inside the processing device 92 has not yet been written in the storage device 94,
The central processing unit 91 executes a process of checking the state of the temporary storage means inside the DMA processing unit 92 and writing the valid data stored in the temporary storage unit inside the DMA processing unit 92 into the storage unit 94. It was necessary to ensure data consistency between the storage device 94 and the input / output processing device 93.

In the above-described information processing apparatus for performing DMA data transfer by the conventional fly-by transfer method shown in FIG. 8, since the input / output processing device 83 and the storage device 84 are accessed at the same time, data consistency is achieved. Will always be secured.

This means that in the fly-by transfer method described with reference to FIG. 8 and the 2-cycle transfer method described with reference to FIG. 9, the central processing unit processes the interrupt request from the input / output processing unit. It means that the contents to be different are different.

Therefore, the DM of the fly-by transfer system of FIG.
When the information processing apparatus adopting the A processing apparatus 82 adopts the 2-cycle transfer type DMA processing apparatus 92 for the purpose of improving the system performance, etc., the processing of the central processing unit 81 in response to the interrupt request from the input / output processing apparatus 83. There is a problem that the program must be changed, and a problem that the processing program for the information processing device that employs the conventional fly-by transfer type DMA processing device 82 cannot be executed as it is.

[0078]

[0079]

The present invention solves the above problems.
In order to determine, a central processing unit, a storage device that can be accessed from now on, an input / output processing device, and a data transfer between the storage device and the input / output processing device are performed in two cycles using an internal temporary storage means. In an information processing device including a DMA processing device that performs a transfer method and an interrupt processing device,
Any one of the following ( A ), ( B ), and ( C ) is adopted.

( A ) Effective indicating whether or not there is data, which has been received from the input / output processing device and held in the temporary storage means, and which has not been transferred to the storage device, in the DMA processing device A means for outputting a data existence signal, and a memory for storing the data received from the input / output processing device and held in the temporary storage means and not yet transferred to the storage device in response to the forced write request signal. And a masking means for masking an interrupt request signal from the input / output processing device by the valid data existence signal and transmitting the interrupt request signal to the interrupt processing device, and before the masking of the input / output processing device. The interrupt request signal of 1 is given to the DMA processing device as the forced write request signal.

( B ) Effective indicating whether or not there is data in the DMA processing device which is received from the input / output processing device and is held in the temporary storage means and which has not been transferred to the storage device. Means for outputting a data presence signal to the outside, and data that is received from the input / output processing device and is held in the temporary storage means and has not yet been transferred to the storage device in response to the forced write request signal. Means for transferring to the storage device, and
The input / output processing device includes mask means for masking an interrupt request signal from its own input / output processing device by the valid data existence signal and transmitting the masked interrupt request signal to the interrupt processing device
Furthermore, an interrupt request signal before masking of the input / output processing device is given to the DMA processing device as the forced write request signal.

( C ) Validity indicating whether or not the DMA processing device has data received from the input / output processing device and held in the temporary storage means and not yet transferred to the storage device Means for outputting a data presence signal to the outside, and data that is received from the input / output processing device and is held in the temporary storage means and has not yet been transferred to the storage device in response to the forced write request signal. Means for transferring to the storage device, and
The interrupt processing device is provided with mask means for masking an interrupt request signal from the input / output processing device according to the valid data presence signal, and further, the interrupt request signal before masking of the input / output processing device is forced write request signal. Is given to the DMA processing device.

[0083]

[0084]

In the information processing apparatus having the configuration ( A ), the DM
The A processing unit notifies the internal masking unit of the presence or absence of data received from the input / output processing unit and held in the temporary storing unit and not yet transferred to the storing unit by the valid data existence signal, and the masking unit The interrupt request signal from the input / output processing device is masked by the valid data existence signal and transmitted to the interrupt processing device. Therefore, when the valid data presence signal indicates the presence of valid data, the interrupt signal from the input / output processing device is masked. On the other hand, the interrupt request signal before masking of the I / O processor is given to the DMA processor as a forced write request signal. Therefore, when valid data exists, first, the data is the data which the DMA processing device received from the input / output processing device and held in the temporary storage means in response to the forced write request signal, and which has not yet been transferred to the storage device. When the data is transferred to the storage device and the valid data is no longer present, the masking of the interrupt request signal from the input / output processing device is released and the interrupt request signal is transmitted to the interrupt processing device.

In the information processing apparatus having the configuration of ( B ),
The DMA processing device notifies the masking means inside the input / output processing device of the presence / absence of data received from the input / output processing device and held in the temporary storage means and not yet transferred to the storage device, The masking means masks the interrupt request signal from the self input / output processing device by this valid data existence signal and transmits it to the interrupt processing device. Therefore, when the valid data presence signal indicates the presence of valid data, the interrupt signal from the input / output processing device is masked. On the other hand, the interrupt request signal before masking of the I / O processor is DMed as the forced write request signal.
A processor is provided. Therefore, when valid data exists, first, D is responded to in response to the forced write request signal.
When the MA processing device receives data from the input / output processing device and holds it in the temporary storage means and has not yet transferred to the storage device, the MA processing device transfers the data to the storage device. Of the interrupt request signal is released and the interrupt request signal is transmitted to the interrupt processing device.

In the information processing apparatus having the configuration of ( C ),
The DMA processing unit notifies the masking unit inside the interrupt processing unit by a valid data existence signal whether or not there is data received from the input / output processing unit and held in the temporary storage unit and not yet transferred to the storage unit. The means masks the interrupt request signal from the input / output processor by the valid data present signal. Therefore, when the valid data presence signal indicates the presence of valid data, the interrupt signal from the input / output processing device is masked. On the other hand,
An interrupt request signal before masking of the input / output processing device is given to the DMA processing device as a forced write request signal. Therefore, when valid data exists, first, the data is the data which the DMA processing device received from the input / output processing device and held in the temporary storage means in response to the forced write request signal, and which has not yet been transferred to the storage device. When the data is transferred to the storage device, and the valid data is no longer present, the masking of the interrupt request signal of the input / output processing device is released, and the interrupt processing device processes the interrupt request signal.

[0087]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an internal block diagram of an embodiment of the DMA processor used in the present invention.

The DMA processor 11 of FIG. 1 comprises a transfer address generator 1, a transfer amount counter 2, and a transfer amount comparator 3.
A transfer amount counter 4, a transfer control circuit 5, and a temporary storage means 6.

The transfer address generator 1 generates an address of an external storage device to be a DMA transfer target.

The transfer amount counter 2 is a circuit for counting the amount of DMA transfer to the external storage device, and is used to detect the end of the DMA data transfer to the external storage device.

The transfer amount counter 4 is a circuit for counting the amount of DMA transfer to the external input / output processing device, and is used to detect the end of the DMA data transfer to the external input / output processing device.

The transfer amount comparator 3 is a DMA transfer amount for an external storage device and a DMA for an external input / output processing device.
This is a circuit for comparing the transfer amount with the temporary storage means 6 when a DMA transfer request signal 105 described later is activated.
Writing the data stored in the external storage device to the external storage device, reading the data from the external storage device into the temporary storage means 6, or outputting the data stored in the temporary storage means 6 to the external input / output processing device. Or to store the data read from the external input / output processing device in the temporary storage means 6.

The transfer control circuit 5 controls the internal storage device system, the external input / output processing device system, and the internal operation of the DMA processing device 11.

The temporary storage means 6 temporarily holds the DMA transfer data input from the external storage device or the external input / output processing device, and stores the held DMA transfer data in the external storage under a predetermined condition. Output to the device or external input / output processing device.

The signal 101 is a series of address signals output from the transfer address generator 1 and indicating the address of the external storage device to be processed.

The signal 102 is output by the transfer control circuit 5.
This is a bus hold request signal for the DMA processing device 11 to request the control right of the external storage device.

A signal 103 is a bus hold permission signal input to the transfer control circuit 5 to indicate that the external central processing unit has given up the control right to the external storage device.

The signal 104 is output by the external central processing unit or the transfer control circuit 5 and is input to the external storage device, and the signal output by the external storage device is output to the external central processing unit or the transfer control circuit 5. It is a series of storage device control signals which consist of input signals and control reading and writing to an external storage device to be processed.

The signal 105 is output from the external input / output processing device and input to the transfer control circuit 5, which indicates that the external input / output processing device requests the DMA processing device 11 for data transfer by DMA. This is a transfer request signal.

The signal 106 is output from the transfer control circuit 5 and input to the external input / output processing device. DMA transfer permission indicating that the DMA processing device 11 has permitted the DMA data transfer to the external input / output processing device. It is a signal.

The signal 107 is output from the transfer control circuit 5 and input to an external input / output processing device, which is the DMA processing device 11.
Is a terminal count signal indicating that the data transfer of the external input / output processing device has reached a specified amount.

The signal 108 includes a signal output from the transfer control circuit 5 and input to the external input / output processing device, and a signal output from the external input / output processing device and input to the transfer control circuit 5. It is a series of input / output device control signals for controlling reading / writing from / to an external input / output processing device to be processed.

A signal 109 is a forced write request signal which is input from the outside to the transfer control circuit 5 and requests to forcibly write the valid data stored in the temporary storage means 6 to the external storage device.

The signal 110 is a valid data existence signal output from the transfer control circuit 5 to the outside and indicating whether or not valid data exists in the temporary storage means 6.

The signal 111 is output by the external central processing unit or the temporary storage means 6 and is input to the external storage device, or is output by the external storage device and is output by the external central processing unit or the temporary storage means 6. Is a series of data signals indicating the data to be processed that is input to the.

The signal 112 is output by an external input / output processing device and is input to the temporary storage means 6, or is a target of processing output by the temporary storage means 6 and input to an external input / output processing device. Is a series of data signals indicating the following data.

The signal 113 is an internal signal of the DMA processing device and is a series of signals for the transfer control circuit 6 to control the temporary storage means 6.

The signal 114 is an internal signal of the DMA processor and is a series of signals for the transfer control circuit 5 to control the transfer address generator 1.

The signal 115 is an internal signal of the DMA processing device and is a signal for the transfer control circuit 5 to control the transfer amount counter 2.

The signal 116 is an internal signal of the DMA processing device and is a signal for the transfer control circuit 5 to control the transfer amount counter 4.

A signal 117 is an internal signal of the DMA processor and is a signal for transmitting the value of the transfer amount counter 2 to the transfer control circuit 5 and the transfer amount comparator 3.

The signal 118 is an internal signal of the DMA processor, and is a signal for transmitting the result of the comparison of the values of the transfer amount counter 2 and the transfer amount counter 4 by the transfer amount comparator 3 to the transfer control circuit 5. is there.

The signal 119 is an internal signal of the DMA processor, and is a signal for transmitting the value of the transfer amount counter 4 to the transfer control circuit 5 and the transfer amount comparator 3.

In FIG. 1, the external input / output processing device is D
When the MA data transfer becomes necessary, the DMA transfer request signal 105 is activated to request the DMA processing device 11 to perform the DMA transfer.

When the DMA transfer request signal 105 from the external input / output processing device becomes active, the transfer control circuit 5 of the DMA processing device 11 reads the transfer direction from the external storage device, that is, to the external input / output processing device. In the case of writing, the value of the transfer amount counter 2 and the transfer amount counter 4
Signal of the comparison result of the transfer amount comparator 3 comparing the values of
The comparison result is read at 18, and the comparison result indicates that the transfer amount indicated by the transfer amount counter 2 is larger than the transfer amount indicated by the transfer amount counter 4, that is, the transfer amount from the external storage device is external input / output. If the transfer amount is larger than the transfer amount to the processing device, it is determined that the DMA transfer data read from the external storage device is held in the temporary storage means 6, and the DMA transfer permission signal 106 and a series of The I / O device control signal 108 is activated.

Further, when the transfer direction is writing to the storage device,
That is, in the case of reading from the input / output processing device, the transfer control circuit 5 determines that the comparison result of the transfer amount comparator 3 comparing the value of the transfer amount counter 2 with the value of the transfer amount counter 4 is
This indicates that the transfer amount indicated by the transfer amount counter 2 is smaller than the transfer amount indicated by the transfer amount counter 4, that is, the transfer amount to the external storage device is smaller than the transfer amount from the external input / output processing device. In this case, it is determined that the data read from the external input / output processing device can be stored in the temporary storage means 6,
The DMA transfer permission signal 106 and the series of input / output device control signals 108 are activated.

The external input / output processing device writes to the external storage device, that is, from its own input / output processing device, in response to the DMA transfer permission signal 106 and the series of input / output device control signals 108 output from the transfer control circuit 5. In the case of reading, the control for outputting the data inside the self input / output processing device to the data signal 112 is executed, and in the case of reading from the external storage device, that is, in the case of writing to the self input / output processing device. Performs control such that the content of the data signal 112 is written inside the self input / output processing device.

At this time, the transfer control circuit 5 outputs the data in the external input / output processing device to the data signal 112 in the case of writing to the external storage device, that is, in the case of reading from the external input / output processing device. At that time, control is performed to store the state of the data signal 112 in the temporary storage means 6, and in the case of reading from an external storage device, that is, in the case of writing to an external input / output processing device. Outputs the valid data stored in the temporary storage means 6 to the data signal 112, and the external input / output processing device executes control such that the valid data can be taken into the own input / output processing device. Using 116, the process of updating the value of the transfer amount counter 4 by the transfer amount is executed.

The external input / output processing device inactivates the DMA transfer request signal 105 when the DMA transfer becomes unnecessary. Further, when the DMA transfer request signal 105 becomes inactive, the transfer control circuit 5 makes the DMA transfer permission signal 106 inactive and ends the DMA transfer with the input / output processing device.

On the other hand, when the DMA transfer request signal 105 from the external input / output processing device becomes active and the transfer direction is read from the storage device,
That is, in the case of writing to the input / output processing device, the comparison result of the transfer amount comparator 3 that compares the value of the transfer amount counter 2 with the value of the transfer amount counter 4 is the transfer amount indicated by the transfer amount counter 2. And the transfer amount indicated by the transfer amount counter 4 are the same, that is, the amount of data transferred from the external storage device is equal to the amount of data transferred to the external input / output processing device. At this time, it is determined that the DMA transfer data read from the external storage device is not held in the temporary storage means 6, the bus hold request signal 102 is activated, and the external central processing unit is stored in the external storage device. Request control.

Further, when the transfer direction is writing to the storage device,
That is, in the case of reading from the input / output processing device, the comparison result of the value of the transfer amount counter 2 and the value of the transfer amount counter 4 indicates that the transfer amount indicated by the transfer amount counter 2 and the transfer amount indicated by the transfer amount counter 4 are equal. If it indicates that the amount of data transferred to the external storage device is equal to the amount of data transferred from the external input / output processing device, the temporary storage means 6 receives the external input data. When it is determined that the data read from the output processing device cannot be stored, the bus hold request signal 102 is activated and the external central processing device is requested to control the external storage device.

When the bus hold request signal 102 becomes active, the external central processing unit receives the address signal 101.
And a series of storage device control signals 104 and a series of data signals 1
And a bus hold permission signal 103 indicating that the signal line for transmitting 11 is passed to the DMA processing device 11.
Activate

The transfer control circuit 5 uses the bus hold enable signal 1
03 becomes active, a series of address signals 101
And a series of storage device control signals 104 and a series of data signals 1
11 is started, and in the case of writing to the external storage device, control is performed to write the state of the data signal 111 to the address of the external storage device indicated by the address signal 101, and the external storage device In the case of reading from, the control for outputting the data stored in the address of the external storage device indicated by the address signal 101 to the data signal 111 is executed, and at the same time, writing to the external storage device, that is, In the case of reading from the input / output processing device, control for outputting the data stored in the temporary storage means 6 to the data signal 111 is executed, and reading from the external storage device, that is, external input / output. In the case of writing to the processing device, control such that the content of the data signal 111 is stored in the temporary storage means 6 is executed.

In this case, the storage device control signal 104 controlled by the transfer control circuit 5 and the control signal 113 of the temporary storage means 6 are controlled.
In the case of reading from an external storage device, that is, when writing to an external input / output processing device, the transfer control circuit 5 of the external storage device of the address indicated by the address signal 101 Data is output to the data signal 111 at the timing of the storage device control signal 104, and the DMA processing device 11
Data in an external storage device is transmitted to the temporary storage means 6
It is controlled so as to be taken into the temporary storage means 6 at the timing of being propagated to.

In the case of writing to the storage device, that is, reading from the input / output processing device, the transfer control circuit 5
At the timing of the control signal 113 of the temporary storage means 6 changes the data stored in the temporary storage means 6 to the data signal 11
1 to be propagated to the storage device, and the storage device control signal 1
04 at the timing when the data stored in the above-mentioned temporary storage means 6 propagates to the storage device.
The control is performed so that it is taken in at the address indicated by.

Upon completion of data transfer with a series of external storage devices, the transfer control circuit 5 causes the series of address signals 1
01, a series of storage device control signals 104, and a series of data signals 111 are released, and the bus hold request signal 102 is made inactive.

Further, the transfer control circuit 5 controls the signal 115 to update the value of the transfer amount counter 2 according to the transfer amount to the external storage device, and uses the signal 114 to transfer address generator. The transfer address to the external storage device in which 1 is generated is controlled so as to be updated according to the transfer amount.

During the DMA data transfer, when it is detected that the transfer control circuit 5 has reached the specified transfer amount by the value of the transfer amount counter 4 input to the transfer control circuit 5, the terminal count signal 107 is activated. And notifies the external input / output processing device that the specified amount of DMA data transfer is completed.

Next, the forced write request signal 109, which is input from the outside to the transfer control circuit 5 and requests to forcibly write the valid data stored in the temporary storage means 6 to the external storage device, becomes active. The operation of the case will be described.

In this case, the transfer control circuit 5 determines the state of the signal 118 input from the transfer amount comparator 3 and the external state only when the DMA transfer direction is writing to the storage device, that is, reading from the input / output processing device. Regardless of the state of the DMA transfer request signal 105 input from, the control is performed so that the valid data held in the temporary storage means 6 is written in the external storage device.

That is, the transfer control circuit 5 activates the bus hold request signal 102, and in response to this, the external central processing unit gives the control right of the storage device to the DMA processing unit 11.
When the bus hold enable signal indicating that the transfer has been made active becomes active, a series of address signals 101, a series of storage device control signals 104, and a series of data signals 11
1 is started, and control for writing the state of the data signal 111 to the address of the external storage device indicated by the address signal 101 is executed, and at the same time, the data stored in the temporary storage means 6 is transferred to the data signal 111. Execute the control output to. At this time, the storage device control signal 104 controlled by the transfer control circuit 5 and the control signal 113 of the temporary storage means 6 are synchronized, and the transfer control circuit 5 temporarily stores at the timing of the control signal 113 of the temporary storage means 6. The data stored in the means 6 is output to the data signal 111 and propagated to the storage device, and the storage device control signal 104 is transmitted to the storage device at the timing when the data stored in the temporary storage means 6 propagates to the storage device. The control is performed so that the data is taken into the address indicated by 101, the value of the transfer amount counter 2 is updated according to the transfer amount to the external storage device by using the signal 115, and further the transfer is performed by using the signal 114. The transfer address generated by the address generator 1 to the external storage device is controlled to be updated according to the transfer amount.

Further, when the transfer direction is writing to the storage device, that is, reading from the input / output processing device, the transfer control circuit 5 has already transferred the data held in the temporary storage means 6 to the external storage device. It has a function of outputting a valid data existence signal 110 indicating whether or not it has been written.

That is, the transfer control circuit 5 compares the value of the transfer amount counter 2 with the value of the transfer amount counter 4 when the transfer direction is writing to the storage device, that is, reading from the input / output processing device. The comparison result of the transfer amount comparator 3 is read by the signal 118, and the comparison result is the transfer amount counter 2
Indicates that the transfer amount indicated by the transfer amount counter 4 is greater than the transfer amount indicated by, that is, the amount of data transferred from the external input / output processing device is greater than the amount of data transferred to the external storage device. In this case, the valid data present signal 110 is activated so that the data held in the temporary storage means 6 is not written in the external storage device.

As described above, the DMA processing device 11 of FIG.
Is capable of externally supplying a forced write request signal 109 requesting to forcibly write the valid data stored in the internal temporary storage means 6 to an external storage device, and forcibly writes in response to the request. It has a function to perform and a function to output a valid data existence signal 110 indicating whether valid data exists in the internal temporary storage means 6 to the outside.

FIG. 2 is an internal block diagram of another embodiment of the DMA processor used in the present invention.

The DMA processing device 21 comprises the DMA processing device 11 described with reference to FIG. 1 and a mask circuit 22.

The signal 409 is an external input signal which is activated when an external input / output processing device which performs DMA data transfer with the storage device using the present DMA processing device 21 requests an interrupt processing from the central processing unit. This is an interrupt request signal from the output processing device. This interrupt request signal 409
Is a signal for requesting to forcibly write the valid data stored in the temporary storage means inside the DMA processing device 11 to the external storage device, that is, the forced write request signal 10 in FIG.
It is input to the DMA processor 11 as 9, and also to one input of the mask circuit 22.

The signal 110 is a signal output from the DMA processor 11 and indicating whether or not valid data is present in the internal temporary storage means, that is, the valid data present signal 110 in FIG. It is the other input.

The signal 410 is an output signal of the mask circuit 22, and is used as an interrupt request signal which becomes active when the central processing unit is requested to perform interrupt processing.

In the mask circuit 22, the valid data present signal 110 output from the DMA processor 11 is active,
That is, if the state indicating that valid data exists in the temporary storage means inside the DMA processing device 11 is input, the interrupt request signal 410 is always made inactive, and the valid data existence signal 110 is made inactive. That is, if a state indicating that valid data does not exist in the temporary storage means inside the DMA processing device 11 is input, the interrupt request signal 410 and the interrupt request signal 40 are input.
The state of 9 is output as it is.

Since the DMA processing device 21 of FIG. 2 has the above-mentioned configuration, the valid data presence signal 110 is inactive, that is, there is no valid data in the temporary storage means inside the DMA processing device 11. In this case, the state of the interrupt request signal 409 input from the input / output processing device is directly output to the interrupt processing device as the interrupt request signal 410. Further, when the valid data existence signal 110 is active, that is, when valid data exists, even if the state of the interrupt request signal 409 input from the input / output processing device becomes active, that is, the input / output processing device is at the center. Even if the processing device is requested to perform processing, the state of the interrupt request signal 410 does not immediately become active, and the interrupt request signal 409, that is, the forced write request signal 109.
Is activated, the DMA processing unit 11 executes a process for forcibly writing the valid data stored in the internal temporary storage unit into the storage unit, thereby the DMA
The interrupt request signal 410 becomes active only when valid data no longer exists in the temporary storage means inside the processing device 11 and the valid data existence signal 110 becomes inactive.

FIG. 3 is a block diagram of an embodiment of the information processing apparatus according to the present invention.

The information processing apparatus shown in FIG. 3 is an input / output processing apparatus that executes data transfer processing between a central processing unit 31 that controls the entire information processing apparatus, a readable / writable storage device 33, and an input / output device (not shown). 32, the DMA processing unit 21 of FIG. 2, and the input / output processing unit 32 arbitrate the input / output interrupt request which is required when the processing of the central processing unit 31 is required, and requests the central processing unit 31 for a specific interrupt processing. It is composed of an interrupt processing unit 34.

The signal 401 is the central processing unit 31 or DM.
A processing device 21 outputs and is input to the storage device 33,
It is a series of address signals indicating the address of the storage device 33 to be processed.

The signal 402 is output from the DMA processing unit 21 and input to the central processing unit 31, which is the DMA processing unit 2.
Reference numeral 1 is a bus hold request signal for requesting the control right of the storage device 33.

The signal 403 is output by the central processing unit 31,
This is a bus hold permission signal that is input to the DMA processing device 21 and indicates that the central processing unit 31 has given up the control right of the storage device 33.

The signal 404 is the central processing unit 31 or DM.
A signal output from the A processor 21 and input to the storage device 33, and a signal output from the storage device 33 to the central processing unit 31 or D
A series of storage device control signals for controlling reading and writing to the storage device 33 to be processed, which is composed of a signal input to the MA processing device 21.

The signal 405 is output from the input / output processing device 32 and input to the DMA processing device 21. A DMA transfer request indicating that the input / output processing device 32 requests the DMA processing device 21 for data transfer by DMA. It is a signal.

A signal 406 is a DMA transfer permission signal output from the DMA processing device 21 and input to the input / output processing device 32, which indicates that the DMA processing device 21 permits the data transfer by DMA to the input / output processing device 32. is there.

The signal 407 is a terminal count signal output from the DMA processor 21 and input to the input / output processor 32, which indicates that the data transfer of the input / output processor 32 by the DMA processor 21 has reached a specified amount. is there.

The signal 408 is composed of a signal output from the DMA processor 21 and input to the input / output processor 32, and a signal output from the input / output processor 32 and input to the DMA processor 21. Target I / O processing device 32
It is a series of input / output device control signals for controlling reading / writing from / to.

The signal 409 is output from the input / output processing unit 32 and input to the DMA processing unit 21, and becomes active when the input / output processing unit 32 requests the central processing unit 31 for interrupt processing. Is an interrupt request signal from the.

The signal 410 is output from the DMA processing unit 21 and input to the interrupt processing unit 34. From the I / O processing unit 32 which becomes active when the input / output processing unit 32 requests the central processing unit 31 for interrupt processing. Is a signal to be output to the interrupt processing device 34 under a certain condition.

The signal 411 is the central processing unit 31 or DM.
The A processing unit 21 outputs and the storage unit 33 inputs, or the storage unit 33 outputs and the central processing unit 31 outputs.
Alternatively, it is a series of data signals indicating data to be processed, which is input to the DMA processing device 21.

The signal 412 is output from the input / output processing unit 32 and input to the DMA processing unit 21, or DM
A series of data signals output from the A processing device 21 and input to the input / output processing device 32 are data to be processed.

The signal 413 is output from the interrupt processing unit 34 and input to the central processing unit 31.
Is an interrupt request signal for the.

The information processing apparatus shown in FIG. 3 is the input / output processing apparatus 3
2 requires DMA data transfer, the DMA transfer request signal 405 is activated, and the DMA processor 2
1 request DMA transfer.

The DMA processor 21 is an input / output processor 32.
When the DMA transfer request signal 405 from the device becomes active, if the transfer direction is reading from the storage device 33, that is, writing to the input / output processing device 32, the temporary storage means inside the DMA processing device 21 (see FIG. 1). In 6), it is checked whether or not there is valid data, that is, data that can be output to the input / output processing device 32, and the transfer direction is writing to the storage device 33, that is, from the input / output processing device 32. In the case of reading, it is checked whether the read data from the input / output processing device 32 can be stored in the temporary storage means inside the DMA processing device 21.

When the transfer direction is reading from the storage device 33 and valid data does not exist in the temporary storage means inside the DMA processing device 21, or when the transfer direction is writing to the storage device 33. When the read data from the input / output processing device 32 cannot be stored in the temporary storage means inside the DMA processing device 21, the DMA processing device 21 activates the bus hold request signal 402 to the central processing unit 31. In response, the control right of the storage device 33 is requested.

When the bus hold request signal 402 becomes active, the central processing unit 31 makes a series of address signals 4
01, a series of storage device control signals 404, and a signal line for transmitting a series of data signals 411 to the DMA processing device 21, and a bus hold permission signal 40 indicating the surrender.
Activate 3

When the bus hold enable signal 403 becomes active, the DMA processor 21 makes a series of address signals 40
1 and a series of storage device control signals 404 and a series of data signals 411 are started, and when writing to the storage device 33, the state of the data signal 411 is written to the address of the storage device 33 indicated by the address signal 401. Control is performed, and in the case of reading from the storage device 33, control is performed such that the data stored in the address of the storage device 33 indicated by the address signal 401 is output to the data signal 411. In the case of writing to the storage device 33, that is, reading from the input / output processing device 32, control is performed to output the data stored in the temporary storage means inside the DMA processing device 21 to the data signal 411,
Further, in the case of reading from the storage device 33, that is, when writing to the input / output processing device 32, control is performed so that the contents of the data signal 411 are stored in the temporary storage means inside the DMA processing device 21.

In this case, the storage device control signal 404 controlled by the DMA control device 21 and the control signal (113 in FIG. 1) of the temporary storage means inside the DMA processing device 21 are synchronized, and read from the storage device 33. That is, in the case of writing to the input / output processing device 32, the data in the storage device 33 at the address indicated by the address signal 401 is transferred to the storage device control signal 4
The data signal 411 is output at the timing of 04 and DMA is performed.
The control signal of the temporary storage means inside the DMA processing device 21 is propagated to the processing device 21, and the temporary storage inside the DMA processing device 21 is performed at the timing when the data in the storage device 33 described above is propagated to the temporary storage means inside the DMA processing device 21. Control so that it is taken into the means.

Writing to the storage device 33, that is,
When reading from the I / O processor 32, DMA
The storage device 3 outputs the data stored in the temporary storage means inside the DMA processing device 21 to the data signal 411 at the timing of the control signal of the temporary storage means inside the processing device 21.
3 and propagate the storage device control signal 404 to the above-mentioned DMA.
The control is performed so that the data stored in the temporary storage means inside the processing device 21 is taken into the address indicated by the address signal 401 at the timing when the data is propagated to the storage device 33.

When the transfer direction is reading from the storage device 33, the valid data is the DMA processing device 21.
The data output from the input / output processing unit 32 can be stored in the temporary storage unit inside the DMA processing unit 21 when it exists in the internal temporary storage unit or when the transfer direction is writing to the storage unit 33. In some cases, DMA processor 21 activates DMA transfer enable signal 406 and a series of I / O device control signals 408.

The input / output processing device 32 responds to the DMA transfer permission signal 406 and a series of input / output device control signals 408,
In the case of writing to the storage device 33, that is, when reading from the input / output processing device 32, control for outputting the data inside the input / output processing device 32 to the data signal 412 is executed,
Further, in the case of reading from the storage device 33, that is, when writing to the input / output processing device 32, control is performed so that the content of the data signal 412 is written inside the input / output processing device 32.

At this time, the DMA processing device 21 outputs the data in the input / output processing device 32 to the data signal 412 when writing to the storage device 33, that is, when reading from the input / output processing device 32. At this point, control is executed so that the state of the data signal 412 is stored in the temporary storage means inside the DMA processing device 21, and the storage device 33.
In the case of reading from, ie, writing to the input / output processing device 32, valid data stored in the temporary storage means inside the DMA processing device 21 is output to the data signal 412, and the input / output processing device 32 is Control is performed so that this effective data can be taken into the input / output processing device 32.

The input / output processing device 32 makes the DMA transfer request signal 405 inactive when the DMA transfer becomes unnecessary.

When the DMA transfer request signal 405 becomes inactive, the DMA processor 21 makes the DMA transfer permission signal 406 inactive and ends the DMA transfer.

During the DMA data transfer, when the data transfer between the storage device 33 and the input / output processing device 32 by the DMA processing device 21 reaches the specified amount, the DMA processing device 21 activates the terminal count signal 407. The I / O processor 32 is notified that the specified amount of DMA data transfer has been completed.

When the terminal count signal 407 is activated, the input / output processing unit 32 stops the data transfer with the input / output device and activates the interrupt request signal 409 to complete the DMA data transfer to the central processing unit 31. Request interrupt processing.

The interrupt request signal 409 is DMA
It may become active not only when the data transfer is completed, but also when the processing of the central processing unit 31 becomes necessary due to an error in the input / output processing unit 32.

Here, in the embodiment of FIG. 3, the interrupt request signal 409 is input to the DMA processing device 21, and the valid data stored in the temporary storage means inside the DMA processing device 21 as described in FIG. It is used as a signal (forced write request signal 109) for forcibly writing to an external storage device, and is also used as one input of a mask circuit (22 in FIG. 2) in the DMA processing device 21.

Mask circuit 2 in DMA processor 21
A signal (valid data presence signal 110 in FIG. 1) indicating whether valid data exists in the temporary storage means inside the DMA processing device 21 is inputted to the other input of 2, and the mask circuit 22 If the valid data presence signal 110 is active, that is, if the state indicating that valid data is present in the temporary storage means inside the DMA processing device 21 is input, the interrupt request signal 410 always outputs inactive. If the valid data present signal 110 is inactive, that is, if a state indicating that valid data does not exist in the temporary storage means inside the DMA processing device 21 is input, the interrupt request signal 410 indicates an interrupt request. The state of the signal 409 is output as it is.

When the interrupt request signal 409 becomes active, the DMA processing device 21 also makes the forced write request signal 109 active, so that the forced write processing is executed under a predetermined condition.

Therefore, when the interrupt request signal 409 from the input / output processing unit 32 becomes active, the valid data existence signal 110 becomes inactive, that is, there is no valid data in the temporary storage means inside the DMA processing unit 21. In this case, the state of the interrupt request signal 409 is immediately output to the interrupt processing device 34 by the interrupt request signal 410. On the contrary, when the valid data present signal 110 is active, that is, when valid data exists, the operation of reporting the state of the interrupt request signal 409 input from the input / output processing device 32 to the interrupt processing device 34 is a mask circuit. 22 is temporarily suspended. Then, in the DMA processing device 21, when the forced write request signal 409, that is, the forced write request signal 109 is activated, the DMA transfer direction is the writing to the storage device 33, that is, the reading from the input / output processing device 32. Is DMA
A process of forcibly writing the valid data stored in the temporary storage means inside the processing device to the storage device 33 is executed, whereby the valid data does not exist in the temporary storage means and the valid data existence signal 110 becomes inactive. Then, the state of the interrupt request signal 409 input from the input / output processing device 32 is reported to the interrupt processing device 34 at that time.

Forced writing is performed as follows.
That is, the DMA processor 21 receives the bus hold request signal 40
2 is activated and the central processing unit 31 is requested to control the storage unit 33. When the bus hold request signal 402 becomes active, the central processing unit 31 sets the address signal 401, a series of storage unit control signals 404, and a series of storage unit control signals 404. A signal line for transmitting the data signal 411 is released to the DMA processing device 21, and a bus hold permission signal 4 indicating the release
03 is activated. When the bus hold permission signal 403 becomes active, the DMA processing device 21 starts controlling the series of address signals 401, the series of storage device control signals 404, and the series of data signals 411, and the storage device 33 indicated by the address signal 401. Data signal 411 at the address
Control that writes the state of
The control for outputting the data stored in the temporary storage means inside the DMA processing device 21 to the data signal 411 is executed. At this time, the storage device control signal 404 and the control signal of the temporary storage means inside the DMA processing device 21 (113 in FIG. 1) are synchronized, and the DMA processing device 21 outputs the control signal 113 of the internal temporary storage means. At the timing, the data stored in the temporary storage means is output to the data signal 411 and propagated to the storage device 33, and the storage device control signal 404 is transmitted at the timing when the data stored in the temporary storage means propagates to the storage device 33. The control is performed so that the address signal 401 is taken in.

When the interrupt request signal 410 becomes active, the interrupt processor 34 determines the priority of the interrupt request signal 410 and the interrupt request signal (not shown) for the other central processing units, and determines the highest priority. The high interrupt request is transmitted to the central processing unit 31 using the interrupt request signal 413. Interrupt request signal 41
When 0 is the highest priority, the central processing unit 31 executes the process for the interrupt request signal 410 related to the interrupt request signal 409 from the input / output processing device 32 described above.

In the conventional information processing apparatus described with reference to FIG. 9, as described above, access to the input / output processing unit 93 for executing data transfer through the temporary storage means inside the DMA processing unit 92 is performed. Between the storage device 94 and the input / output processing device 93 when the DMA data transfer direction is writing to the storage device 94, that is, reading from the input / output processing device 93. As a means for ensuring the consistency of the data of the above, it is necessary for the central processing unit 91 to execute two types of interrupt processing, an interrupt request output from the input / output processing unit 93 and an interrupt request output from the DMA processing unit 92. there were.

On the other hand, in the information processing device of FIG. 3, the interrupt request signal 409 from the input / output processing device 32 is used.
To the DMA processing device 21, and the interrupt request signal 40
When 9 becomes active, valid data is held in the temporary storage means inside the DMA processing unit, and this is forcibly written in the storage unit 33, during which the central processing requested by the input / output processing unit 32 is requested. The interrupt request to the device 31 is temporarily suspended inside the DMA processing device 21, and the DM
The central processing unit 31 requested by the input / output processing unit 32 held in the DMA processing unit 21 at the time of writing the valid data held in the temporary storage means inside the A processing unit 21 into the storage unit 33. By outputting the interrupt request to the interrupt processing device 34, the consistency of the data in the storage device 33 and the input / output processing device 32 can be ensured. Therefore, as in the conventional case, the central processing unit 31 is
The processing for an interrupt request generated at the time when the MA processing device 21 writes the valid data held in the temporary storage means inside the DMA processing device into the storage device 33 becomes unnecessary, and the fly-by transfer method described with reference to FIG. DM
When the information processing apparatus adopting the A processing apparatus 82 adopts the information processing apparatus of FIG. 3 for the purpose of improving the system performance, a conventional fly-by transfer type DMA processing apparatus 82 is used.
There is an effect that the processing program of the information processing apparatus adopting can be executed as it is.

FIG. 4 is a block diagram of another embodiment of the information processing apparatus according to the present invention, and the same reference numerals as those in FIG. 3 indicate the same parts.

The information processing apparatus shown in FIG. 4 is replaced by the information processing apparatus shown in FIG.
The DMA processing device 11 is used, and the input / output processing device 41 as shown in FIG.

Referring to FIG. 5, the input / output processing device 41
Is an input / output processing circuit 42 that executes input / output processing with an external input / output device and interfaces with the central processing unit 31.
And a mask circuit 43.

The signal 110 is the DMA processor 11 of FIG.
The valid data present signal 110, which is a signal indicating whether or not valid data is present in the temporary storage means inside the DMA processing device 11, which is input from one side of the mask circuit 43.

The signal 409 is an interrupt request signal from the input / output processing circuit 42, which is output from the input / output processing circuit 42 and is output when the input / output processing device 41 needs the processing of the central processing unit 31. This signal 409 becomes the other input of the mask circuit 43, and is output to the DMA processing device 11 as the forced write request signal 109.

The signal 501 is an output signal of the mask circuit 43, and is used as a signal which becomes active when the input / output processing unit 41 requests the central processing unit 31 for interrupt processing.

The mask circuit 43 outputs the valid data presence signal 1
If 10 is active, that is, if a state indicating that valid data exists in the temporary storage means inside the DMA processor 11, the interrupt request signal 501 is always made inactive and the valid data present signal 110 Is inactive, that is, if a state indicating that valid data does not exist in the temporary storage means inside the DMA processing device 11 is input, the state of the interrupt request signal 409 is output as it is to the interrupt request signal 501. To do.

Since the input / output processing unit 41 of FIG. 5 has the above-mentioned configuration, the valid data presence signal 110 is inactive, that is, valid data exists in the temporary storage means inside the DMA processing unit 11. If not, the state of the interrupt request signal 409 from the input / output processing circuit 42 is directly used as the interrupt request signal 501.
4 to the central processing unit 31. Further, when the valid data existence signal 110 is active, that is, when valid data exists, even if the state of the interrupt request signal 409 from the input / output processing circuit 42 becomes active, that is, the input / output processing circuit 42 is in the center. Even if the processing device 31 is requested to perform processing, the interrupt request signal 501 does not immediately become active, but the interrupt request signal 409 becomes active, that is, the forced write request signal 109 becomes active. 11 forcibly writes the valid data stored in the internal temporary storage means to the storage device 33, whereby
The interrupt request signal 501 is not provided until the valid data present signal 110 becomes inactive because there is no valid data in the temporary storage means inside the DMA processing device 11.
Becomes active.

By the way, in the information processing apparatus of FIG.
When the data transfer between the storage device 33 and the input / output processing device 41 by the DMA processing device 11 reaches the specified amount during the A data transfer, the DMA processing device 11 activates the terminal count signal 407 to perform the input / output processing. The device 41 is notified that the specified amount of DMA data transfer is completed.

Input / output processing circuit 42 of input / output processing device 41
When the terminal count signal 407 is activated, the data transfer with the input / output device is stopped and the interrupt request signal 409 is activated. The interrupt request signal 409 may be activated not only when the DMA data transfer is completed, but also when the processing of the central processing unit 31 is necessary such as an error in the input / output processing unit 41. .

Here, in the embodiment of FIG. 4, the interrupt request signal 409 is the DMA processor 1 as shown in FIG.
1 is input as the forced write request signal 109 and is also used as one input of the mask circuit 43 in the input / output processing device 41.

Mask circuit 4 in input / output processing unit 41
A valid data present signal 110 indicating whether valid data exists in the temporary storage means inside the DMA processing device 11 is inputted to the other input of the masking circuit 43.
Indicates that the valid data present signal 110 is active, that is, DM
If a state indicating that valid data exists in the temporary storage means inside the A processor 11 is input, the interrupt request signal 501 always outputs inactive,
The valid data present signal 110 is inactive, that is, DM
If a state indicating that valid data does not exist in the temporary storage means inside the A processor 11 is input,
The interrupt request signal 501 includes an interrupt request signal 409.
The state of is output as it is.

Therefore, when the interrupt request signal 409 from the input / output processing circuit 42 becomes active, the valid data existence signal 110 becomes inactive, that is, there is no valid data in the temporary storage means inside the DMA processing device 11. In this case, the state of the interrupt request signal 409 is immediately output to the interrupt processing device 34 by the interrupt request signal 501. On the contrary, when the valid data presence signal 110 is active, that is, when valid data is present, the operation of reporting the state of the interrupt request signal 409 from the input / output processing circuit 42 to the interrupt processing unit 34 is temporarily suspended. To be done. Then, in the DMA processing device 11, when the forced write request signal 109 becomes active, DM
When the A transfer direction is writing to the storage device 33, that is, reading from the input / output processing device 41, the valid data stored in the temporary storage means inside the DMA processing device 11 is forcibly written to the storage device 33. When the processing is executed, the valid data no longer exists in the temporary storage means, and the valid data presence signal 110 becomes inactive, the input / output processing circuit 4 in the input / output processing device 41 at that time.
The state of the interrupt request signal 409 from the mask circuit 4
Interrupt request signal 5 to the interrupt processor 34 through
Reported as 01.

The operation during forced writing and the operation during normal data transfer are performed in the same manner as in the embodiment of FIG.

As described above, in the information processing apparatus described with reference to FIG. 4, the interrupt request signal 409 from the input / output processing circuit 42 of the input / output processing apparatus 41 of FIG. 5 is used as the forced write request signal 109. DMA processing device 1
1 and the interrupt request signal 409 from the input / output processing circuit 42 becomes active, the DMA processing device 1
1. When valid data is held in the temporary storage means inside 1, the valid data is forcibly written in the storage device 33, and during that time, the interrupt request to the central processing unit 31 requested by the input / output processing circuit 42 is input / output processed. When the valid data held in the temporary storage means inside the DMA processing device 11 is written in the storage device 33 by temporarily holding it in the mask circuit 43 of the device 41, the held input / output processing circuit 42 makes a request. By outputting an interrupt request to the central processing unit 31 to the interrupt processing unit 34, it is possible to ensure data consistency between the storage unit 33 and the input / output processing unit 41. Therefore, as in the conventional case, the central processing unit 31 uses the DMA
The processing for the interrupt request generated when the processing device 11 writes the valid data held in the temporary storage means inside the DMA processing device into the storage device 33 becomes unnecessary,
When the information processing apparatus employing the fly-by transfer type DMA processing apparatus 82 described with reference to FIG. 8 adopts the information processing apparatus of FIG. 4 for the purpose of improving system performance,
There is an effect that the processing program of the information processing apparatus adopting the conventional DMA processing apparatus of the fly-by transfer method can be executed as it is.

FIG. 6 is a block diagram of still another embodiment of the information processing apparatus according to the present invention, and the same reference numerals as those in FIGS. 3 and 4 denote the same parts.

The information processing apparatus shown in FIG. 6 is replaced with the DMA processing apparatus 21 of the information processing apparatus of the embodiment shown in FIG.
Using the DMA processing device 11 of
Instead, an interrupt processing device 61 as shown in FIG. 7 is used.

Referring to FIG. 7, the interrupt processing device 61.
Determines the priority order of the interrupt request signals to the various central processing units 31, and uses the interrupt request signal 413 to determine the priority level of the interrupt request having the highest priority.
It is composed of an interrupt processing circuit 62 for transmitting information to a mask circuit 63 and a mask circuit 63.

The signal 110 is the DMA processor 11 of FIG.
Is a signal indicating whether or not valid data is present in the temporary storage means inside the DMA processing device 11, that is, a valid data present signal 110, which is one input of the mask circuit 63.

A signal 601 is an interrupt request signal from the input / output processing unit 32, which is input from the input / output processing unit 32 and is output when the input / output processing unit 32 requires the processing of the central processing unit 31. This signal becomes the other input of the mask circuit 63, and the forced write request signal 10
9 to the DMA processing device 11.

The signal 602 is a signal output from the mask circuit 63 and input to the interrupt processing circuit 62.

The signal 413 is a signal output from the interrupt processing circuit 62, and is a signal that becomes active when the interrupt processing device 61 requests the external central processing unit 31 for interrupt processing.

The mask circuit 63 uses the valid data presence signal 1
If 10 is active, that is, if a state indicating that valid data is present in the temporary storage means inside the DMA processor 11 is input, the signal 602 is always made inactive, and the valid data present signal 110 becomes inactive. If an active state, that is, a state indicating that valid data does not exist in the temporary storage means inside the DMA processing device 11, is input, the state of the interrupt request signal 601 from the input / output processing device 32 is added to the signal 602. Is output as is.

In addition to the signal 602, another interrupt request signal (not shown) to the central processing unit 31 is also added to the interrupt processing circuit 62, and the interrupt request signal 413 is selected by selecting the interrupt request with the highest priority. To the central processing unit 31.

Since the interrupt processing device 61 of FIG. 7 has the above-mentioned configuration, when the valid data presence signal 110 is inactive, that is, when there is no valid data in the temporary storage means inside the DMA processing device 11. Outputs the state of the interrupt request signal 601 input from the input / output processing device 32 to the interrupt processing circuit 62. Further, when the valid data presence signal 110 is active, that is, when valid data exists, even if the state of the interrupt request signal 601 input from the input / output processing device 32 becomes active, that is, the input / output processing device 32. When the CPU requests the central processing unit 31 for processing, the signal 602 is not immediately activated, but the interrupt request signal 601 becomes active, that is, the forced write request signal 109 becomes active, so that the DMA processing device 11 forcibly writes the valid data stored in the internal temporary storage means to the storage device 33, whereby the valid data does not exist in the temporary storage means inside the DMA processing device 11 and the valid data is deleted. The signal 602 becomes active only when the presence signal 110 becomes inactive.

When the signal 602 becomes active, it becomes the selection target of the interrupt processing circuit 62, and the signal 60
When the interrupt request for 2 is selected, it is transmitted to the central processing unit 31 as an interrupt request signal 413. That is, when the signal 602 input from the mask circuit 63 becomes active, the interrupt processing circuit 62 sends an interrupt request signal (not shown) to the other central processing unit 31,
The priority order with respect to the above-mentioned signal 602 is determined, and the interrupt request having the highest priority is requested to the central processing unit 31 using the interrupt request signal 413. When the signal 602 input from the mask circuit 63 has the highest priority, the central processing unit 31 executes the processing for the interrupt request signal 601 from the input / output processing unit 32 described above.

By the way, in the information processing apparatus of FIG.
When the data transfer between the storage device 33 and the input / output processing device 32 by the DMA processing device 11 reaches the specified amount during the A data transfer, the DMA processing device 11 activates the terminal count signal 407 to perform the input / output processing. The device 32 is notified that the transfer of the specified amount of DMA data is completed.

When the terminal count signal 407 is activated, the input / output processing unit 32 stops the data transfer with the input / output device and activates the interrupt request signal 601 to end the DMA transfer to the central processing unit 31. Request interrupt processing. The interrupt request signal 601
May become active not only when the DMA data transfer is completed, but also when the processing of the central processing unit 31 becomes necessary due to an error occurrence in the input / output processing unit 32.

Here, in the embodiment of FIG. 6, the interrupt request signal 601 becomes one input of the mask circuit 63 of the interrupt processing device 61 as shown in FIG. 7, and D
DM is obtained by converting the valid data stored in the temporary storage means inside the MA processing device 11 into a forced write request signal 109 for forcibly writing to the external storage device 33.
It is input to the A processor 11.

To the other input of the mask circuit 63 in the interrupt processing device 61, a valid data existence signal 110 indicating whether or not valid data exists in the temporary storage means inside the DMA processing device 11 is inputted, and the mask Circuit 6
3, the valid data present signal 110 is active, that is, D
If a state indicating that valid data exists in the temporary storage means inside the MA processing device 11 is input,
The input signal 602 of the interrupt processing circuit 62 is made inactive, the valid data existence signal 110 is made inactive,
That is, if a state indicating that valid data does not exist in the temporary storage means inside the DMA processing device 11 is input, the input signal 602 to the interrupt processing circuit 62 is input.
As an interrupt request signal 6 from the input / output processing device 32.
The state of 01 is output as it is.

Therefore, when the interrupt request signal 601 from the input / output processing unit 32 becomes active, the valid data existence signal 110 becomes inactive, that is, there is no valid data in the temporary storage means inside the DMA processing unit 11. In this case, the state of the interrupt request signal 601 output from the input / output processing device 32 is immediately output to the interrupt processing circuit 62 by the signal 602. On the contrary, when the valid data presence signal 110 is active, that is, when valid data exists, the operation of reporting the state of the interrupt request signal 601 input from the input / output processing device 32 to the interrupt processing circuit 62 is temporarily performed. Pending Then, in the DMA processing device 11, when the forced write request signal 109 becomes active and the DMA transfer direction is writing to the storage device 33, that is, reading from the input / output processing device 32, the DMA processing device 11 When the process of forcibly writing the valid data stored in the internal temporary storage means to the storage device 33 is executed, and when the valid data does not exist in the temporary storage means and the valid data existence signal 110 becomes inactive, the processing is executed. At this time, the state of the interrupt request signal 601 input from the input / output processing device 32 is the signal 60.
2 is output to the interrupt processing circuit 62.

The operation during forced write and the operation during normal data transfer are the same as in the embodiment of FIG.

As described above, in the information processing device described with reference to FIG. 6, the interrupt request signal 601 of the input / output processing device 32 is input to the interrupt processing device 61 of FIG. Data present signal 1
When 10 is input to the interrupt processing device 61 and the interrupt request signal 601 from the input / output processing device 32 is activated, the valid data is stored in the temporary storage means inside the DMA processing device 11 when it is stored. The write request is forcibly written in the device 33, and during that time, the interrupt request to the central processing unit 31 requested by the input / output processing device 32 is temporarily suspended in the interrupt processing device 61, and the DMA processing device 11
At the time when the valid data held in the internal temporary storage means is written in the storage device 33, the interrupt request to the central processing unit 31 requested by the input / output processing device 32 that has been held is interrupted by the interrupt processing device 61. Processing circuit 62
By outputting the data to the storage device 33, the consistency of the data in the storage device 33 and the input / output processing device 32 can be ensured. Therefore, unlike the conventional case, the central processing unit 31 does not need to process the interrupt request generated when the DMA processing unit 11 writes the valid data held in the temporary storage means inside the DMA processing unit into the storage unit 33. The DMA processor 8 of the fly-by transfer system described with reference to FIG.
When the information processing apparatus adopting No. 2 adopts the information processing apparatus of FIG. 6 for the purpose of improving the system performance, the processing program of the information processing apparatus adopting the conventional fly-by transfer DMA processing apparatus can be executed as it is. There is an effect.

[0214]

[0215]

As described above , according to the information processing apparatus of the present invention, it is possible to secure the consistency of data during the DMA data transfer of the 2-cycle transfer system between the DMA processing apparatus and the input / output processing apparatus. The same processing as the fly-by transfer method described with reference to FIG. 8 can be achieved while causing the central processing unit to perform the same processing. Therefore, the flyby transfer method D
Even when the information processing apparatus adopting the MA processing apparatus adopts the 2-cycle transfer type DMA processing apparatus for the purpose of improving the system performance or converting the byte width, it is not necessary to change the processing program of the central processing unit. Has the effect of.

[Brief description of the drawings]

FIG. 1 is an internal block diagram of an embodiment of a DMA processing device used in the present invention.

FIG. 2 is an internal block diagram of another embodiment of a DMA processing device used in the present invention.

FIG. 3 is a block diagram of an embodiment of an information processing device according to the present invention.

FIG. 4 is a block diagram of another embodiment of the information processing apparatus according to the present invention.

FIG. 5 is a block diagram of a configuration example of an input / output processing device 41.

FIG. 6 is a block diagram of still another embodiment of the information processing apparatus according to the present invention.

FIG. 7 is a block diagram of a configuration example of an interrupt processing device 61.

FIG. 8 is a block diagram of an information processing device using a general DMA processing device.

FIG. 9 is a block diagram of an information processing device using a DMA processing device according to a 2-cycle data transfer system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transfer address generator 2 ... Transfer amount counter 3 ... Transfer amount comparator 4 ... Transfer amount counter 5 ... Transfer control circuit 6 ... Temporary storage means 11, 21 ... DMA processing device 22, 43, 63 ... Mask circuit 31 ... Central Processing device 32, 41 ... Input / output processing device 33 ... Storage device 34, 61 ... Interrupt processing device 42 ... Input / output processing circuit 62 ... Interrupt processing circuit 101, 401 ... Address signal 102, 402 ... Bus hold request signal 103, 403 ... Bus hold enable signal 104, 404 ... Storage device control signal 105, 405 ... DMA transfer request signal 106, 406 ... DMA transfer enable signal 107, 407 ... Terminal count signal 108, 408 ... I / O device control signal 109 ... Forced write request signal 110 ... Effective data present signal 111, 112, 411, 412 ... Data Signal 113-119 ... signal 409,410,413,501,601 ... interrupt request signal

Claims (3)

(57) [Claims] 1. A central processing unit, a storage device accessible from now on, an input / output processing unit, and data transfer between the storage unit and the input / output processing unit using an internal temporary storage unit. In an information processing device including a DMA processing device that performs a cycle transfer method and an interrupt processing device, the DMA processing device stores in the storage device data received from the input / output processing device and held in the temporary storage means. Means for outputting a valid data existence signal indicating whether or not there is data that has not been transferred, and data received from the input / output processing device and held in the temporary storage means in response to the forced write request signal. Means for transferring data that has not yet been transferred to the storage device to the storage device, and the input / output processing device according to the valid data existence signal A masking means for masking the interrupt request signal from the above and transmitting it to the interrupt processing device, and giving an interrupt request signal before masking of the input / output processing device to the DMA processing device as the forced write request signal. An information processing device comprising: 2. A central processing unit, a storage device accessible from now on, an input / output processing unit, and data transfer between the storage unit and the input / output processing unit using an internal temporary storage unit. In an information processing device including a DMA processing device that performs a cycle transfer method and an interrupt processing device, the DMA processing device stores in the storage device data received from the input / output processing device and held in the temporary storage means. A means for outputting to the outside a valid data existence signal indicating whether or not there is data that has not been transferred, and, in response to a forced write request signal, received from the input / output processing device and held in the temporary storage means. Means for transferring to the storage device data that has not yet been transferred to the storage device, and the input / output processing device The interrupt request signal from its own input / output processing device by a data presence signal and transmitting the masked interrupt request signal to the interrupt processing device. An information processing device having a configuration for giving it to the DMA processing device as a signal. 3. A central processing unit, a storage device accessible from now on, an input / output processing unit, and data transfer between the storage unit and the input / output processing unit using an internal temporary storage unit. In an information processing device including a DMA processing device that performs a cycle transfer method and an interrupt processing device, the DMA processing device stores in the storage device data received from the input / output processing device and held in the temporary storage means. A means for outputting to the outside a valid data existence signal indicating whether or not there is data that has not been transferred, and, in response to a forced write request signal, received from the input / output processing device and held in the temporary storage means. Means for transferring to the storage device data that has not yet been transferred to the storage device, and the interrupt processing device comprises: Comprises a mask means for masking the interrupt request signal from the output processing unit by a data present signal,
Further, the information processing apparatus has a configuration in which an interrupt request signal before masking of the input / output processing device is given to the DMA processing device as the forced write request signal.