JPH05108493A - Memory control system - Google Patents

Abstract

PURPOSE:To prevent system down by providing the configuration in which duplexing is attainable by arbitrarily specifying specific memory area so as to duplex important memory area. CONSTITUTION:The hardware of a memory system is constituted with the same amount of memories 21 and 22. Each memory area is further divided into (n) numbers of area. The each area divided into by n number is assigned to each bit in a register 10 consisting of n bits, and its correspondence is stared in OS. OS can specify each area as duplexing area. When a CPU 1 executes memory accessing, a selector means 11 decides whether an accessing object is duplexing area or not by referring to the register 10. If it is found to be duplexing area, a memory control device 30 permits data output from a memory 21. At this time, when the error signal coming from an error detecting device 41 is detected, the memory control device 30 puts the data from the memory 22 on a memory bus 5. Then, an acknowledge signal generating device 70 outputs an anknowledge signal 8 at data confirmation timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory control system,
In particular, the present invention relates to a memory control method in a system that places importance on reliability.

[0002]

2. Description of the Related Art A conventional memory control system will be described with reference to FIG. In FIG. 2, 1 is a central processing unit (hereinafter referred to as CP
U), and the software runs on the CPU 1. A memory 2 stores instructions and data used by the CPU 1. Reference numeral 3 denotes a memory control device, which gives a control signal (RAS / CAS, etc.) to the memory 2. An error detection device 4 checks the content of the data when reading the data from the memory 2 and sends an error signal 6 to the CPU 1 when an error is detected. 5 is a memory 2 and a CPU
A memory bus for connecting 1 and 7 is an acknowledge signal generating device, which outputs an acknowledge signal 8 for notifying the CPU 1 of the data acquisition timing.

The memory access operation in FIG. 2 is performed as follows. When the CPU 1 reads the memory 2,
A memory access request is issued to the memory control device 3, and the memory control device 3 outputs a control signal to the corresponding physical address. The memory 2 receiving the control signal is connected to the memory bus 5
Output the data to. At that time, the error detection device 4 checks the data output from the memory 2, and if an error is detected within the data fixed range, the error signal 6 is set to CP.
Output to U1 to stop the operation of CPU1. When no error is detected, the error signal 6 is not output and the CPU 1 continues the process. It should be noted that regardless of whether or not an error is detected, the acknowledge signal generation device 7 is a CPU.
An acknowledge signal 8 is output to 1 and the CPU 1 acquires data at that timing and ends the memory access cycle.

[0004]

In the above-mentioned conventional memory control method, when a memory failure occurs, the operation of the CPU is unconditionally stopped. Therefore, in any case, the system is down and it is necessary to restart the system. There is a drawback.

It is an object of the present invention to provide a memory control system which can duplicate an important part of a memory and prevent the occurrence of a system down.

[0006]

According to the memory control method of the present invention, each of the memories is divided into n areas and two corresponding memories can be used by duplicating each area. An error detection device connected to
A register having an n-bit structure that indicates whether or not each n-divided area of each memory is a duplicated area according to the value of each bit, and a control signal is sent to control the operation of each memory to duplicate. A memory control device that outputs the contents of the other when an error is detected in one of the activation areas, an acknowledge signal generation device that outputs an acknowledge signal indicating the timing of data acquisition permission to the CPU, and an output of the error detection device. An error signal output device for controlling the transfer to the CPU,
If the address currently being accessed is 2 by referring to the register
It comprises selector means for judging whether or not it is an overlap area and controlling the memory control device, the error signal output device and the acknowledge signal generation device.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 1 is a CPU, 21 and 22.
Is a memory, 30 is a memory control device, and 41 and 42 are error detection devices corresponding to the memories 21 and 22, respectively. 5 is a memory bus, 70 is a CP for acknowledge signal 8
An acknowledge signal creating device for sending to U1, 9 is a CPU for outputting the output of the error detecting devices 41, 42 as an error signal 6
It is an error signal output device for controlling whether to output to 1. A register 10 has a bit number corresponding to the number of divided areas of the memories 21 and 22, and is a register that determines whether or not to duplicate the corresponding memory area depending on the state of each bit, and can be set by software. Reference numeral 11 refers to the register 10 to determine whether or not the target of the access request from the CPU 1 is the memory duplication area.
0, the error signal output device 9 and the acknowledge signal generation device 70 are selector means having a function of giving an instruction.

Memory system hardware (hereinafter H /
W) is divided into two, as shown in FIG. 1, into a memory 21 and a memory 22 having the same capacity, and each memory area of the memories 21 and 22 is further divided into n physical address areas. .. The purpose of each divided physical address area is determined by virtual memory management of an operating system (hereinafter referred to as OS).

In the H / W configuration, each physical address area divided into n is assigned to each bit of the register 10, and the correspondence is stored in the OS.

Then, the OS can designate any of these n-divided physical address areas as a memory duplication area (OS resident area, etc.) (this designation can be dynamically changed). The bit corresponding to the specified physical address area of the register 10 is set to "1".

The operation when the CPU 1 accesses the memory in the situation where the memory duplication area is set as described above will be described below. Here, it is assumed that when the memory duplicated area is accessed, the data is output from the memory 21 in the normal case where no error has occurred.

First, the case where the CPU 1 accesses the memory duplicated area will be described.

When the CPU 1 activates the write access to the memory, the selector means 11 judges the physical address to be accessed and compares it with the contents of the register 10, and if the physical address to be accessed is the memory duplication area. , The control signal is output from the memory control device 30 to both the memories 21 and 22 in the same manner. As a result, the same data is written in the memories 21 and 22.

Next, when the CPU 1 performs a read operation to the memory, when the selector means 11 similarly determines that the area is a memory duplicated area, it sends an addressing control signal to the memories 21 and 22. Output to both sides. here,
When no error signal is detected from any of the error detection devices 41 and 42, the memory control device 30 enables the output to the memory bus 5 only for the memory 21 so that the data is output from the memory 21. Send the control signal to set the status. Then, at the data confirmation timing, acknowledge signal generating device 70 outputs acknowledge signal 8 to CPU 1 and the memory read cycle ends.

On the other hand, when only the error detection device 41 detects an error, if the currently accessed address is the memory duplication area, the error signal output device 9 is set to the cutoff state by the instruction from the selector means 11. Has become CP
The error signal 6 is not output to U1. When the error signal from the error detection device 41 is detected, the memory control device 30 disables the output of the memory 21,
Instead, the output of the memory 22 is enabled and the data in the memory 22 is loaded on the memory bus 5. Then, in consideration of the timing when the data from the memory 22 is fixed,
The acknowledge signal generating device 70 returns the acknowledge signal 8 to the CPU 1 to end the memory read cycle.

After that, the OS sets all the contents of the register 10 to "0" and restores the contents of the duplicated physical address area of the memory 22 to the memory 21 in order to recover the damaged data in the memory 21. Copy to the physical address area, restore the register 10 to the original state, and finish the processing.

If only the error detection device 42 detects an error, the OS reads the data from the memory 21 after the data is normally read from the memory 21 and the memory read cycle ends.
In order to recover the broken data of the above, the copy processing similar to the above is performed from the memory 21 to the memory 22.

When an error is detected by both the error detecting devices 41 and 42, the error signal output device 9 immediately outputs the error signal 6 to the CPU 1 to stop the CPU 1.

If the physical address to be accessed is not the memory duplication area, the memory 21 and the memory 22 are
And operate as memories independent of each other and perform the same operation as the case described in the related art. That is, since the error signal output device 9 outputs the error signals of the error detection devices 41 and 42 as they are to the CPU 1 as the error signal 6, the CPU 1 immediately stops when an error is detected.

[0022]

As described above, according to the memory control method of the present invention, a specific memory area can be arbitrarily designated and duplicated, and the other area can be used as a normal single memory. By mapping different programs and data to the memory duplication area, when an intermittent failure of the memory occurs, it is possible to prevent the data from being destroyed without immediately leading to the system down, and to construct a highly reliable system.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a conventional memory control system.

[Explanation of symbols]

 1 CPU 2, 21, 22 Memory 3,30 Memory Control Device 4, 41, 42 Error Detection Device 5 Memory Bus 6 Error Signal 7, 70 Acknowledge Signal Creating Device 8 Acknowledge Signal 9 Error Signal Output Device 10 Register 11 Selector Means

Claims (1)

[Claims] 1. Two memories, each of which is divided into n areas and can be used by duplicating corresponding areas, an error detection device connected to each of the memories, and each bit. A register having an n-bit structure indicating whether or not each of the n-divided areas of each memory is a duplicated area, and a control signal is sent to control the operation of each memory to duplicate the duplicated area. If an error is detected in one of the two, the memory controller that outputs the contents of the other and an acknowledge signal indicating the timing of data acquisition permission to the CPU
To the CPU, an error signal output device for controlling the transfer of the output of the error detection device to the CPU, and the register to determine whether or not the currently accessed address is a duplex region. A memory control system comprising: a memory control device, an error signal output device, and selector means for controlling an acknowledge signal generation device.