JPS6018899A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify a selecting circuit and to quicken circuit operation by allowing non-selection of a defective memory cell to be conducted through the blown fuse element connected to a selecting line. CONSTITUTION:Selection signals 3-3' are given to selection circuits 11-11' at normal operation and one of memory cells 14-14' is selected depending on the content. Selecting signals 1-2 by which memory cells 12-13 are not selected are given to selection circuits 8-9 by a redundancy control circuit. If a defect is found out in the memory cells 14-14', even if the defective memory cell is selected by a selection signal, the signal is not transmitted to the selection line by allowing a fuse element connected to the selection line selecting said memory cell to be blown so as to make the defective memory cell unselected. Even if the defective memory cell is selected, the memory is replaced into the redundancy memory cell instead for selection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory provided on a semiconductor substrate and having a redundant circuit for relieving defects.

[Technical background of the invention and its problems]

In semiconductor memories provided on semiconductor substrates, as large-capacity memories with highly integrated memory cells on a single chip are developed, manufacturing yields are decreasing due to defects in the semiconductor substrate and defects that occur during the manufacturing process. It is becoming a problem that the Therefore, in order to remedy the above-mentioned defects, a method has been adopted in which the defective parts are replaced with redundant circuits provided on the same chip.

FIG. 1 is a circuit diagram showing a conventional example of a defect relief method.

If there is no defect in the normal memory cells 14-24', a redundancy control circuit (not shown) generates signals 1-2 that do not select the redundant memory cells 12-19.
Redundant selection circuit 8 (NAND circuit 82, inverter 8.
9 (NAND circuit 911, inverter 9.) to 9 (NAND circuit 911, inverter 9. At the same time, a circuit 10 (consisting of a NAND circuit 101 and an inverter 10. , inverter xx, good) ~ J2' (consisting of NAND circuit 11.', inverter II!')
and one of the normal memory cells I4 to J4' is selected. If a defect is found in the memory cell I4-21', a signal corresponding to the selection signal 3 or 3' of the defective cell is sent to the selection signal i by the redundant control circuit.
.about.2 to the selection circuits 8-9, and as a result, one of the memory cells 12-13 is selected using the redundancy selection lines 5-6. At the same time, a signal 4 indicating that the redundant memory cell has been selected is transmitted from the detection circuit 10 (consisting of a NAND circuit ZO and an inverter 1θ!) to the normal selection circuit 1l-F.
l' to deselect normal memory cells.

In this way, even if a defect is found in a normal memory cell, the defect can be repaired by replacing it with a redundant memory cell using a redundancy control circuit.

However, in the conventional redundancy circuit described above, when replacing a defective memory cell by selecting a redundant memory cell, it detects that the redundant memory cell has been selected and uses the detection signal to replace the defective memory cell with a normal one. Since memory cells are not selected, there is a risk of double selection of normal memory cells and redundant memory cells. To avoid this, it is necessary to introduce a time delay into the redundant selection line, which poses a problem in speeding up the process.

In addition, a normal selection circuit also requires a circuit for non-selection by the above-mentioned detection signal, which makes the circuit complicated and has a 1ifP point in speeding up due to circuit delay.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor memory in which the normal and redundant selection circuits can be simplified and the speed of one circuit can be increased.

[Summary of the invention]

The present invention inserts a fuse element between a normal selection circuit and a selection line that selects a normal memory cell.If a defect is found in a normal memory cell, it is connected to the selection line of that memory cell. By disconnecting the fuse element that has been selected and making the defective memory cell non-selectable, the circuit for detecting that a redundant circuit has been selected and its detection signal can be omitted, and the normal selection circuit can be simplified and the circuit can be simplified. This is to achieve high speed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Second
Although the figure shows the same embodiment, since this is an example in which it corresponds to that of FIG. 1, the same reference numerals are used for corresponding parts. In FIG. 2, 1 to 2 are selection signals for selecting redundant memory cells 12 to I3 when a defect is found in the normal memory cells 14 to 14', and a redundancy control circuit (not shown) The redundant selection circuits 8 and 9 are provided with redundancy selection circuits 8 to 9. 5-6 are selection lines for redundancy, 7-
7' is a selection line for normal memory cells. 8-1' is a selection circuit 11 that selects normal memory cells Z4 to I('
This is the selection signal that becomes the input of ~11'. 15~15'
is a fuse element that disconnects when a defective memory cell 14 to ZJ' is found so that no signal is transmitted to the selection line even if the memory cell is selected by the selection circuit, and this is a fuse element that makes up the circuit. It is made of polycrystalline silicon, which is made in the same process as forming the gate electrode of a transistor.

In normal operation in FIG. 2, selection signals 3-3' are applied to the selection circuit tr-1r', and one of the memory cells 14-14' is selected depending on the contents of the selection signals 3-3'. At this time, selection signals I-2 are applied to selection circuits 8-9 so that memory cells 12-13 are not selected by the redundancy control circuit. If a defect is found in the memory cells 14 to 14', the fuse element connected to the selection line that selects that memory cell can be cut with a laser or the like, even if the selection signal indicates that the defect is detected. To deselect a defective memory cell by preventing a signal from being transmitted to a selection line even if the memory cell is selected. At the same time, the redundancy control circuit sends a signal corresponding to the selection signal of the defective memory cell to the selection circuits 8 to 9 as selection signals l to 2 so that one of the redundancy memory cells 12 to 1.9 is selected. give to By doing so, even if a defective memory cell is selected, it can be replaced with a redundant memory cell.

It should be noted that the present invention is not limited to the examples only, and various applications are possible. For example, in the embodiment, the fuse element is formed using polycrystalline silicon that can be formed in the same process as the gate formation, but this is not limited to this, and any gate material such as molybdenum silicide may be used, and polycrystalline silicon that is not the gate material may be used. They may be formed in the same process of forming wiring using a wiring material such as silicon, molybdenum silicide, or AA'.

〔Effect of the invention〕

As explained above, according to the present invention, a defective memory cell is deselected by cutting the fuse element connected to the selection line, so there is no need for a circuit to detect that a redundant memory cell has been selected. Moreover, since there is no need to control a normal selection circuit based on the detection signal, the selection circuit can be simplified and the speed of the circuit can be further increased.

Furthermore, since there is no signal delay caused by the redundant memory cell selection detection circuit, the problem of double selection of memory cells is eliminated, and high speed operation can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a conventional semiconductor memory circuit diagram, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 5-6...Redundancy selection lines 7-7'...Normal selection lines B-9...Redundancy selection circuits 1l-II'...Normal selection circuits 12-13...Redundancy memory cells 14-14'... Normal memory cell + + -h, -L,, --A Ameto Applicant's agent
Patent Attorney Takehiko Suzue - - - Continued from page 1 of 0 Inventor Akira Aono Toshiba Microcomputer Engineering Link Co., Ltd., 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City Applicant Toshiba Microcomputer Engineering Co., Ltd. Kawasaki 1 Komukai Toshiba-cho, Ichisaiwai-ku

Claims (3)

[Claims] (1) A normal memory cell for storing information formed on a semiconductor substrate, a normal selection circuit that selects the memory cell, and a normal selection circuit that is provided separately from the memory cell and the selection circuit to prevent defects in the memory cell. A redundant defect relief memory cell for relieving a defect when it occurs, a defect relief selection circuit for selecting the defect relief memory cell, a selection line for selecting the normal memory cell, and the normal selection. A semiconductor memory characterized by comprising a fuse element inserted between a circuit and a fuse element. (2) The semiconductor memory according to claim 1, wherein the fuse element is formed of the same material and in the same process as the gate electrode of the transistor formed on the semiconductor substrate. (3) The semiconductor memory according to claim 1, wherein the fuse element is formed of the same material and in the same process as the wiring material formed on the semiconductor substrate.