JPH04192198A - Redundant circuit - Google Patents

Abstract

PURPOSE:To allow the relieving of perfectly nondefective articles by providing a redundant line disable circuit provided with a polysilicon fuse and returning the spare line and row lines which are once substd. to an initial state. CONSTITUTION:The re signal and rao signal of the outputs of a redundant line selection circuit 8b and an address selection circuit 14a turn to an H and the circuit of a NAND circuit 15 turns to an L and a redundant line 18 is selected when the polysilicon fuse 4 of the circuit 8b is cut by irradiation with a laser beam and the polysilicon fuse 10 of the circuit 14a, etc., corresponding to a defective address is cut. The rd signal of the circuit of the redundant line disable circuit 24 turns to an H and the re signal is inverted to an L via a NOR circuit 25 and the output of the circuit 15 turns to an H when the polysilicon fuse 20 of the circuit 24 is fused in this state. The line 18 is made into a non-selection state in this way and attains the initial state before the relieving. Then, the perfectly non-defective articles are relieved even in the case of substitution with the redundant line by a fuse selection error.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention reduces the defective rate by saving a chip containing a defective memory cell due to a defect in a semiconductor memory device by using a spare memory cell prepared in advance. This invention relates to redundant circuits that reduce redundancy.

[Conventional technology]

FIG. 2 is a redundant circuit diagram in which a defective memory cell is saved as a spare memory cell by blowing out a polysilicon fuse using conventional laser trimming (hereinafter referred to as LT). Power supply Vcc, (2)
C GND, (3), (9) C Capacity, +4), QO
) are polysilicon fuses, (5), (6), (7
), QL), CI2.17) High inverter circuit, (
8a) is a redundant line selection circuit, 03 is an ex-OR circuit,
(14a) and (14b) are address selection circuits, a9 is a NAND circuit which is a redundant line decoder, 0■ is a signal for disabling the normal decoder, and αa is a redundant line.

Next, the operation will be explained. During normal operation without using redundant circuits, the polygon fuse (4) is connected to GND (
2) is grounded, so there is a “L” in the inverter circuit (5).
” level is input, the output of the inverter circuit (5) is “
It becomes "H" level and is input to the next stage inverter circuit (7).The "H" level signal is also latched by the inverter circuit (6).The output "e signal" of the inverter circuit (7) is "L" level and the NAND circuit four circuit power O
F5 always outputs "H", and the redundant line 0 is inverted by the inverter circuit αη and always becomes "L" level, so that the redundant line is in a non-selected state.

On the other hand, when using the redundant line, the redundant line selection circuit (8
a) Cut the polysilicon fuse (4) inside using LT. At the same time, the polysilicon fuses in the address selection circuits (+4a) and (14b) corresponding to the defective address are also canted by the LT as necessary. Then, since the polysilicon fuse (4) in the redundant line selection circuit (8a) is cut, an H" level signal is input to the inverter circuit (5) by the capacitor (3) connected to Vcc (1). Then, the re double signal “H”
" level, and the redundant line is selected or enabled. At this time, the address selection signal plane 8 ("4a'),
When the information of the polysilicon fuse (IQ) in (14b) and the information of the address signals a0 to a1 input from the outside become the same, the ra, signal to rat signal all output "H" level, and the NAND circuit 0'5 The output Oe becomes “L” level, disabling the regular decoder,
The signal on the redundant line ag becomes "H" and the redundant line is selected.

Figure 3 shows the manufacturing flow. LT performs wafer test 1 after completing the aluminum process of the wafer process, and determines whether or not it can be repaired.
The defective address of the repaired chip is stored as information for each chip on each wafer. Next, LT is performed based on the stored information, and polysilicon fuses are cut as necessary.

[Invention or problem to be solved]

Since the conventional redundant circuit is configured as described above, L
If a redundant line is selected by T and the fuse is cut, the original state cannot be restored.

If the wafer test l and LT devices are not operating online, the wafer test l and LT operations become completely independent operations, and if the wafer order is mixed up or there is a discrepancy between the stored information and the chip, etc. This is caused by a mistake in fuse selection. If a fuse selection mistake occurs, the defect cannot be repaired, and furthermore, a redundant line may be used for a perfectly good product that does not require a redundant circuit, and if there is a defect in the redundant line at this time, the product is either completely good or defective. The problem was that it became

This invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a redundant circuit that can restore a line replaced by a redundant line to its initial state in the event of a fuse selection error and rescue a completely non-defective product.

[Failure to solve the problem]

The redundant circuit according to the present invention is provided with a polysilicon fuse for returning spare row lines and column lines that have been replaced to their initial states.

[Effect]

By cutting the polysilicon fuse in the redundant line disable circuit, the redundant circuit according to the present invention returns the state at the time of a fuse selection error to the initial state, and is repaired as a completely non-defective product.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) to α odor are the same as in the conventional example, and their explanation will be omitted. α9 is the capacitance, 4 is the polysilicon fuse, (
21), (22), and (23) are inverter circuits, (
24) is a redundant line disable circuit, (25) is N
It is an OR circuit.

Next, the operation will be explained. During normal operation without using redundant circuits, the polysilicon fuse (4) is connected to GND (
2), the output of the inverter circuit (5) becomes "H" level, and the input NO.
The output re multiplied signal of the R circuit (25) is always at the "L" level, the output αG of the NAND circuit 09 is always at the "H" level, and the redundant line a& is always in the non-selected state.

On the other hand, when using the redundant line, the redundant line selection circuit (8
b) Cut the polysilicon fuse (4) inside using LT. At the same time, the polysilicon fuse CLO1 in the address selection circuits (14a) and (14b) corresponding to the defective address is also cut by the LT as necessary.

When the relief by LT is carried out without any problems, polysilicon fuse 4 in the redundant line disable circuit (24) remains connected, and at this time the rd signal outputs "L level" and is input to the NOR circuit (25). In addition, the polysilicon fuse (4) in the redundant line selection circuit (8b)
) is cut by LT, so Vcc (1)
An "H" level signal is input to the inverter circuit (5) by the capacitor (3) connected to the capacitor (3), and as a result, an "L" level signal is input to the NOR circuit (25).

Since the two outputs of the NOR circuit (25) both go to the "L" level, the re multiplication signal goes to the "H" level, and the selection of the redundant line becomes enabled. At this time, the information on the polysilicon fuses in the address selection signal circuits (14a) and (14b) and the address signals a0 to a input from the outside are
When the information of , becomes the same, ra0 signal ~ra.

All signals output “H” level, and NAND circuit α5
The output αG of is set to "L" level, disables the regular decoder, and selects the redundant line 0ε.

However, when a fuse selection error occurs, the polysilicon fuse (A) in the redundant line disable circuit (24) is cut by the LT. Then, an "H" level signal is input to the inverter circuit (21) due to the capacitor connected to Vcc (1). In addition, the inverter circuit (
23), the rd times signal becomes "H" level at this time. Then, the output of the NOR circuit (25) is the re multiplied signal "
The output αG of the NA4JD circuit α9 goes to the “H” level. The redundant line αe goes to the “L” level, and the redundant line returns to the non-selected state, that is, the initial state before relief.

[Effects of the Invention] As described above, according to the present invention, since the polysilicon fuses are provided to restore the spare row lines and column lines that have been replaced to their initial states, it is possible to rescue completely non-defective products in the event of a fuse selection mistake. There is.

[Brief explanation of the drawing]

FIG. 1 is a redundant circuit diagram according to an embodiment of the present invention, FIG. 2 is a conventional redundant circuit diagram, and FIG. 3 is a manufacturing flow diagram. In the figure, (4), αω, and ■ are polysilicon fuses, and ag is a redundant line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Multiple row lines and multiple column lines are arranged in a matrix,
A semiconductor memory device in which a memory transistor is connected to the intersection of both lines, and includes a polysilicon fuse that can be blown by laser light, and can be replaced with spare row lines and column lines by blowing the polysilicon fuse. 1. A redundant circuit characterized in that a polysilicon fuse is provided for returning spare row lines and column lines that have been replaced to their initial states.