JP3198546B2 - Semiconductor device having redundant memory cells - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a redundant memory cell (hereinafter referred to as a "redundant cell"), and more particularly to an improvement in a redundancy cell test circuit of a DRAM.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional redundancy cell test circuit. The input X1T is a signal that becomes 1 when the X address input to the A1 pin is 1, and becomes 0 when the X address is 0. The input X1N is a signal that the X address input to the A1 pin is 0. The signal becomes 1 when the X address is 1, and becomes 0 when the X address is 1. Input X
Similarly, 2T, X2N, X3T, X3N,..., X7T, X7N are signals that become 0 or 1 corresponding to the X addresses input to the A2 to A7 pins. Also, input X8
T and X9T are signals that become 1 when the X address input to the A8 and A9 pins are both 1, and become 0 otherwise. The input E is a signal that is 0 before the address is determined and becomes 1 before and after the address is determined.

In this example, two addresses among X addresses X0 to X7 = 256 can be separately replaced.
In addition, the adjacent WORD selected by XO due to the configuration of the memory cell
The lines are replaced by redundancy word lines in units of two. Therefore, there are four (two sets) of redundancy word lines on one plate selected by the X8 and X9 addresses.

The portions surrounded by broken lines are fuse trimming groups 1 and 2 for laser trimming, and include F1 to F14 and F21 to F21.
There are 14 fuses, each indicated by F34. Now, as a result of the test, if a certain fuse programming is performed, 7 out of 14 fuses are cut,
It becomes non-conductive.

Although the point A is set to a high state by the input E,
When an address different from the redundancy-programmed redundancy address is input, the point A is in a low state. Conversely, when the same address as the programmed address is input, point A remains high, the outputs XRDSO and XRED become 1, and the redundancy word line is selected.

Although this example is a method of selecting a redundancy word line related to an X address, the same applies to a method of selecting a redundancy digit line related to an X address.

[0007]

However, in this conventional redundancy address selection circuit, the redundancy cell is selected only after the fuse is cut by laser trimming, so that the redundancy cell to be replaced is tested for good or defective in advance. It is impossible to do. For this reason, there has been a problem that the yield may be reduced due to a defect at the replacement location, or the characteristics may be deteriorated at the replacement location.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is possible to know good and bad and characteristics of a redundancy cell before replacing a normal cell with a redundancy cell. It is an object of the present invention to provide a semiconductor device having a redundant memory cell that can prevent deterioration.

[0009]

A semiconductor device having a redundant memory cell according to the present invention has a redundant memory cell and a fuse group for selecting the redundant memory cell. And an address input pin for inputting an address to the redundant memory cell are used as input pins for a select signal for the redundant memory cell during a test, and the select signal is used to input the redundant memory cell. select use memory cells, have row tests the redundant memory cell without cutting the fuse group of fuses, after the test, address during the test
Laser trimming of input pins that are not necessary for
It characterized in that so as to be separated from the redundant memory cell by.

[0010]

In the present invention, before the fuse is cut by laser trimming, the redundant memory cell can be selected by the selecting means, and the redundancy memory cell to be replaced is tested for good and bad and its characteristics. be able to. Therefore, only when it is determined as good as a result of this test, the redundant memory cell can be used for replacement. Therefore, it is possible to prevent a reduction in yield and a deterioration in characteristics due to replacement.

[0011]

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. This example is for a DRAM having a function of switching between a 4 Mbit × 1 configuration and a 1 Mbit × 4 configuration by a bonding option. Normally, in the case of DRAM, a screening test is first performed in the wafer state, and good products and defective products are separated.
A chip that becomes a 4M bit × 1 component due to the bonding option can be tested as a 1M bit × 4 component.

In the figure, X10T is a signal which becomes 0 when the X address inputted to the A10 pin is 1, and becomes 1 when the X address is 0. Further, fuses F15, F16,
F35 and F36 are provided to deactivate the present test circuit, and the transistors 3 and 4 are N-channel transistors having sufficiently small abilities.

Next, the operation of this embodiment will be described.
As mentioned above, 4Mbit x 1 component is also 1Mbit x
Can be tested as four components. Now all chips are 1M
When tested as a bit × 4 component, the A10 pin is not required. That is, the A10 pin has no relation to the address selection. Therefore, the A10 pin is used for selecting a redundancy cell. Since the points B and D are always low before fuse cut, XRDSO, XRDS
1, XRED is determined by the input values of X7T, X7N, X10T. When the inputs X7N and X10T are both 1, the point C is 1. Here, since the capability of the transistor 3 is sufficiently small, the potential at the point C is not easily extracted. As the point C becomes 1, XRDS0, XRE
D becomes 1 in each case, and the redundancy word line is selected. Similarly, when X7T and X10T are both 1, XRDS1 and XRED are both 1, and another set of redundancy word lines is selected.

After the test is completed, fuses F1 to F14, F
In the step of cutting 21 to F34, the fuses F15, F16, F35, and F36 are cut at the same time. As a result, the test circuit becomes inactive, and the A10 pin can be used in the same manner as in the related art. At this time, the transistor 3 and the transistor 4 are provided in order to prevent floating at points C and E. As a measure to reduce the current, NAN separated by fuse cut
It is preferable to cut off the power supply in the D inverter by fuse cutting.

Although the present embodiment relates to an X address for selecting a redundancy word line, it goes without saying that a redundancy digit line can be selected if the same is applied to a Y address.

[0017]

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The input MOR is a test mode activation signal which becomes 1 at the timing shown in FIG. That is, a high voltage of a certain voltage or more is applied to a specific address pin,
At the timing of FIG. 3 called BR, the redundancy cell test mode is set.

Next, the operation of the embodiment shown in FIG. 2 will be described. In test mode, input MOR is 1, so
The two transfer gates 5 and 6 in the figure are turned off. Therefore, the output XRDSO is determined by the input X7N. X
If 7N is 0, XRDS0 and XRED both become 1, and the redundancy word line is selected.

When X7T, which is the opposite phase of X7N, becomes 0, XRDS1 and XRED become 1.

Since MOR is 0 during normal use, it can be used in the same manner as in the prior art.

In this example, there is an effect that the test circuit can be made inactive without being cut off by a fuse cut, and the test can be performed in a subsequent process.

[0023]

As described above, according to the present invention, the redundancy cell can be selected without cutting the fuse for selecting the redundancy cell. Therefore, before replacing the normal cell with the redundancy cell, the redundancy cell can be selected in advance. It is possible to know good and bad and characteristics, and it is possible to prevent a reduction in yield and deterioration in characteristics due to replacement.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a redundant cell of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a redundant cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a timing to enter a test mode in a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a redundant cell of a conventional semiconductor device.

[Explanation of symbols]

1, 2; fuse group 3, 4; N-channel type transistor having sufficiently small capacity F1 to F16, F21 to F36; fuse for laser trimming

Claims (1)

(57) [Claims] An input pin having a redundant memory cell and a fuse group for selecting the redundant memory cell, which is unnecessary for selecting an address in a test; An address input pin to be input is used as an input pin of a selection signal for the redundant memory cell at the time of a test, and the redundant memory cell is selected by the selection signal without cutting the fuse of the fuse group. There line test of the redundant memory cell,
After the test, no need to select addresses during the test
Input pins are redundant by laser trimming.
A semiconductor device having a redundant memory cell, which is separated from a redundant memory cell.