JPS60182818A - Cmos logic circuit - Google Patents

Abstract

PURPOSE:To attain the reduction of power consumption depending on the processed amount by discriminating the quantity of processing to be operated for the circuit and changing the common processing clock frequency accordingly. CONSTITUTION:Every time a content to be processed by a program is lost in a circuit comprising a CPU1 of CMOS type, an oscillator 2 oscillating a clock at a frequency of plural steps, a counter 3 controlling the frequency and a clock oscillator 4 of a prescribed frequency, a pulse counting down the counter 3 is outputted. The counter 3 is counted up by the clock oscillator 4 in addition to the count-down control from the CPU1. The counter 3 is controlled so as to increase the processing clock frequency of the oscillator 2 as the counter value is higher. Thus, when the CPU1 has much pocessing amount, the output frequency of the count-down pulse is decreased, the processing clock frequency is increased and vice versa.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMO8 logic circuit, and more particularly to a CMO8 logic circuit that can reduce power consumption in accordance with the amount of processing.

(Prior art) Conventionally, in this type of eMO8 logic circuit, a dedicated circuit was installed to monitor the presence or absence of processing, and when there was no processing, the processing clock of the CMO8 logic circuit was stopped or the power supply was stopped. In addition to requiring a dedicated circuit to monitor the presence or absence, there is a drawback that if even a small amount of processing is performed, there is no reduction effect.

(Object of the invention) The object of the invention is to determine the amount of processing that one circuit should perform,
The object of the present invention is to provide a CMO8 logic circuit which eliminates the above drawback by changing the frequency of a common processing clock accordingly, and which makes it possible to reduce power consumption in accordance with the amount of processing.

(Structure of the Invention) The CMO8 logic circuit of the present invention includes a CPU that executes various processes in accordance with a processing clock, a first oscillator that outputs a clock of a constant frequency, and a first oscillator that counts down when the CPU is in an idle state. The present invention is characterized in that it includes a clock that counts up and down with the output of the first oscillator, and a second oscillator that outputs the processing clock whose frequency increases as the count value of the counter increases.

(51! Examples) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a CMOS type CPU, 2 is an oscillator that can oscillate a clock at multiple step frequencies, 3 is a counter that controls the frequency, and 4 is a constant frequency It is a clock oscillator.

FIG. 2 is a schematic flow of a program that controls the CPUI.

In FIG. 2, the program outputs one pulse that causes the counter 3 in FIG. 1 to count down each time there are no more factors to process, that is, the program enters an idle state. In addition to the countdown control from the CPU 1, the counter 3 receives a constant frequency clock from the clock oscillator 4 to perform clocking/up-up of the counter 3. The output of counter 3 is as follows:
The oscillator 2 is controlled to increase the frequency of the processing clock of the oscillator 2. By adopting this configuration, C)
When the amount of processing is large for the PUI, the output frequency of countdown pulses decreases and the frequency of the processing clock increases.

Conversely, when the amount of processing is small, the frequency of the processing clock becomes low because the countdown pulse is output sufficiently faster than the oscillation period of the second oscillator 4.

Therefore, the operating speed of the CPU is controlled according to the amount of processing, and the effect of reducing the power consumption of the CPU when the amount of processing is small is awaited.

(Effects of the Invention) As explained above, the present invention applies to a CMO8 logic circuit that operates using a common processing clock.

This has the effect of changing the frequency of processing cry according to the amount of processing that the circuit should operate, lowering the operating speed when the amount of processing is small, and reducing the power consumption of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart showing a general flow of a program for controlling the CPU in FIG. 1... CPU, 2... Oscillator, 3...
····counter. 4...Clock oscillator. ￥-1＠ Fall 2＠

Claims (1)

[Claims] a CPU that executes various processes according to a processing clock; a first oscillator that outputs a clock of a constant frequency;
a counter that counts down when the PU is in an idle state and counts up with the output of the first oscillator;
and a second oscillator that outputs the processing clock whose frequency increases as the count value of its own counter increases.