JPS60180162U

JPS60180162U - data transmission equipment

Info

Publication number: JPS60180162U
Application number: JP6646784U
Authority: JP
Inventors: 茂斉藤
Original assignee: カルソニックカンセイ株式会社
Priority date: 1984-05-09
Filing date: 1984-05-09
Publication date: 1985-11-29

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のＭ系列多重伝送装置の概略構成を示すブ
ロック回路図、第２図はこの考案が対象としている伝送
系が取扱う信号のタイムチャートで、第３図はこの考案
の実施例に係るデータ伝送装置受信機のブロック回路図
、第４図は第３図における多数決判定回路２５の具体回
路図である。図において、１０・・・・・・送信機、２０〜４０・・
・・・・受信機、２１および２４・・・・・・シフトレ
ジスタ、２２・・・・・・指定判定回路となるアドレス
デコーダ、２５・・・・・・多数決判定回路、Ｓ□・・
・・・・アドレス信号、Ｓ２・・・・・・シフトクロッ
ク信号、Ｓ３・・・・・・データ信号である。Fig. 1 is a block circuit diagram showing a schematic configuration of a conventional M-sequence multiplex transmission device, Fig. 2 is a time chart of signals handled by the transmission system targeted by this invention, and Fig. 3 is an example of an embodiment of this invention. FIG. 4, a block circuit diagram of such a data transmission device receiver, is a specific circuit diagram of the majority decision circuit 25 in FIG. 3. In the figure, 10... transmitter, 20-40...
...Receiver, 21 and 24...Shift register, 22...Address decoder serving as a designation judgment circuit, 25...Majority decision circuit, S□...
. . . address signal, S2 . . . shift clock signal, S3 . . . data signal.

Claims

[Scope of utility model registration request]

A plurality of receivers 20.30.40. . . . and the plurality of receivers 20, 30, 40 . An address signal S□ that individually specifies ...... is sent to each receiver 20, 30゜4
0, . . . and the receiver 20.30°40 specified by the address signal S1.
, . . . , a transmitter 10 that repeatedly outputs a data signal to be transmitted to
0. . . . is a register 21 that temporarily stores the -address signal S0 from the transmitter 10, and the own device decodes the contents of the address signal S□ stored in the register 21. A designation determination circuit 22 determines whether or not the aircraft has been designated; and each time the designation determination circuit 22 determines that the own aircraft has been designated, the data signal S3 from the transmitter 10 is chronologically transmitted. 1. A data transmission device comprising: an odd-numbered shift register 24 that sequentially stores data in a shift register 24; and a majority decision circuit 25 that selects a majority logic value from a group of outputs of the shift register 24.