JPS61104657U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of this invention. FIG. 2 is a diagram showing the operation timing of an embodiment of this invention, FIG. 3 is a diagram showing an example of a conventional data receiving device, and FIG. 4 is a diagram showing the operation timing of an example of a conventional data receiving device. In the figure, 1 is a data transmitting device, 2 is a receiver, 3 is a data holding unit, 4 is a data receiving device, and 5 is a data receiving device.
1 is a timing generation section, 6 is a latch 1, 7 is a latch 2, 8 is a latch 3, and 9 is a majority logic circuit.
Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] Receives data signals and write signals output from a data transmitter that generates various data signals with meanings such as numerical values, symbols, codes, and characters, and write signals output in synchronization with these data signals. In a data receiving device comprising a receiver that shapes a signal waveform, a data holding section that holds the data signal shaped by the receiver in synchronization with a write signal, and the receiver and the data holding section, a plurality of latch groups that temporarily hold data signals; a timing generation unit that generates latch signals to the latch groups based on the write signal; A majority logic circuit that selects the most obtained one is provided, so that even if sporadic noise is superimposed on the data signal sent from the data transmitting device, a correct data signal can be obtained at the data receiving device. data receiving device.