JPS6017271B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention stores the channel signal of the channel to be selected in a station memory, reads out the channel signal by specifying the address of this station memory at the time of channel selection, and reads the read channel signal. Regarding a channel selection device that selects a channel according to the
The present invention aims to provide a device that facilitates channel selection during channel selection by displaying a list of which channels are stored at which addresses in a station memory.

There are two ways for a viewer to specify the channel to be selected on a television receiver, etc., by directly inputting a 1- to 2-digit channel number from a numeric keypad keyboard, and by storing the channel to be selected in advance in some kind of memory. When selecting a channel, there is a method in which the channel number is read from the memory by specifying the address of the memory and the channel is selected.

The former method allows you to input channel numbers directly from the keyboard when selecting a channel, but the operation is cumbersome, while the latter method allows easy operation when selecting a channel, but it is difficult to input which channel is assigned to any address in memory. There is a problem that you cannot make a selection unless you know whether it will be remembered or not. Therefore, the present invention aims to make it easier to understand which channel is stored at which address in the memory when selecting a channel in a channel selection device using the latter method. This feature is characterized by providing a list display of the channels stored at each address to facilitate channel selection.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings showing an embodiment implemented in a synthesizer type channel selection device.

First, FIG. 1 shows its configuration.

In the figure, 1 is an RF amplifier circuit, 2 is a mixing circuit, and 3 is a V
IF circuit, 4 is a video detection circuit, 5 is a video circuit, 6 is a deflection circuit, and 7 is a cathode ray tube, which are similar to those in a normal color television receiver.

Further, 8 is a voltage-controlled local oscillation circuit that creates a local oscillation signal to be applied to the mixing circuit 2, 9 is a prescaler that pre-converts the oscillation output, 10' is a programmable frequency division foundation, 11 is a reference oscillation circuit, and 12 is a A phase comparison circuit 13 compares the phases of the frequency division output and the reference oscillation output, and 13 is a low-pass filter circuit that converts the phase comparison output into a low frequency filter and applies it to the local oscillation circuit 8 as an oscillation frequency control voltage. It constitutes a lock loop (PLL) circuit. The programmable frequency dividing circuit 10 includes a code conversion circuit 1 as described later.
4, a frequency division ratio program signal is added so that the frequency division ratio corresponds to the channel to be selected, and the frequency division ratio changes according to the channel. Then, the PLL circuit operates so that the frequency of the divided output and the reference oscillation signal from the reference oscillation circuit 11 match, and the local oscillation circuit 8 is controlled to generate a local oscillation that is passed to the channel to be selected. A signal is applied from the local oscillator circuit 8 to the mixing circuit 2, and that channel will be tuned. Next, a description will be given of the part that applies the signal for channel selection to the PLL circuit.

Reference numeral 15 indicates a station memory for storing the corresponding channel signal in the memory location of each address; 16 indicates a station selection circuit for selecting and specifying the address from which the channel signal is to be read when selecting a station; and 17 indicates the selected address. 18 is a channel input circuit such as a numeric keypad for inputting a channel number to be stored in the station memory 15; 19 is a channel display circuit such as a 2-digit 7-segment number display element for displaying the channel number; It is.

- The station memory 15 has, for example, 16 addresses for 16 stations, and is composed of a RAM or PROM having a storage capacity of 8 bits per address, and 4 bits in each address contain a signal of the channel number rising to 1. However, in the remaining 4 bits, the 1st signal is BCD
Memorized as a signal. The write address and read address are specified by the station selection circuit 16, which converts the output of a single-stitch multiple press/down switch into a 4-bit binary signal for address specification. It consists of an encoder. Further, the station display circuit 17 is constituted by a single indicator light that is integrated with each switch of the station selection circuit 16 or arranged in parallel with each switch, and indicates which station is selected. . On the other hand, the channel input circuit 18 is comprised of a ten-key keyboard for inputting channel numbers and an encoder that generates IM and first BCD signals in accordance with the one- to two-digit channel number input from the keyboard. The channel number input from the channel input circuit 18 is written as a BCD signal to the address designated at that time in the station memory 15. Further, the channel number input from the channel input circuit 18 or the channel number read from the station memory 16 is displayed as it is in the channel display circuit 19 on a numerical display element such as a two-digit 7-segment liquid crystal display element. . This channel display circuit 19 may be omitted. Then, the channel signal read from the station memory 15 is applied to the code conversion circuit 14, where a 9-bit signal is input to set the division ratio in the programmable frequency division circuit 10 necessary for selecting that channel. Programmable frequency divider circuit 1 converted into frequency division ratio signal
A divider ratio of 4 is added to the program input.

Therefore, by sequentially specifying the addresses of the station memory 15 in the station selection circuit 16 in advance, and inputting and writing the channel number to be selected from the channel input circuit 18 for each address, the station memory 16 is written. Each address and each channel signal can be stored in correspondence.

Then, when performing channel selection thereafter, simply specifying the read address of the station memory 16 from the station selection circuit 16 reads out the channel signal at that address, and controls the programmable frequency divider circuit 10 via the code conversion circuit 14. You can select the desired channel. Next, the part that displays a list of the stored contents of the station memory 16, which is a feature of this device, will be explained.

First, 20 is station memory 1 for its display.
a channel memory for storing address signals of 6 and channel signals stored in each address;
1 is a code conversion circuit that converts the address signal to be stored and the 2-digit BCD channel signal into a 6-bit binary signal (ASCI signal) and inputs the signal to the channel memory 20; 22 and 23 are code conversion circuits that convert the input timing; The controlling switching circuit 24 is a 5-bit switch for displaying address number characters 34 and channel number characters 35 as shown in FIG. 2 in accordance with the address signal and channel signal read from the channel memory 23 during display. A character generator 25 that generates parallel video signals is a P-S conversion circuit that converts the parallel video signals into serial video signals. Furthermore, 26 is a broadcast memory for storing whether or not a broadcast signal exists for each channel stored in the station memory 15, and 27 and 28 are for storing each address number or channel number depending on the presence or absence of the broadcast signal. This is a switching circuit for switching the display color of display characters. The output signal of the switching circuit 27 is applied to all the R, G, and B circuits of the video circuit 5 to display the address number and channel number of the channel where the broadcast signal exists in white, and the output signal of the switching circuit 28 is applied to each of the R, G, and B circuits of the video circuit 5. The voltage is applied only to the R circuit of circuit 5 so that the address number and channel number of the channel where no broadcast signal is generated are displayed in red. Reference numeral 29 is a memory control circuit for controlling the operations of these memories 20, 26, etc., a clock oscillation circuit, and 31 is a switch for switching between television image display and channel list display.

Here, if the channel memory 2 rivers are displayed as shown in Figure 2, a total of 72 characters (16 characters and 12 characters) x 4 lines will be displayed.
It has a character-length address, and the characters 32 of "ST" representing the address number of the station memory and the characters 33 of "CH" representing the channel number are written in advance. Then, when writing the channel signal to the station memory 15, the station selection circuit 1
The address of the channel memory 20 is also designated by the address designation signal from 6 at the same time, and that address signal at that time is converted by the code conversion circuit 21 and written to that address of the channel memory 20.
The channel signal inputted from the channel input circuit 18 and written to the station memory 15 is also converted by the code conversion circuit 21 and also stored in the channel memory 20. At this time, 4 addresses of the channel memory 20 are allocated per address of the station memory 15 so that the 1q position and 1st position of the address signal and the 1q position and 1st position of the channel number are respectively stored in separate addresses.
Address control is performed by the memory control circuit 29 so that addresses are assigned one by one, and data is written in a time-sharing manner. At the same time, the broadcast memory 26 is addressed as well, and it is detected at the input of that channel whether a broadcast signal has been received in the television receiver circuit and, for example, by whether a vertical synchronization signal has been received in the deflection circuit 6. detected, “1” is placed at that address in the broadcast memory 26.
(broadcast presence) is stored as "0" (broadcast non-existence).
Such channel memory 20 and broadcast memory 26
Address signals, channel signals, and broadcast detection signals are written to the station memory 15 each time a channel signal is written to the station memory 15, and for all channels stored in the station memory 15, corresponding display address signals and channels are written. The signal and broadcast detection signal are stored in the channel memory 20 and the broadcast memory 26.
will be remembered. Next, when displaying a list, an address designation signal and a clock signal are generated from the memory control circuit 29 in synchronization with both the horizontal and vertical deflections of the color cathode ray tube 7. "CH" signals, address signals, and channel signals are read out in the order they are displayed and applied to the character generator 24 as column signals and data signals.

Thereby, the character generator 24 generates a video signal for display, which is converted into a serial signal by the P-S conversion circuit 25 and applied to the video circuit 5, so that it is displayed on the color cathode ray tube 7 as shown in FIG. A list like this will be displayed. Therefore, the viewer must press the switch 31 before selecting a channel.
By switching to the list display side, a list of the addresses of the station memory 15 and the channel numbers recorded in each can be displayed as shown in Figure 2, and the desired channel can be selected by looking at this. By being able to immediately know the operating position of the station selection circuit 16 for selecting a station, operability at the time of selecting a station is extremely improved. At this time, in synchronization with reading out the address signal and channel signal from the channel memory 20, the broadcast memory 26 is also addressed, and a stored signal indicating whether or not a broadcast signal exists in the channel of each address is read out. When a broadcast signal exists, the switching circuit 27 is opened and display signals are applied to each R, G, and B circuit, so that the address number and channel number are displayed in white, and conversely, when a broadcast signal is not present. Sometimes the switching circuit 28 is opened and the display signal is applied only to the R circuit, so that its address number and channel number are displayed in red.

Therefore, for viewing, it is convenient that by looking at the display color and specifying the address of the channel on which the white-displayed broadcast signal is present using the station selection circuit 16, the channel on which the broadcast signal is broadcast can be immediately selected. In the above embodiment, the address signal and the channel signal are code-converted and written to the channel memory, but the address signal is fixedly stored in the ROM etc., and only the channel number is written in the RAM etc. You can.

Alternatively, instead of providing a separate broadcast memory, an extra bit of storage capacity may be provided in the channel memory for dual use. As detailed above, in the present invention, in a channel selection device using a station memory that presets and stores channel signals, the channels stored at each address of the station memory are displayed on the cathode ray tube at that address. Since the corresponding list is displayed, the viewer can easily and immediately know which address the desired channel is preset to by displaying the list display as necessary when selecting a channel. This makes it possible to obtain a device with good operability during channel selection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a channel selection device according to an embodiment of the present invention, and FIG. 2 is a front view showing a display mode of the device. 2...Mixing circuit, 5...Video circuit, 7
...Color cathode ray tube, 8...Local oscillation circuit, 9...Prescaler, 10...
Programmable frequency divider circuit, 11... Reference oscillation circuit, 12... Phase comparison circuit, 13...
Low-pass filter circuit, 14... Code conversion circuit, 15...
Station memory, 16... Station selection circuit, 17... Station display circuit, 18...
・Channel input circuit, 19...Channel display circuit, 20...Channel memory, 21...
... code conversion circuit, 22, 23 ... switching circuit, 24 ... character generator, 25
...P-S conversion circuit, 26...Broadcast memory, 2
7, 28...Switching circuit. Figure 2 Figure 1

Claims (1)

[Scope of Claims] 1. A station memory that stores channel signals of a plurality of channels to be selected in storage devices each having a plurality of addresses, and selects an address to be read from the station memory to select a channel to be selected. A station selection circuit, a tuning circuit that selects a channel of the channel signal in response to a channel signal read from the station memory, and a channel selection circuit that reads out all channel signals stored for each address of the station memory. A channel selection device characterized by comprising a display circuit that displays a list of all the addresses and channels on a display element in a form that corresponds to each other. 2. The channel selection device according to claim 1, characterized in that among the channels stored in the station memory, the channel in which a broadcast signal exists is displayed in a different color from the display of other channels. .