KR830000730B1 - Television receiver tuning device - Google Patents

Abstract

A receiver is tuned by a memory system which stores programming information to tune to different channels in sequence. Poor reception on a channel causes next choice to be selected. A receiver tuning system comprises a tuning element which responds to a voltage to alter tuning. A binary signal generator generates signals which represent tuning voltages which are then stored in a memory. A selector produced binary signals representing preferred and non preferred conditions which are stored in a second memory. Both memories are addressed by switching to select mode of operation and tuning sequence.

Description

TV receiver tuning device

1 is an embodiment of the present invention having an arrangement of a Nurum button operating in association with a memory device for accumulating tuning information and an order detector for detecting an operation sequence of a Nurum button for controlling the programming and operation of the tuning device according to the present invention. Block diagram of the tuning device accordingly.

2 is a logic diagram of the sequence detector configuration of the apparatus of FIG. 1 constructed in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuning apparatus for a television receiver and to an apparatus including a memory for storing tuning information.

Background Art A tuning device for a television receiver having a memory for storing binary information representing tuning information is already known.

In general, such an apparatus includes a tuning voltage memory having a plurality of storage positions for accumulating a binary signal representing a tuning voltage corresponding to various channels selectable by a viewer, and two stored in the tuning voltage memory. A digital-analog converter for converting a true signal into a tuning voltage for controlling a voltage-tuned tuning element such as a varactor diode, and an address of a storage location of the tuning voltage memory. Thereafter, the viewer has a channel selection circuit for extracting the binary signal accumulated in the tuning voltage memory when the viewer presses the "up" push button "down" push button to select a channel. Such tuning devices also allow viewers to accumulate binary information for each of the channels indicating whether or not the channel is the desired channel, so that the viewer can choose which of the " up " or " down " It has a skip channel memory having a plurality of storage positions that are addressed when pressing. For example, if the channel is not the desired channel due to reception characteristics or program contents, the channel is automatically skipped by the tuning device.

Since the tuning beams accumulated in the memory can be specially programmed to suit specific tuning conditions at the user's residential location, a tuning device with a memory is advantageous over other types of tuning devices. Since the manufacturer cannot know in advance the tuning conditions at the location of each user, it is often necessary for the user to perform any programming. Since most users are not familiar with the programming of electronic instruments, it is desirable that the programming device be relatively easy to operate. Furthermore, it is desirable to be able to operate the programming device for television tuners provided with the memory for tuning voltage accumulation, in such a manner as to be operated at least by the usual rotary tuning knob. Finally, the programming device may be as few programming means as possible, such as push buttons, switches and light emitting means for displays, and it is also desirable that these programming means be relatively inexpensive.

According to an embodiment of the present invention, a tuning device for tuning a water receiver to several tuning positions generates a voltage variable tuning device and a binary signal indicating a tuning voltage corresponding to the tuning position for controlling the voltage variable tuning device. A tuned voltage circuit for accumulating and storing it, a second type binary signal for specifying a tuning position that should not be skipped, and a second type generating binary signal for specifying a tuning position to be skipped. The tuning circuit and the skip tuning position in response to the position circuit and the selection direction signal generated when the viewer operates the selection direction switch such as the "up" push button switch and the "down" push button switch. A tuning position selection circuit for extracting the binary signal accumulated in the circuit is included. In addition, a preferred mode switch and a sequence detection circuit of a push button switch type for generating a mode signal in accordance with the operation are provided so that a signal for controlling the programming of the tuning device in response to the mode and the sequence in which the mode switch and the selection method switch are operated is provided. Occurs. Preferably, the order detection circuit includes first and second order detectors. The first sequence detector generates a tuned voltage programming signal in response to the generation of the selection direction signal before it is terminated after the mode signal has occurred. The tuning voltage circuit operates in response to the moving tuning voltage programming signal to generate a binary signal representative of the tuning voltage. The second sequence detector responds to the first synchronizing position signal in response to a series of generation and termination of the scanning direction signal followed by a series of generation and termination of the mode signal subsequent to the second series of generation and termination of the mode signal. And the second sequence detector generates a second tuning position signal in response to a first series of generation and termination of the mode signal followed by the generation and termination of a second end of the mode signal. In response to the first tuning position signal, the tuning position skipping circuit generates a binary signal of the first form. In response to the second tuning position signal, the tuning position skipping circuit generates a binary signal of the second form.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, the radio frequency signal is received by the antenna 12 and supplied to the radio frequency processing circuit 14. In this radio frequency processing circuit 14, the radio frequency signal is filtered, amplified and processed. The processed radio frequency signal is supplied to the mixer 16 and mixed with the local oscillation signal generated by the local oscillator 18 to generate an intermediate frequency signal. The frequency of the local oscillation signal is controlled in response to the tuning voltage generated by the tuning device 20 in relation to the channel selected by the viewer. Accordingly, when the intermediate frequency signal is mixed with the radio frequency signal, the radio frequency signal is modulated at a predetermined frequency. Image color and audio carrier.

The intermediate frequency signal is supplied to the intermediate frequency processing circuit 22 where it is filtered, amplified and processed. Part of the intermediate frequency signal is supplied to an AFT discriminator 24, which is a nominal value of the image carrier frequency (e.g., in the United States) caused by aging changes in each part or by ambient operating conditions. Generates an AFT signal indicating a deviation of 45.75 MHz. The automatic fine tuning voltage is supplied to the local oscillator 18 to correct the tuning voltage so that the deviation between the image carrier frequency and its nominal value is reduced. The output of the intermediate frequency processing circuit 22 is supplied to a signal processing circuit 26 for processing each component of the intermediate frequency signal, whereby a visual image is generated by the video tube 28, and audio is reproduced by the speaker 30.

The tuning device 20 is a memory type tuning device capable of storing tuning information necessary for tuning fewer desired channels than the number of channels allocated to the television band. For example, in the United States, the Federal Communications Commission (FCC) assigns 82 channels (channels 2 to 83) to television bands, while tuning device 20 is programmed to tune to only 16 channels that the viewer desires. This depends on the program content of the channel or the relative reception characteristics of each channel in the viewer's residence. The tuning device 20 is almost identical to that described in US Patent Application No. 828,848 filed on August 29, 1977, which is different from the tuning device 20 described later for control of its normal operation and programming. A device constructed according to the invention as described above is installed.

The tuning device 20 has a tuning voltage memory 112 having 16 memory locations for accumulating binary signals representing tuning voltages for each of the 16 channels desired by the viewer.

The address register 114 is an up / down counter such as, for example, a CD 4029 integrated circuit from RCA Corporation, which is installed for a binary signal supplied to a “jam” input. This address register 114 is coupled to the tuning voltage memory 112, and generates a binary signal representing decimal to 15 to address 16 positions of the tuning voltage memory 112. If the storage location of the tuning voltage memory 112 is behind an address, the binary signal accumulated at the addressed location is read from the tuning voltage memory 112, and converting this binary signal into a corresponding direct current (DC) tuning voltage for the local oscillator 18. Digital analog converter 116 is coupled.

Coupled to the up / down memory 112 and responding to control by the viewer, the tuning device 20 generates binary signals accumulated at respective memory locations of the tuning voltage memory 112 while operating in tuning voltage programming, mode. The selected signal of the binary signal generated by the tuning voltage register 118 during the tuning voltage program mode period is supplied to the display 120 for use in numerical display of a channel normally selected by the viewer. As a result, a number related to the tuning voltage is displayed, and the viewer can confirm that the desired channel corresponds to the obtained image.

The channel number represented by two decimal digits, that is, the binary signal indicating the channel number between channels 02 and 03 in the United States, is a channel number consisting of two cascaded up / down counters of the CD 4029 type of RCA Corporation. It is generated by the register 122 and supplied to the display device 120. In order to reduce the circuits used in the display 120, the binary signal indicating the ten unit position of the channel number and the binary signal indicating the one unit position are displayed by the display multiplexer (MUX) 129. The unit display unit 130A and unit 10 display unit 130B are supplied by multiplexing and successively processing. The unit display unit 130A and unit 130A are provided with seven (7) segment display units of a light emitting diode or a liquid crystal type, respectively. It becomes

The binary signal generated by the channel number register 122 is supplied with 132 degrees to the skip memory to address it. The skip memory 132 has a storage device for each of the dry channel numbers assigned to the television band. Therefore, the addresses of 82 storage positions of the skip memory 132 correspond to 82 channel numbers of 02 to 83. Each memory device in skip memory 132 is not a desired channel and must be skipped during channel selection (when skipped, a logical state "1" is also used and the corresponding channel is a desired channel and will not be skipped during channel selection. Has a memory cell for accumulating a logic state of “0.” The skip detector 134 generates a " skip " signal in response to the presence of a logic " 1 " Binary signals " 1 " and " 0 " representing skip information of the channel are supplied to the skip memory 132 in response to the control of the viewer during the channel program mode period.

The binary signal generated by the channel number register 122 is also supplied to the band selector 136. The band selector 136 is preferably a read-only memory (ROM) which determines, for example, the frequency band channel number in which the selected channel exists and generates a band selection signal in response thereto. Thus, for example, in the United States, the band selector 136 generates a band select signal on channels 2 through 6, 7, 8, 9, 13, and 14 through 83, respectively. The band select signal is supplied to the local oscillator 18 to determine the frequency range in which the oscillator oscillates. The local oscillator 18 has an array of varactor diodes switched to an oscillator configuration corresponding to each band select signal for determining the frequency range in which the local oscillator 18 oscillates. The specific frequency at which local oscillator 18 oscillates is determined by the magnitude of the tuning voltage.

After initiating the NORMAL mode and programming mode of operation of the tuning device 20 as described above, the control signal for controlling the operation during their mode period is then sent to the mode push button switch 214 of the viewer. &Quot; UP " push button switch 216, " DOWN " Pressing the push button 214, 216, 218 generates a first binary signal, e.g., logic "1"; when released, it automatically returns to the unpressed state and generates a second binary signal, e.g., logic "0". It is desirable to be in a form that can be used. This Nurum button switch is used as shown in US Patent No. 4040791.

Sequence detector 212 generates a " NORMAL " signal for bringing the tuner 20 into its normal operation mode while the viewer selects a channel for viewing the program normally, and while the viewer programs skip memory 132. Generates a "CHANEL" signal to put the device into the channel program mode, and while the viewer is programming the tuned voltage memory 112, a "TUNE" signal to put the tuner 20 into the tuned voltage programming mode. Occurs. During normal mode, the binary contents of the channel number register 122 change in response to the operation of the " UP " push button 216 and the " DOWN " push button 218, and select a channel for viewing the program normally. . "Mode" push button 214 during channel programming mode Sequence detector 212 supplies logic "1" to skip memory 132 in the order in which the "UP" push button and the "DOWN" push button are operated. Generates an "ERASE" signal to specify (by connecting + V of a constant voltage source) to specify an unwanted channel to skip during channel selection in normal mode, or to logic "0" in skip memory 132 Generates a " STORE " signal to supply (by connecting to the signal ground point) to specify the desired channel that will not be skipped during channel selection in normal mode. During the tuning voltage programming mode, the binary contents of the tuning voltage register 112 change in response to the operation of the "UP" push button 216 and the "DOWN" button 218 to adjust the magnitude of the tuning voltage for each of the desired channels. Adjust

The "NORMAL", CHANNEL, and "TUNE" signals are supplied to the display multiplexer (MUX) 129 and are one unit (UNITS) as described in the foregoing specification of US Patent Application No. 828,848. A sign indicating each mode is indicated by the display device 30A and the ten unit display device 130B. In brief, in normal mode, which responds to a "NORMAL" signal, the binary signal generated by the channel number register 122 is processed by the display multiplexer 129, and two decimal numbers representing the selected channel number are displayed. .

In the channel programming mode in response to the " CHANNEL " signal, a binary signal of the encoded form indicating the letter " C " (given by the device 152 indicating the proper connection of + V or ground), the letter " H " The binary signal of encoding format (given by the device 154 indicating + V or proper connection of ground) is synthesized, and the binary signal generated by the channel number register 122 is generated by the display multiplexer 129. In order to display the channel program mode, the symbol " CH " and the currently selected channel number are alternately displayed. In the tuning voltage program mode, a binary signal of the encoding format representing the letter "A" given by the device 148 in response to the "TUNE" signal, of the encoding format representing the letter "J" given by the device 156 The logic level signal, the binary signal indicating the sign "_" given by the device 150, and the binary signal generated by the channel number register 122 are processed by the display multiplexer 129 where the signs "AJ" and "-n", where n is an approximation of a decimal number of instantaneous tuning voltages) alternately to indicate a tuning voltage programming mode or an adjustment mode.

In addition to the sequence detector 212 and the Nurum buttons 214, 216, 218, the control section of the tuning device 20 has a PUP (POWER UP) detector 142 coupled to the power supply circuit (not shown) of the receiver, when the receiver is switched on. Generates a "PUP" signal. This "power-up" signal is supplied to the sequence detector 212 and the respective parts of the tuning device 20 to control their operation. In addition, the control section of the tuning device 20 is connected to each of the cross-coupled NAND gates 222 and 224 NAND gates 222,224. It includes a set-reset (SR) flip-flop 220 consisting of two inverters 226,228 coupled to the output, and an OR gate 230 coupled to the input of the NAND gate 224.

Generated when the "DOWN" push button is pressed and responds to the push button "Down" status indication signal (PBDN) supplied to one input of the NAND gate 222 to "DOWN" at the output of the inverter 226. Signal is generated. Pressing the "UP" push button 216 Presses the push button "Phase" status display signal (PBUP) signal "PUP" signal or "ERASE" signal in response to OR Gate 230 generates an output (OUP) in a "phase" state to generate a "phase (UP)" signal at the output of inverter 228. The "UP" and "DN" signals are supplied to the address register 114 tuning voltage register 118 and the channel number register 122 to control the direction in which they count.

Next, the operation will be described. Assume that the tuning device is programmed as described later. In response to the generation of a "power up" signal, a binary signal representing the lowest channel number, e.g., channel 02 in the United States, is supplied to the "jam" input J of the channel number register 122 in device 123 and number 15 A binary signal representing is supplied to the J input of the address register 114 from the device 15, the sequence detector 212 resets the tuning device 20 to the normal mode, and a "UP" signal is generated by the RS flip-flop 222. To be the incremental countable state.

In this regard, the contents of the storage position of the skip memory 132 corresponding to the channel number 02 are checked by the skip detector 134. If logic " 1 " detects channel 2 is not a desired channel and a skip signal is generated indicating that it is to be skipped. If logic " 0 " is detected, a skip occurs indicating that channel 2 is the desired channel and will not be skipped.

Equivalent to the skip signal, a clock signal is supplied from the AND gate 231 and the OR gate 232 to the "CK" input of the channel number register 122. The contents of the channel number register 122 are increased by "coefficient 1" only to the next channel. The contents of the storage device of the corresponding skip memory 132 are checked. This process continues until a "skip" signal occurs. In response to the " skip " signal, a " clock " input of address register 114 is supplied with a clock signal at inverter 234 and AND gate 236 to increase the contents of address register 114 by a factor of one. However, at this point, the content of channel number 122 does not increase further. Therefore, at this point, the contents of the channel number register 122 (this is logical " 0 ") are detected by the channel number display device 120 and the contents of the first position of the tuning voltage memory 112 are read. And change to the corresponding tuning voltage.

When the viewer wants to change the channel in the normal mode, he presses either the "UP" push button 216 or the "DOWN" push button 218. When the "up" push button 216 is pressed, a push button "up" status indication signal (PBUP) is generated. In response to the OR gate output (OUP) signal being generated by the OR gate 230, a "phase (U)" signal is applied to the previously generated "power up" signal or the push button "phase" status indication signal (PUP) signal. This "up" signal is generated by the reset-set flip-flop 220 if it does not occur in response. In response to the " phase (OP) " signal, the channel number register 122 and the address register 114 are brought into a steam type countable state. In addition, the contents of the channel number register 122 increase by a factor of 1 in response to the OR gate output (OUP) signal supplied to the "clock (CK)" input at the OR gate 238. Thereafter, the contents of the channel number register 122 are continuously increased in response to the " SKIP " signal which is generated continuously until the " SKIP " signal is generated. When the " skip " signal is generated, the contents of the address register 114 are increased by a factor of 1, but the contents of the channel number register 122 are not increased further. At this point, the second desired channel number is displayed to generate a corresponding tuning voltage. The operation of the tuning device 20 when the "DOWN" push button 218 is pressed to change the channel is similar to that of the tuning device 20 when the "UP" push button 216 is pressed. In this case, the channel number register 122 and the address register 114 perform a decrement coefficient rather than an increment expression.

The viewer presses and releases all push buttons 214 to place the tuning device 20 in channel program mode to assign the desired or undesired state to each channel. In response, the " MODE " signal is generated momentarily and then stopped.

The sequence detector 212 generates a " CHANNAL " signal in accordance with the operation sequence of the mode button room button 241. At this time, the channel selected prior to the operation of the mode push button 214 is alternately displayed with the symbol "CH" by the display device 120. If the viewer wants to assign the desired state to the channel, increase or decrease the contents of the channel number register 122 so that the "UP" pushbutton 216 or "DOWN" until the channel assigned to the desired state appears. Press any of the Nurum buttons 218 in succession. When the desired channel number is displayed by the display unit 120, the viewer responds to this occurrence and end of the MODE signal so that a "STORE" signal is generated by the sequence detector 212, resulting in the displayed channel number. A logic " 0 " is introduced at the storage position of the addressed skip memory 132, and the tuning device 20 is set again to the normal mode by the end of the channel signal. In the channel program mode, it is preferable that an undesired state recovers a pre-allocated channel, so the "SKIP" and skip (SKIP) signals are input to the "clock (CK)" input of the channel number register 122 and the address register 114. As a result, the channels that are skipped during channel selection in normal mode are prevented from being supplied by the " NORMAL " signal generated by sequence detector 212 except when the tuner is in normal mode during channel mode. In response to the presence of the NORMAL signal), the operation of the AND gates 231 and 236 is not skipped.

When a viewer wants to assign an unwanted state to a channel, select the channel to be assigned to the unwanted state in the usual manner as described above, and then press and release the mode pushbutton 214 to release the tuner 20 in the channel programming mode. Set to. At this time, the channel selected prior to the operation of the mode push button 214 is alternately displayed with the symbol "CH". Here the viewer presses and releases the mode push button 214 again. In response to the continuous generation and stop of the second mode signal, the sequence detector 212 generates an "ERASE" signal, and logic "1" is introduced into the storage location of the skip memory 132 addressed by the display channel number. do. In response to the generation of the " clear " signal, the sequence detector 212 generates a " NORMAL " signal and sets the tuning device 20 to the normal operating mode, so that the OR gate 230 is connected to the " clock " input of the channel number register 122. The OR gate output (OUP) signal is supplied to increase the contents of the channel number register 122 by one. At this point, as described above, the next desired channel is tuned in a conventional manner.

When a viewer wants to program or reprogram (i.e. fine tune) one of the desired channels, he or she may "up" the button 216 or "until the display 120 displays the desired channel number." By continuously pressing any of the " DOWN " push button 128, the channel to be programmed for tuning voltage is selected. The mode push button 214 is then pressed while pressing either the “UP” push button 216 or the “DOWN” push button 218. In response to the occurrence of either the push button "up" status display signal (PBUP) or the push button "bottom" status display signal (PBDN) in the presence of a "MODE" signal, the sequence detector 212 tunes the tuning device 20. Generate a "TUNE" signal to put into voltage programming or tuning mode. The tuning voltage does not end, and the tuning device 20 remains in the tuning voltage program mode until any of the push buttons 214,218 pressed before is released. The clock signal generated by clock 242 in response to the tuning signal and the push button "up" status display signal (PBUP) or the push button "bottom" status display signal (PBDN) (OR output of OR gate 240) is ANDed. It is supplied to the " clock " input of the tuning voltage register 118 via gate 244. This causes the contents of the tuning voltage register 118 and the tuning voltage to change. In addition, one decimal number corresponding to the tuning signal and displaying the tuning voltage is displayed alternately with the symbol "AJ" by the display device 120, whereby the viewer can adjust the tuning voltage by one decimal number and the manufacturer. By comparing the provided tuning voltage channels, it is possible to determine when the tuning voltage is almost correct. The viewer releases all the Nurum buttons 214, 216, and 218 that were previously enjoyed after confirming the satisfied state of the display screen. The sequence detector 212 is the end of the "MODE", the push button "up" status display signal (PBUP), the "press button" "low" status display signal (PBDN), the push button "down" status display signal (PBDN). An end is detected and a "STORE" signal is generated so that the contents of the tuning voltage register 118 are in the current addressed position of the tuning voltage memory 112, and the end of the tuning signal is detected to return the tuning device 20 to the normal mode. While the mode push button 212 is depressed, the tuning device 20 enters the tuning voltage program mode by operating either the "up" push button 216 or the "down" push button 218. Since it is necessary to release the three push buttons to terminate the signal, the viewer does not have to keep pressing the pressed mode push button 214 and at the same time the "up" push button 216 or the "down" push button 218 Continue to manipulate There is no need.

This is desirable because the viewer may unconsciously release the mode Nurum button 214 during tuning voltage adjustment. The tuning device 20 can be set to the tuning voltage program mode from either the normal mode (after the channel has been selected for normal mode) or the channel mode (after the channel has been assigned to the desired state as described above).

Therefore, the control of the tuning device 20 is performed by operation of only three push-button type switches. Here, the two push button switches are used for the operation of the regular channel selection mode, and the other push button switches are operated in a predetermined order together with the operation of the first two push button switches to start the channel and tuning voltage programming modes. And control is performed. In the configuration of the present invention, not only the minimum number of control elements are used, but also relatively inexpensive control elements, for example, a key of a calculator, in comparison with other types of control elements such as a rotary type or a switch having a large number of switching positions, which are generally used. It uses a control device of a Nurum button switch type that is used as a board. In addition, the control procedure is relatively simple for the viewer of the frostbite and is performed as follows.

Selection of the channel ... Either the "UP" push button 216 or the "DOWN" push button 218 is operated so that a desired channel can be obtained.

To add a channel: Press and release the mode pushbutton 214. Manipulate either the "UP" push button 216 or the "DOWN" button 218 to obtain the channel to be added. Pressing mode pushbutton 214 and removing the released channel ... operates either of the "UP" pushbutton 216 or the "DOWN" button 218 to obtain the channel to be removed. Press and hold mode push button 214 twice to release it.

Adjusting the tuning voltage ... Either the "up" push button 216 or the "pown" push button 218 is operated to obtain a channel to which the tuning voltage is to be adjusted. Hold the mode push button 214 and operate the "UP" push button 216 or the "DOWN" push button 218 until the display is satisfactory.

Moreover, after the control sequence of each programming is completed, the tuning device 20 automatically returns to the normal mode, so that the tuning is performed in a state that may confuse the average viewer without programming, mode indication (ie, "CH" or "AJ"). Device 20 does not stay inadvertently. In this connection, the above confusion may arise when a switch having a non-Instantaneous multiple switching position is used. The tuning voltage programming process when the mode push button 214 is held down while either the "UP" push button 216 or the "DOWN" push button 218 is operated is deactivated. It is somewhat similar to the type in which a conventional mechanical tuning device having a tart-shaped tuner with a rotary channel selector that is rotated in a state is operated.

출력에 논리 "0" 이 발생하는 셋트 상태와, 그 Q 출력에 논리 이 "0",

출력에 논리 "1"이 발생하는 리셋트 상태와에 서로 번갈아 절환된다. "채널(CHANNEL)" 신호는 트리거 플립플롭312의 Q 출력에 발생한다.데이타 플립플롭 316은 그 D 입력에 공급되는 신호가 논리 "1"인 경우에는그 CK 입력에 정방향 펄스가 공급되는 것에 응동하여 셋트되어, 그 D 입력에 공급되는 신호가 논리 "0"인 경우에는 CK 입력에 정방향 펄스가 공급되는 것에 응동하여 리셋트된다. "축적(STORE)" 신호는 OR게이트 330의 출력에 발생한다. "소거(ERASE)" 신호는 AND 게이트 324의 출력에 발생한다.Here, the execution of the logic of the sequence detector 212 shown in FIG. 2 is considered. Trigger Flip Flop 312 OR gate 314, data flip-flop 316, differential circuit composed of capacitor 318 and resistor 319, OR gate 320, AND gates 322 and 324, inverters 326 and 328, OR gate The first logic configuration, including 330, detects the operating sequence of the mode push button switch 214 UP push button 216 "POWN" push button switch 218 to initiate and continue to control the channel programming mode. It is used for. Trigger flip-flop 312 responds to the continuous application of a negative pulse supplied to its clock (CK) input, causing a logic " 1 "

Set state where logic "0" occurs at the output, and logic "0" at its Q output,

The output alternates between reset state and logic "1" occurring. The "CHANNEL" signal is generated at the Q output of the trigger flip-flop 312. The data flip-flop 316 responds to the forward pulse supplied to its CK input when the signal supplied to its D input is a logic "1". When the signal supplied to the D input is a logic " 0 ", it is reset in response to the forward pulse supplied to the CK input. A "STORE" signal occurs at the output of OR gate 330. An "ERASE" signal is generated at the output of AND gate 324.

Next, the circuit operation of FIG. 2 will be described. It is assumed that the trigger flip-flop 312 is reset because the generation of the forward reset pulse according to the OR gate 314 responds when the "TUNE" signal or the "PUP" signal is occurring. When the mode push button switch 214 is pressed and released, the trigger flip-flop 312 is set at the negative edge of the resulting "MODE" signal, and a "CHANNEL" signal is generated. The data flip-flop 316 is reset in response to the forward edge of the "CHA NNEL" signal supplied via the capacitor 318 to the R (reset) input of the data flip-flop 316.

Logic " 1 " is supplied to the D input of data flip-flop 316 as long as trigger flip-flop 312 is in the set state. Thus, assuming the mode push button switch 214 is released when either of the "UP" push button 216 or the "DOWN" push button 218 is pressed, the push button "up" status signal (PBUP) or push This D input is supplied with a logic "1" when the forward pulse generated by the OR gate 320 in response to any of the button "bottom" status indication signals PBDN sets the data flip-flop 316. If the mode push button switch 214 is not released when the "UP" push button switch 216 or the "DOWN" push button switch 218 is depressed, the "TUNE" signal is generated as described below. Trigger flip-flop 312 is reset. The negative direction of the second "MODE" signal when the mode push button is pressed again and released after the operation of either the "UP" push button switch 216 or the "DOWN" push button button 218 In response to the edge, trigger flip-flop 312 is reset, but data flip-flop 316 is not reset.

At this time, the Q output of the data flip-flop 316 becomes logic "1". Therefore, when the Q output of the data flip-flop 312 decreases in response to the second "MODE" signal, the negative edge of the "CHANNEL" signal is supplied to the inverter 326 through the capacitor 318 and inverted to the positive direction. The pulse is generated. In response to this forward pulse, the AND gate 322, activated by logic "1" at the Q output of the data flip-flop 316, generates a forward pulse, which is supplied as an "STOR" signal through the OR gate 330. do.

출력은 논리"1"로 된다. 따라서 만약 모드 누룸단추 214가 계속해서 두번 눌려지고 해제되면, 두번째의 "모드(MODE)" 신호에 응동하여 발생하는 "채널(CHANNEL)" 신호의 부방향 연부는 반전기328에 의해 반전되어 데이타 플립플롭 316의

출력에서 논리 "1"에 따라서 활성화된 AND 게이트 324는 "소거(ERASE) 신호"를 발생한다.Trigger flip-flop 312 does not reset as described above unless "up" pushbutton switch 216 or "down" pushbutton switch 218 is operated after mode pushbutton switch 214 is pressed and released. . However, data flip-flop 316 is not set due to the absence of a forward clock pulse at OR gate 320, and

The output is logical "1". Thus, if mode pushbutton 214 is repeatedly pressed and released twice, the negative edge of the "CHANNEL" signal generated in response to the second "MODE" signal is inverted by inverter 328 to flip the data. Flop 316

AND gate 324 activated according to logic " 1 " at the output generates an " ERASE signal ".

Data flip-flop 412, inverter 414, differential circuit formed by capacitor 416 and resistor 417 differential circuit formed by capacitor 424 and resistor 425, OR gate 426, AND gate 428, inverter 430, 432, 434, and separate OR gate 320 The second logic configuration of the sequence detector 212 includes the mode push button 214, the "UP" push button 216, and the "DOWN" push button 218 for starting and controlling the tuning voltage program mode of the tuning device 20. It is used to detect the operation method and the order.

The data flip-flop 412 is reset in response to a "power up" signal. If mode push button 214 is pressed, logic " 1 " is supplied to D input of deta flip-flop 412. While either mode UP button 214 is held depressed, either “UP” push button 216 or “DOWN” push button 218 is manipulated and a positive clock pulse causes OR gate 320 and 426 and capacitor 424 to It is supplied via a clock (CK) input of the data flip-flop 412 to set the data flip-flop 412 and generate a "TUNE" signal at its output. The rising edge of the " TUNE " signal is supplied to the R input of the trigger flip-flop 312 via the OR gate 314 to reset it as described above. If both the " UP " nurum button 216 and the " DOWN " nurum button 218 are released, a logic " 1 " is supplied to the two inputs of the AND gate 428 via inverters 432 and 434.

At this time, when the mode push button 214 is released, logic "0" is supplied to the D input of the data flip-flop 412, and logic "1" is supplied to the other input of the AND gate 428 via the inverter 430. In response, a forward pulse is supplied to the clock CK input of the data flip-flop 412 via the AND gate 428, the OR gate 426, and the capacitor 424. As a result, data flip-flop 412 is reset and the " TUNE signal " stops. In response to the negative edge of this TUNE " signal, a negative pulse is supplied to inverter 414 and inverted to produce a forward pulse. This forward pulse is “stored” via capacitor 416 and OR gate 330. When the initial mode pushbutton 214 is released and then both the "UP" pushbutton 216 and the "DOWN" pushbutton 218 are released, the "TUNE" signal is terminated. The "STORE" signal is generated.

Inverters 418,422 and AND gate 420 of sequence detector 212 are used to generate a " NORMAL " signal. Both trigger flip-flop 312 and data flip-flop 412 are reset so that logic " 1 " is supplied to inputs of AND gate 420 via inverters 418 and 422 to react with it to generate a " NORMAL " signal.

While the sequence detector 212 has been described as an executable of logic, the detection of the mode of operation and the sequence of the mode push button 214, the "up" push button 216, and the "down" push button 218 can be performed using a properly programmed subroutine ( It is also executed by a microprocessor with subroutines. It goes without saying that such forms and other variations are included in the scope of the invention.

Claims (1)

In a television receiver tuning device including a voltage variable tuning device 18 for tuning a receiver to various tuning positions that can be selected by a viewer, the tuning device corresponding to the tuning position for controlling the voltage variable tuning device 18 is provided. A tuning voltage device 118 for generating a binary signal indicating the tuning voltage; A first storage device (112) having a plurality of storage locations for accumulating binary signals generated by said tuning voltage device (118); Generating a first binary signal " 0 " and a second binary signal " 1 " representing each of the desired and undesired states of the tuning position and accumulating the generated binary signals; A skipping device (132, 134) having a plurality of storage locations for the same; A tuning position selection device (216, 218, 220) including at least a direction switch device (216; 218) for addressing a storage position of the skip device; In the device provided with the mode switch device 214, Input terminals are coupled to the directional switches 216 and 218 and the mode switch 214, and a first output terminal is coupled to the tuning voltage device 118 so that the first and second switches of the directional switches 216 and 218 and the mode switch 214 are connected. First logic gates 320, 426, 412 for generating a tuning voltage programming signal for enabling the operation of the tuning voltage device 118 in response to a series of operations, and input terminals of the direction switches 216, 218; And a second and third output terminals coupled to the input terminals of the skip device 132 and 134, the second and third output terminals of the direction switch 216 and 218 and the mode switch 214. A sequence detection device comprising second logic gates 320, 312, 316, 322, 326, 328, 324 and 330 for generating first and second tuning position programming signals to generate first and second types of binary signals from the skip devices 132 and 134 respectively in response to an operation. Scoop 212 Water appointed television tuning apparatus as.

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