JPS5957321A - Dma access control system - Google Patents

Abstract

PURPOSE:To attain efficient use of a DMA controller, by making an address output of the DMA controller accessible at both byte and word, in a computer system. CONSTITUTION:When a DMA request is given from an input/output device to a DMA controller 11 in a DMA cycle, a DMA response signal is returned to a request channel. The response signal is returned to a requesting input/output device and becomes an input to a byte/word information storage means 13. When the DMA channel is a word, an A input to an address selector 12 is suppressed, and a B input is selected. An address is advanced at each even number address at a DMA controller exclusive use of byte access and the word access is made possible. If the transfer is the byte transfer, an inverting signal of A0 signal of the DMA controller 11 becomes a BHE signal and signals A0-An are outputted as they are.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to l) an MA access control system, in particular a D
This relates to an MA access switching control method.

Traditionally, computer systems have DMA (D
direct Me”017ACQ8”B) An input/output device that is equipped with a controller and requires high-speed transfer, such as C
When transferring character data or image data from memory to an RT display device, printer, etc., the transfer is performed using MA control, which is much faster than program control using a CPU.

By the way, whether to access memory in units of words or units of bytes depends on, for example, 1
．． In a 6-bit CPU, each control signal is output from the CPU for easy access, whereas the D
Conventional MA controllers do not have a cusp that can arbitrarily control bytes/words, so addresses cannot be controlled in the same way.

In general, in a word-structured memory, the address control signal will differ depending on whether the memory is accessed in bytes or words, even if the address is the same. Further, in order to efficiently access a word-structured memory in units of words, it is desirable to access every even address by &1, and in the middle of a byte, even and odd addresses alternate.

In this way, in order to access a memory with a one-phase word structure in units of bytes/words, it is necessary to control the address control signals by the method of y4 and tr, respectively. [Therefore, it is said that it is difficult to maintain the same address control.

The purpose of the present invention is to solve such conventional problems,
The address output of the DMA controller can be accessed in both bytes and words, and the bit/word can be arbitrarily specified for each channel to control DMA control.
- It is an object of the present invention to provide a DMA access control method that can make efficient use of the RAM.

The DMA access control method of the present invention includes an information holding means of at least one bit or more corresponding to a DMA channel, and a selector for selecting either the m-th bit or the (m+1)-th bit of a DMA address. The selector is controlled according to the output of the information holding means corresponding to the DMA channel in the DMA, and the selector output is
It is characterized by being an address.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of main parts of a computer system using the present invention.

In FIG. 1, C11 is a DMA module according to the present invention, and in addition to the MA controller 11, a byte/word information holding means 13 and a data address selector 12 are newly provided. 2 is the CPU, 3.4 is the address buffer, 5 (1 memory module, 6 is the data
Bus 7 is an address bus.

Memory module 5 has DOND8 low) < -
f) 43 storage sections 51 and D8 to T') 15 high-byte storage sections 52 are provided.

First, the case where CPU 2 accesses memory 5 will be described.

CP r, y outputs the memory address to be accessed through address buffer 3, and further outputs the memory address to be accessed through address buffer 3.
Depending on whether it is read or written, a control signal M RDC or MWTC is output. At this time, when accessing the memory 5 in word units, CP
Address signal AO-“L” from U2, B I-T E
- "T, IT". Also, since the DMA (enable signal (DMA, EN) is °°L", the address buffer 3 is activated, and the DMA address buffer 4 is activated.
is not activated. Note that the control signals MRDC, MWTC
, l0RC, TOWC also has 7)-L, super buffer 3,
4, it is driven by a buffer with an enable gate, and the buffer is selected and used in the CPU cycle or DMA cycle.

Next, in the DMA cycle, the input/output device (Ilo
) issues a DMA request to the DMA controller 11, the DMA controller 11 returns a DMA response signal to the request channel as a permission signal. The DMA response signal is returned to the requesting input/output device and is input to the byte/word information holding means 13 through the bus 14. The byte/word information holding means holds in advance one piece of information specifying whether the DMA channel is a byte transfer or a word transfer, corresponding to each T)MAA channel, and if the DMA channel is a word transfer, the address selector 12 The input to is suppressed and the B input is output.

When the B input is output, the address signal of the address selector 12 becomes AO-"L", T3HE-■, ", and the address output signal of the DMA controller 11 becomes A1, A1 becomes A2, etc. ...An becomes An+1,
The address is output with the address shifted one bit at a time.

In word transfer, by selecting the B input of the address selector 12, the DM dedicated for byte access
In the A controller as well, the address is incremented at every even address (AO is always IT, "), allowing word access.

If it is a byte transfer, the inverted signal of the AO signal of the DMA controller 11 becomes the B)iE signal, and the AO
~An is output as is.

In this way, in the present invention, D
By controlling the address output from the MA controller 11 with the selector 12, byte access and word access can be freely used in a plurality of DMA channels.

The second diagram shows the configuration of a DMA module according to an embodiment of the present invention, and the third diagram is an explanatory diagram of a memory access operation according to the present invention.

FIG. 2 shows a case where four mutually independent DMA channels are controlled.

In the 1-bit information holding means 13 corresponding to DMA channels 1 to 4, data specifying whether each channel is accessed by byte or word is held in advance by the CPU 2. Now, Word
When the access is ``1'' and the byte access is O'', channels 1, 2.4 are designated as byte access and channel 3 is designated as 1 node access in the information holding means 13.

When a DMA 1th VF,'JJ request is issued from channel 1, a DMA response signal is activated for only that channel as a permission signal for this request. Only the output of the DMA response MA channel 1 is activated and the output is sent to the address selector 12. The S terminal of the address selector 12 becomes O'' (low level) and operates so that the A input is selected, so the address output of the DMA controller remains unchanged as the selector output (A,
OA, n). However, the inverted signal of AO is BH
It becomes E signal.

Note that the AO multiplication signal BFTE signal changes alternately as the address increments.
This is the r number for separating/removing the data, and the AO multiplied signal inversion signal is the BHE signal, so by incrementing the DMA address, even Toa ground (low byte) - odd number
+! + (Hypa・rl) −・Even address (low byte) →
jj'i of . That is, as shown in Figure 3,
A low byte storage section 51 and a high byte storage section of the memory 5,
52, addresses rt7 A1 to An are input in parallel, and address signals A are input as enable signals for the low byte storage section 5 and the high byte storage section 52, respectively.
O and BHE are used.

Next, a case where DMA channel 3 is activated will be described.

Due to the DMA response signal No. 9, the 1111 information holding means 13
Since the output becomes I II I+, the S terminal of the address selector 12 becomes "1" (high level), and the B input is selected. When the B input is selected, both the Ao multiplied signal B and the HE signal are always at the ``0'' level, and the DMA controller output output child address becomes an address sequentially shifted by 1 bit. That is, the address A
O becomes A1, address AI becomes A2, A (n
-1) becomes An.

Due to such a taII configuration, when the DMA controller output address is incremented, the memory address is incremented every even address. For example, DMA controller) o-rall
Gara' 00001 ”, ”00010”,
When the address signal incremented by 1 as 00011''' is output, the address selector 12 outputs o.
.

010", '00100', "00110"...
Since the memory address is converted to an address incremented by 2 and output, the memory address is incremented at every even address. Therefore, the memory 5 is sequentially accessed word by word. The shaded area shown in FIG. 3 indicates a word access unit.

As explained above, according to the present invention, the address output of the DNIA controller dedicated to byte access can be accessed in both byte and word.
The MA controller can be used effectively, and bytes/words can be arbitrarily specified for each channel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a computer system using the present invention, FIG. 2 is a block diagram of a DMA module showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of memory access operation according to the present invention. be. 1: DMA module, 2: CPU, 3, 4 near address buffer, 5: memory, 6: 7'-ta bus,
7: Address bus, l1: T) MA controller, 12 Near address selector, 13: Information holding means. 2nd Figure 11. 12 Figure 3

Claims (1)

[Claims] Controlled by the information holding means that specifies access in bytes or words for each DMA channel, and the output of the information holding means, m bit 11 of the DMA address and (
The DMA channel being executed is provided with a selector that selects one of the m+1) bits, and when the DMA channel being executed is in bait units, the memory is accessed using the selector output of the 4th m bit as an address, and when it is in word units, the memory is accessed using the (m+1) bits as the address.
1) A DMA access control method characterized in that the memory is accessed with an address incremented for every even number address using the selector output as the bit-th bit.