JPS6285343A - Memory reading-out circuit - Google Patents

Abstract

PURPOSE:To execute efficiently the processing by executing continuously read- out from a memory by the designated number of pieces. CONSTITUTION:By the number of continuous read-out data which are sent from a processor part, a data counter 11 is preset, the value of an address register in which a read-out head address is stored in advance is set as an initial value, an increment value which is set in advance is added by an adder 15, and a memory 16 is read out continuously by the designated number of pieces. According to such constitution, a data value 104 which is inputted from an external circuit is inputted to the counter 11, and the memory 16 is brought to read-out.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a memory readout circuit for an external large capacity data memory of a data flow processing processor. (Prior Art) Conventionally, large capacity data memories such as image data are When reading the data, the read address must be sent from the processor unit in 1-word units each time, which hinders speeding up memory access. One method is to place an address generator inside the memory and perform continuous reading or writing by providing only the activation timing.90 (Problem to be solved by the invention) According to this method, in the case of writing, there is no particular problem because the data value is destroyed by writing and does not flow to the subsequent processor, but in the case of reading, it is difficult to write a large amount of data at once. If the data is read out, the processing capacity of the subsequent processor section will be exceeded, causing a problem that, for example, the internal key memory of the processor section will overflow.

(Means for Solving the Problems) The circuit of the present invention uses a memory read data identification number of a data flow processing device in which a plurality of processor groups and memories are cascaded in a ring-shaped pipeline bus. an identification number memory that is referenced as an address value and from which a new b data identification number is read; a counter that presets the number of consecutive read data sent from the processor; and an address that stores the start address of the read data in advance. a register; an increment value register for storing an increment value of an address in advance; an adder for adding the increment value to the value of the address register after the counter is set in advance to generate all read addresses of the memory; Memo Ij
At the same time as the counter value t'''1'' is read out, the counter value t'''1'' is decremented. A specified number of data values are continuously read out by the processor and sent to the next processor group together with the data identification number.

(Function) The gist of the present invention is to maintain a sufficiently high reading speed of the memory, and at the same time, to control the reading speed from the memory according to the processing speed of the processor section, thereby efficiently preventing overflow. In order to realize a memory read circuit that can execute processing, a data counter is preset according to the number of consecutive read data sent from the processor section, and the value of the address register in which the read start address is stored is set as the initial value. The important point is to add the increment value using the adder and to read out the specified number of values continuously from the memory.

In other words, in the case of occurrence of attrition, the initial value B and the increment value B
The address value sequence generated from A, A+B, A+
2 B , ---, A+ (n-1) B, which is an arithmetic progression. Here, n corresponds to the specified number. The value of B is determined by how the data value is read. For example, if one data is stored in one word and it is read out sequentially, the value of B is "l".
Therefore, one data is stored in two words, and the first
If processing is performed first on the busy word and then on the second word, intermittent access is required, so the value of B is '2#'. In processing for a two-dimensional data array, if it is necessary to generate addresses in the X and Y directions, the value of B is "work" when scanning in the X direction, but when scanning in the Y direction, the data in the X direction is The number becomes the value of B.

It is assumed that the start address register and its increment value have been initialized in advance, and when the processor section is started to process from an external host processor, first,
The number of pieces required for reading is sent to the memory section. The number used at this time is determined by estimating the processing (1) in the processor section of the target processing and the predicted value for all memory accesses, and is selected so as to prevent overflow and at the same time to operate sufficiently efficiently. It is also possible to dynamically control the total flow rate by changing the number of data generated during processing. Such control allows efficient memory reading according to the processing content and eliminates memory necks and path necks.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 14 is a block diagram showing one embodiment of the present invention.

The readout circuit of FIG. The increment value initialized in the register 3 is added by the adder 15 and the memory 6 is read out.

Signal 102 is a system pipeline clock, and the operation of this circuit is performed in synchronization with this clock.

The signal 103 is a memory read request signal from the outside, and becomes "1" when the busy signal 114 is in the state of "0" and there is a memory read request from the outside.

The counter 1 uses the output signal 112 of the AND gate 10 as a clock, and the value of the signal -jt 104 is preset at the rising edge of the clock, and the value is decremented by 1 each time the clock signal 113 from the control section 14 is issued. When ft occurs, a zero detection signal 105'i is sent to the control section 14.

The memory 1 is set in the counter 11 and continues for the number of 9 pieces.
Address 110 to 6 is generated and read out.

The read start address value is initially set in the register 12. It is assumed that this initial setting is made in advance prior to a series of processes and is not changed during the process. The value of the signal 104 is taken into the register 12 in synchronization with the rise of the clock 106 from the control section 14. register 1
The output value 108 of 2 is added to the output value 109 of the register 13 by the adder 15, and a signal 110 is output. Subsequently, signal 110 is sent to register 1 in synchronization with clock 106.
2 and this operation is repeated until the zero detection signal 105 is issued.

A signal 104 is set in the register 13 in synchronization with the rising edge of the clock 107, and its output value becomes a signal 109.

The adder 15 adds the current address value 108 and the increment value 109 and outputs the address value 110 of the memory 16.

The memory 16 is accessed using the signal 110 as an address value, and is read when the read/write switching signal 115 is '0', and outputs a signal 111.

The control unit 14 uses a pipeline clock 102. Control signal 1
01 , Zero detection signal 105 t - Precise busy signal 1 to wait for a request from the previous stage circuit during read operation
Output 14 and decrement pulse 11 of counter 11
3. Latch clock 107 of register 13, register 1
2 latch clock 106 and read/write control signal 115 for memory 16 are output.

Data input/output to/from this embodiment from a processor group external to this embodiment has a data identification number in addition to the data value itself. This data identification number completely indicates to which processor in a group of multiple processors the data value is sent and what kind of processing is performed.A data identification number is assigned to each data value. It is being

The identification number memory 17 is referred to as the input identification number 116t-address value, and a new data identification number 117 is read. The identification number memory 17 has a control signal 118 of 1.
0'', the above reading is performed, and the pair is output to the next pipeline stage with the output data value 111 from the memory 16, indicating the destination of the data value 1110.The control signal 118 is @ Identification number 1 when 1''
16? The value of signal 104 is used as the address value in memory 17.
When written, it is initialized. This initial setting must be performed in advance prior to processing.

FIG. 2 is a detailed block diagram of the control section 14 in FIG. 1. The circuit shown in FIG. 2 is composed of a gate array section 21 and a register 22. The gate array section 21 performs logical operations on input signals 101, 105, 102 and 301, and outputs signals 113, 106, 107, 115, 1.
14 and 201 are generated. Signals 301 and 201 are signals indicating the internal state, and the register 22 generates a new internal state in synchronization with the clock signal 102.

FIG. 3 is an input/output logic table showing the internal operation of the gate array section 21 in FIG. 2. In Figure 3, the input signals are 102, 101, 105.301, and the output signal is 11.
3,106,107,115,114.201.

``0'', ``1'', ... ``4#'' in the table indicates the signal value of the corresponding column, and the blank column indicates the value of ``-0#'' or ``1'' for input. and is indeterminate in the case of output.

Among these signals, the signal 101 is a multilevel signal, and the others are binary signals.

The signal 102 is a pipeline clock signal, and the input to the register included in this circuit is latched in synchronization with the rising edge of the signal. Signal 105 is a zero detection signal and is the first
When the value of the counter 11 in the figure is '0', it becomes '1', and otherwise it is O'.

When the signal 101 is @0'', it does nothing, when it is ``1'', it decrements the value of the counter 11, when it is ``2#'', it sets the initial value of the register 121C, and when it is ``3H'', it increments the value in the register 13. Set the value, and if it is 4H, memory 1
6, the control signal 115 is set to '1#'.
shall be.

(Effects of the Invention) As described above, according to the present invention, it is possible to read data from the memory for the total specified number of pieces continuously, and to eliminate the pathneck at the same time.

The number of read data can be controlled according to the processing content, and the processing can be executed efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of the control section in FIG. 4, and FIG. 3 is the input/output logic relationship and state of the gate array section 21 in FIG. 2. It is a diagram showing transition. 10...AND gate, 11...Counter, 12°22...Register. Figure 1 Y-zushi]

Claims (1)

[Claims] In a memory reading circuit of a data flow processing device in which a plurality of processor groups and memories are cascaded via a ring-shaped pipeline bus, data identification numbers sent from the processors are used as address values. an identification number memory from which a new data identification number is read out; a counter that presets the number of consecutive read data sent from the processor; an address register that prestores the start address of the read data; an increment value register that stores an increment value in advance; an adder that adds the increment value to the value of the address register after the counter is preset to generate a read address of the memory; and an adder that generates a read address of the memory; At the same time, the value of the counter is set to “1”.
”, and a zero detector that determines whether or not the specified number of data values have been output. and read it out,
A memory read circuit characterized in that the data identification number is sent to the next processor group together with the data identification number.