JPH064398A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor with which a CPU can access memory blocks parallelly so as not to generate bus neck in the case of performing access from the CPU to the memory blocks at different access speed. CONSTITUTION:This information processor divides the memory access into access time and data transfer time. An address outputted from the CPU during the access time is latched by an address latch circuit 3 and decoded by an address decode circuit 4. A memory cell 5 reads/writes a select signal C from the address decode circuit 4 and data D corresponding to a control signal from a control circuit 6. An address back circuit 8 informs of which access performs data transfer, by returning an address B latched during the data transfer time to the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device for controlling a memory block by a CPU.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of an information processing apparatus. 1
Is a CPU, a is a bus line from CPU1, 2 is a CP
Memory blocks controlled by U1 having different access speeds. FIG. 4 is an internal block diagram of the conventional memory block 2 of FIG. 3 is an address latch circuit that latches the address output from the CPU and holds it until the bus cycle ends. 4 is an address decode circuit that decodes the latched address B and outputs a select signal c. 5 is a select signal c and a memory. A memory element which reads / writes data D according to a control signal of a control circuit 6 which controls the input / output of signals in the block 2, and 7 is a ready signal generation circuit which generates a ready signal E indicating the end of the bus cycle.

Next, the operation will be described. CPU in Figure 3
The address output from 1 is latched by the address latch circuit 3 of FIG.
It is decoded by and it is judged whether or not this memory element is selected by the CPU 1. When this memory element is selected, the address decode circuit 4 outputs a select signal C, the control circuit 6 outputs a control signal, and data 2 is read / written to / from the memory element. At this time, the ready signal generation circuit 6 sends a ready signal key to the CPU to end the bus cycle.
Output to 1.

[0004]

Since the conventional information processing apparatus is configured as described above, the CPU 1 accesses one memory block 2 and the memory element becomes readable / writable until the ready signal is returned. During this period, the other memory blocks and the CPU are stopped, and the CPU bus is also in an unused state. Further, there is a problem that a bus neck occurs when the CPU operates at a high speed with respect to the memory access speed.

The present invention solves the above problems and
An object of the present invention is to obtain an information processing apparatus that can access another memory block while accessing one memory block. It also aims to be able to operate in parallel for memory blocks with different access speeds.

[0006]

An information processing apparatus according to the present invention divides a bus cycle into an access period and a data transfer period, returns an address output from the CPU 1 during the access period to the CPU 1 during the data transfer period, and determines which memory By notifying whether it is a data transfer for the block,
This enables parallel operation such that another memory block is accessed during the access period and the data transfer period.

Further, instead of returning the above-mentioned address to the CPU, the memory block number programmed in advance in the CPU is output to the CPU during the data transfer period to inform which memory block the data transfer is to.

[0008]

In the information processing apparatus according to the present invention, the bus cycle is divided into the access period and the data transfer period, the address output from the CPU 1 is returned to the CPU 1 during the data transfer period, and which memory block the data transfer is to be performed. Since the information is notified, it is possible to access another memory block during the access period and the data transfer period, and it is possible to efficiently use the CPU 1, the memory block and the bus line. In addition, when the CPU is operated at high speed, it does not fall into a bus neck.

Further, instead of returning the above address to the CPU 1, the memory block number programmed in the CPU 1 in advance is output to the CPU 1 during the data transfer period to inform the memory block to which the data transfer is performed, so that the address line is not used. The memory block can be accessed even during the data transfer period.

[0010]

【Example】

Example 1. FIG. 1 shows an embodiment of the present invention, and a memory block 2 of an information processing apparatus as shown in FIG.
FIG. 3 is an address latch circuit that latches the address output from the CPU and holds it until the end of the bus cycle. 4 is an address decode circuit that decodes the latched address B and outputs a select signal c. A memory element that reads / writes data D by a control signal of a control circuit 6 that controls the input / output of data in the memory 2, and 8 is an address back that returns the latched address to the CPU during the data transfer period of the bus cycle. Circuit.

In the information processing apparatus configured as described above, the address output from the CPU 1 is latched by the address latch circuit 3 during the access period of the bus cycle, and the latched address B is decoded by the address decoding circuit 4, It is determined whether the memory block has been chosen by the CPU. When this memory block is selected, the address decode circuit 4 outputs a select signal C to the memory block 5 and the data 2 is read / written together with the control signal from the control circuit 6. During this data transfer period, the address back circuit 8 returns the latched address to the CPU 1 and informs the CPU 1 of which access the data transfer is to. During the period from the access period to the data transfer period, the CPU 1 can access other memory blocks.

Example 2. In FIG. 2, a block number output circuit 9 is provided instead of the address back circuit 8 of the first embodiment, and by outputting a memory block number programmed in advance to the CPU 1 during the data transfer period, the CPU 1 is notified of which access the data transfer is to. . By transferring this memory block number without using the address line, the CPU 1 can access it even during the data transfer period.

[0013]

As described above, according to the present invention, the bus cycle of the information processing device is divided into the access period and the data transfer period, and the address is returned from the memory block to the CPU during the data transfer period, so that the access period and the data transfer are performed. The CPU is allowed to access other memory blocks during the period. As a result, memory blocks having different access speeds can be operated in parallel, and a bus neck will not occur even when a CPU having a high memory access speed is used.

The memory block number is programmed in advance in the CPU, and the memory block number is transferred to the CPU during the data transfer period so that the address line is not used and the CPU also writes another memory block during the data transfer period. Can access.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory block showing a first embodiment of the present invention.

FIG. 2 is a block diagram of a memory block showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram of an information processing device.

FIG. 4 is a block diagram of a conventional memory block.

[Explanation of symbols]

 1 CPU 2 Memory Block 3 Address Latch Circuit 4 Address Decode Circuit 5 Memory Element 6 Control Circuit 7 Ready Generation Circuit 8 Address Back Circuit 9 Block Number Output Circuit

Claims (2)

[Claims] 1. A CPU, a plurality of memory blocks having different access speeds for accessing the CPU, an address latch circuit for holding an address from the CPU in each memory block until the end of a bus cycle, and an output of the address latch circuit. An address decoding circuit for decoding
A memory device for storing data output from the PU, and C
A control circuit that monitors the control signal output from the PU and the state of the bus and controls the input / output in the memory block, and the access to the memory block is divided into an access period and a data transfer period. An information processing device, comprising: an address back circuit that notifies which memory block is ready for data transfer during a data transfer period and returns the latched address to the CPU so that the block can be accessed. 2. A CP is a block number of a memory block programmed in advance in the CPU to inform the CPU which memory block is ready for data transfer.
An information processing apparatus comprising a block number output circuit for outputting to U.