JPS6059462A - Pipeline access memory of bi-directional data bus - Google Patents

Abstract

PURPOSE:To avoid the contention of a bi-directional data bus by producing a writing signal which is applied to a memory part according to the writing/reading requests, a signal which controls the holding method of data to be read out and a signal which gives the output timing. CONSTITUTION:A read/write address is supplied to a memory 20 through an address ling 50 and held by a latch 10. At the same time, the write data is held by a latch 11 from a bi-directional data bus 60 through a data line 61. The read data read out of the memory 20 is held by a latch 30 through a data line 52 and held by a latch 31 through a data line 53 to be delivered to the bus 60 in a read data output period. Then three signals (n) showing the presence of no read/ write request, (r) showing a read request and (w) showing a write request are supplied through a signal line 70. At the same time, a clock signal is supplied through a signal line 80. Thus it is possible to produce a signal which performs the control to prevent the contention of the data bus 60.

Description

[Detailed Description of the Invention] This invention utilizes bidirectional data and buses.
The present invention relates to a circuit that performs memory access using a bigline method in order to perform 7 accesses and to access the memory 7 times at K speed.

Conventionally, when memory access is performed using a pipeline method, data transfer conflicts occur when requests to write data to memory and requests to read data from memory are made randomly, so a manual port and an output port are prepared separately. There were seven methods such as

The purpose of the present invention is to provide 2.microglosses. It is an object of the present invention to provide a memory that can be applied to bidirectional data buses used in other applications, etc., and can be accessed at high speed near the maximum performance of a memory chip by applying a big-line method to memory access.

According to the present invention, a memory accessed using a bidirectional data bus includes means for manually holding write data and address data, a memory section for receiving and storing an output signal from the input holding means, and the memory. a means for holding and outputting data read from the memory section; a write signal to the memory section in response to a write/read request; a signal for controlling a method of holding the read data; and a means for providing output timing of the read data. A bidirectional data pipeline access memory is provided which includes means for generating a signal and which prevents bidirectional data bus contention from occurring in response to successive read/write requests.Next, the present invention will be described with reference to the drawings. I will explain. 1st
The figure is a block diagram showing an embodiment of the present invention. A read/write address to the memory 20 is manually inputted through the address line 50 and held in the latch 10, and write data is held in the latch IJ from the bidirectional data bus 60 through the data line 61. Data read from the memory 20 is held in the latch 30 through the data line 52, further held in the latch 31 through the data line 53, and then outputted to the bidirectional data bus 60 through the data line 63 when outputting read data.

Signals indicating the three states H, r, and W are inputted from the signal line 70, and a clock signal synchronized with the memory access cycle is inputted from the signal line 80. Here, n indicates that there is no read/write request, r indicates a read request,
W indicates a write request. FIG. 2 is a schematic diagram showing the contents of the ROM 40, in which three states i1. The state transition for fSW is shown.

The initial state is S, and when the signal n is input manually, it stays in the state S, when r is input manually, the state increases by 5rKi, and when the signal W is input manually, it moves to the state Sw. In addition, when n is input manually, when Bw is input, the read data is output to the bidirectional bus and the state goes to S, and when V input is input, the read data is output to the bidirectional bus.・When W is moved to state Sr and W is manually operated, it stays at Bw. The circuit state for each state is V(.When state S, launch 10.11,3
Data held at 0.31 has no meaning. Status S
The address of w's 11 memory 20 including key saving,
Data is held in latches 10.11. condition 8r
At this time, the address for reading from the memory 20 is held in the latch 10. In state B, data read from the memory 20 is held in the latch 31. Address for writing to memory 20 when in state BwO,
Data read from the memory 20 before the memory cycle is held in the latch 31. In state Br, the read address from the memory 20 is held in the latch 10, and the data read from the memory 20 before the memory cycle is held in the latch 31.

Finally! ! 4AWO time memory 2 era mori komi no ta 2
Data read before the memory cycle is held in the latch 31.

It, 0M40 is connected to the state of the signal line 70 by n, r, w, and the data of the latch 3 is transferred to the signal line 92 by the bidirectional bus 60.
A gate signal indicating whether or not to output the data is output to signal lines 78 and 79, and a signal is output to signal lines 78 and 79 to distinguish the holding method of data read from the memory 20, and seven signals are set in the latch 41 through the signal line 71.

The latch 31 determines whether there is data to be read from the memory.
Signal a78 indicates whether read data is held in
．． 79 holds data in the latch or sets data in the latch. The latch 30 also operates as a buffer that allows data on the signal line 52 to pass through to the signal line 78 as is. When the latch data is stored in the state Aw, it is used as a signal with a value of ``1''; otherwise, it is used as a signal with a value of 2 degrees, and is input to the subtracter 43 through the signal line 73.The last one is stored in the memory. When data is set in the latch 10.II, it is used to write the address into the memory 20 through the signal line 75, and when the read data is output to the bidirectional bus 60, the signal line 92 is used.
A signal indicating the output is output to tt-c. Two-way bus 6
When several memory access ports are connected to 0, each port holds the value of signal @92 when a memory access is requested, and when read data is output to the bidirectional bus 60, it is output through the signal line 91. The read data can be received correctly by monitoring whether the stored value matches the held value.

Although the state-transfer diagram in Fig. 2 was explained in terms of realizing it using the 0M40, PLA (for example, Signetic, <Company's
Ll! , ["P, LA 82S100) wo use i 117
tj can be easily realized.

By using the bi-line access memory of the bi-directional data bus of the present invention, it is possible to realize a memory board that can easily access and read the bi-directional bus of a general-purpose microflo bus and makes the best use of the performance of memory chips.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention.
FIG. 1 is a diagram showing the contents of the ROM 40. In the figure, 10, 11, 30, 31, 4] are latches,
20 is memory, 40 is RO decrease 42 I'i counter,
43 is a subtracter. Figure 2

Claims (1)

[Claims] A memory accessed using a bidirectional data bus, comprising means for manually holding input data and address data, a memory section for receiving and storing output signals from the manual holding means, and a memory section for receiving and storing output signals from the memory section. means for holding and outputting read data; a write signal to the memory section so as to prevent contention in response to a write/read request; a signal for controlling a method of holding the read data; and outputting read data. A bidirectional data bus pipeline, characterized in that the bidirectional data bus pipeline is characterized by comprising: a signal for providing timing;
access, memory.