JPS5956880U - Clock pulse generation circuit - Google Patents

Clock pulse generation circuit

Info

Publication number
JPS5956880U
JPS5956880U JP14839582U JP14839582U JPS5956880U JP S5956880 U JPS5956880 U JP S5956880U JP 14839582 U JP14839582 U JP 14839582U JP 14839582 U JP14839582 U JP 14839582U JP S5956880 U JPS5956880 U JP S5956880U
Authority
JP
Japan
Prior art keywords
shift register
signal
generation circuit
pulse generation
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14839582U
Other languages
Japanese (ja)
Inventor
大槻 光弘
田中 和佳
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP14839582U priority Critical patent/JPS5956880U/en
Publication of JPS5956880U publication Critical patent/JPS5956880U/en
Pending legal-status Critical Current

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  • Television Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はパケット伝送される文字信号が多重化されたテ
レビジョン信号を示す波形図、第2図は第1図に示す文
字信号の拡大図、第3図は本考案によるクロックパルス
発生回路の一実施例を示す回路図、第4図a、 bおよ
び第5図axdは第3図に示す回路の各部動作波形図で
ある。 1、・・・シフトレジスタ、2・・・基準発振回路、3
・・・N進カウンタ。5
FIG. 1 is a waveform diagram showing a television signal in which packet-transmitted character signals are multiplexed, FIG. 2 is an enlarged view of the character signal shown in FIG. 1, and FIG. 3 is a diagram of a clock pulse generation circuit according to the present invention. The circuit diagrams illustrating one embodiment, FIGS. 4a and 4b and FIG. 5 axd, are operational waveform diagrams of each part of the circuit shown in FIG. 3. 1. Shift register, 2. Reference oscillation circuit, 3.
...N-ary counter. 5

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パケット伝送により送られて来る情報の冒頭部に位置す
る走り込み基準信号をクロック入力として“1パ信号の
シフト動作を行なうとともに水平同期信号によってクリ
アされるシフトレジスタと、クロックパルスを発生する
基準発振回路と、前記シフトレジスタの出力信号によっ
てクリアが解除されて前記クロックパルスを計数するこ
とによりN分周されたサンプリングクロックを発生する
N進カウンタとを備え、前記シフトレジスタは走り込み
基準信号0不安亨期間を越えた時点1於パて出力を発生
する様にその段数が設定されていることを特徴とするク
ロックパルス発生回路。
A shift register that uses the run-in reference signal located at the beginning of the information sent by packet transmission as a clock input to perform a shift operation of the "1P signal" and is cleared by a horizontal synchronization signal, and a reference oscillation circuit that generates clock pulses. and an N-ary counter that is cleared by an output signal of the shift register and generates a sampling clock frequency-divided by N by counting the clock pulses, and the shift register is configured to operate during the running reference signal 0 instability period. 1. A clock pulse generation circuit characterized in that the number of stages is set so that an output is generated once the pulse exceeds 1.
JP14839582U 1982-09-30 1982-09-30 Clock pulse generation circuit Pending JPS5956880U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14839582U JPS5956880U (en) 1982-09-30 1982-09-30 Clock pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14839582U JPS5956880U (en) 1982-09-30 1982-09-30 Clock pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS5956880U true JPS5956880U (en) 1984-04-13

Family

ID=30329712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14839582U Pending JPS5956880U (en) 1982-09-30 1982-09-30 Clock pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS5956880U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532032A (en) * 1976-06-29 1978-01-10 Sony Corp Phase extraction circuit of burst signal
JPS597272A (en) * 1982-07-05 1984-01-14 Japan Electronic Control Syst Co Ltd Self-diagnosis starting system of self-diagnosing device of engine for motorcar

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532032A (en) * 1976-06-29 1978-01-10 Sony Corp Phase extraction circuit of burst signal
JPS597272A (en) * 1982-07-05 1984-01-14 Japan Electronic Control Syst Co Ltd Self-diagnosis starting system of self-diagnosing device of engine for motorcar

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