JPS60124170U

JPS60124170U - Video signal processing device

Info

Publication number: JPS60124170U
Application number: JP986384U
Authority: JP
Inventors: 笹村　晃平; 徳光　淳亮
Original assignee: 日本ビクター株式会社
Priority date: 1984-01-27
Filing date: 1984-01-27
Publication date: 1985-08-21
Also published as: JPH042541Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案装置の一実施例のブロック系統図、第２
図は本考案装置の要部の一実施例を示す回路系統図、第
３図及び第４図Ａ〜Ｆは夫々第２図図示回路系統の動作
説明用信号波形図である。１・・・再生複合映像信号入力端子、３・・・ＡＤ変換
器、４・・・パスラインコントローラ　５　、　　ｋタ
イミング制御回路、６・、・・制御信号入力端子、９・
・・メモリ、１０・・・アドレス信号発生回路、１１・
・・ＤＡ変換器、１４・・・ディジタルビデオ信号入力
端子、１５・・・水平同期パルス抽出回路、１６・・・
垂直同期　・パルス抽出回路、２０・・・カウンタ、２
１，２９・・・クロックパルス入力端子、２２・・・ゲ
ート回路、２５・・・シフトレジスタ、２６・・・スイ
ッチ。Figure 1 is a block system diagram of one embodiment of the device of the present invention;
The figure is a circuit system diagram showing one embodiment of the main part of the device of the present invention, and FIGS. 3 and 4 A to 4F are signal waveform diagrams for explaining the operation of the circuit system shown in FIG. 2, respectively. DESCRIPTION OF SYMBOLS 1... Reproduction composite video signal input terminal, 3... AD converter, 4... Pass line controller 5, k timing control circuit, 6... Control signal input terminal, 9...
...Memory, 10...Address signal generation circuit, 11.
...DA converter, 14...Digital video signal input terminal, 15...Horizontal synchronization pulse extraction circuit, 16...
Vertical synchronization ・Pulse extraction circuit, 20...Counter, 2
1, 29... Clock pulse input terminal, 22... Gate circuit, 25... Shift register, 26... Switch.

Claims

[Scope of utility model registration request]

When writing a composite video signal to a memory and reading it out, the composite video signal written to the memory is supplied when writing to the memory, and the composite video signal read from the memory is supplied when reading from the memory. A video signal processing device that generates a reference signal for an address signal based on a horizontal synchronization pulse and a vertical synchronization pulse in an input composite video signal, the video signal processing device comprising: a counter that counts clock pulses of a constant frequency; 1 at the time when the time equal to one horizontal scanning period minus the first set time has elapsed after the time when the counter is cleared based on the output count value.
Generating and outputting the first pulse of the horizontal scanning period, and the time after the clearing point, minus a second setting time equal to or greater than the first setting time from one horizontal scanning period. gate circuit means for generating and outputting a second pulse for a period from the elapsed time until the counter is cleared next time; and delay selection means for delaying the first pulse and outputting it immediately after input of the horizontal synchronizing pulse. Then, the counter is cleared approximately every horizontal scanning period based on the pulse obtained by gate-outputting the input horizontal synchronizing pulse only during the output period of the second pulse, and when the horizontal synchronizing pulse is missing, the counter is cleared. A video signal processing device comprising a logic circuit that clears the counter based on the output pulse of the selection means, and configured to generate and output the first or second pulse as the reference signal.