JPS594364A - Single line synchronism type receiver - Google Patents

Abstract

PURPOSE:To improve the reliability of a line, by catching a transition signal of a transmission signal line by two flip-flops, and separating the signal with logical conditions between the transition signal and a data sampling period signal for decreasing the fluctuation of a time constant. CONSTITUTION:In receiving a data signal TCD, a signal change is caught by flip-flops FFs 4, 5 and a pulse is generated to an EXO being an output of an exclusive OR gate EX. A shift register SR2 is started with this pulse and a data signal RXD is reset at the leading of an output signal QB. When a signal data is ''1'', the data signal RXD is ''1'', and when the signal data is ''0'', the RXD remains ''0''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single-wire synchronous receiving device used for single-wire synchronous communication in which both a synchronous waveform and a signal waveform are superimposed and transferred onto one signal line.

Generally, in single-wire synchronous communication systems, because it is necessary to distinguish between synchronous waveforms and signal waveforms, a system is adopted in which the frequencies of the two are changed and the signals are transmitted, and after reception, the signal waveforms are extracted by a filter circuit. And the transmitter has a superimposition circuit, and
A leap wave circuit is used in the receiving section, and both of these circuits are constructed from analog circuits using capacitors and resistors.

By the way, in the above-mentioned conventional device, the time constant required for superimposition or multiple waves is 4'14 in the analog circuit, so the reliability of the line is affected by fluctuations in the time constant due to changes in ambient temperature and variations in component constants. It has the disadvantage of decreasing.

Therefore, the present inventor has proposed a single-wire synchronous transmitter that solves the drawbacks of the conventional devices, and therefore, for convenience of explanation, this transmitter will be described first.

FIG. 1 shows the configuration of this transmitting device, and FIG. 2 shows its timing chart.

That is, in FIGS. 1 and 2, FFI to FFB are flip-flops, OR is an OR gate, V is an inverter gate, CLK is an external clock that determines the synchronous transfer speed,
It represents the RET beam set signal. In the 5RII'i shift register, the shift operation is performed only when the A and B inputs are 41#, and the output signals at Q, A - Q, and Ef are
, A to Q, and E.

Also, TKO, TXD ij Qi 11 M'j+
(7) It is assumed that the TJSART is connected to a communication control integrated circuit, and data is output from the TJSART to the data signal TXD at the falling edge of the data signal 'rxc. Note that TCD indicates signal output.

This transmitting device is configured as described above, and its operation will be explained next.

Now, when the transmitter generates a clock C1=i, the data signal TXC changes from 1 to 0 to 1 in synchronization with the rising edge of the output signals Q and A of the shift register 81. The output signal TCD becomes poor when the data signal TxC is 1' and the data signal F is 11' at the rising edge of the output signals Q and D of the shift register SRI, and the data signal method changes at l'. Points C and E indicate the start of the data l cycle, point B, where the data signal F changes at '1', indicates that the data is 51', and point D, where the data signal - does not change at 'hO'. As described above, according to this transmitter, a synchronization signal is periodically generated on the -wood signal line, and when the data is 1', the signal is in the middle of the synchronization signal. A single-wire synchronous transmitter can be constructed using only digital circuits, by weakening the signal at a point and changing the signal line when the data is 0#.

The present invention corresponds to the above-mentioned single-wire synchronous transmitter, and the wave circuit of the receiving section of the single-wire synchronous receiver that receives the output signal from the single-wire synchronous transmitter is a shift register,
The object of the present invention is to provide a device which is constructed of a digital circuit consisting of a block flop, and which significantly reduces fluctuations in time constant and improves line reliability.

An embodiment of the present invention will be described below with reference to the drawings.

That is, Fig. 3 shows the receiving section @, and Fig. 4 shows its timing chart.

In Figs. 3 and 4, FF4 to FF7 are flip-flops, EX is an exclusive or gate, ■v
indicates an inverter gate, OR indicates an OR gate, and NORFi Minoan gate 5CRz indicates a shift register. Furthermore, stages Ω and 'HXD are connected to a communication control integrated circuit such as USART with data signals similar to those of the transmitter shown in FIG.
7 in synchronization with the falling edge of the data signal Wω.
Assume that the AET reads the contents of the data signal stage (2) as data [7]. TCD indicates an output signal from the transmitter shown in FIG.

The embodiment of the present invention is constructed as described above, and its operation will now be explained.When the receiving device receives the data signal TCD, the flip-flop FF4 and block 5 change the signal. A pulse is generated in the book (■) which is the output of the exclusive or gate EX. This pulse causes shift register SR
2, and the rise of output signals Q and B (F in Fig. 4).
, H point), the data signal is reset, and if the signal data is 11', the output signals Q, B or Q, C are η'
During the period, the output of the exclusive OR gate EX becomes 11', and in synchronization with this, the data signal W becomes 1' at the 0 point in Fig. 4, but the signal data becomes 10'.
', the output TWO remains at 10' during the same period, so the data signal RXD remains at 10'.

As described above, according to the device of the present invention, the single-wire synchronous receiving device that extracts the data signal from the signal line in which the synchronizing signal from the transmitting device and the data signal are superimposed can be configured with only digital circuits, so that fluctuations in the time constant can be significantly reduced. It is hoped that it will be possible to provide a device that reduces the number of lines and improves line reliability.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of the transmitting device, Fig. 2 is a time chart of the device shown in Fig. 1, Fig. 8 is an embodiment of the device of this invention, and Fig. 4 is a time chart of the device shown in Fig. 3. be. In the figure, FFI-FF7 is a flip-flop, SRI
. It is an SR2&-1 shift register. Agent Makoto Kuzuno - L; g, g, intestine and Fρ Figure 4 F cr Silk L Mr. Commissioner of the Patent Office 1. Display of the incident Patent application No. 113551/1989 2
, Title of the invention Single-wire synchronous receiver 3, Person making the amendment (1) Application (2) Full text of the specification (3) Drawing 7 Contents of the amendment (1) Copy the application as shown in the attached sheet. (2) Print the entire specification as attached. (No change in content) (3) Print the drawing plan (Figures 1 to 3) as shown in the attached sheet. (No change in content)

Claims (1)

[Claims] A shift register is connected in series with first and second flip-flops that are set and reset at the output timing of the shift register to generate a data sampling period by applying a clock having an integral multiple of the reception frequency to the shift register. At the same time, a wire assembly synchronization signal obtained by superimposing the data signal and synchronization signal from the transmitting device is given.
and a fourth flip-flop, the third flip-flop and the fourth flip-flop.
A flip-flop causes a transition signal on the transmission signal line, and a data signal and a synchronization signal are separated from one transmission signal line according to the logic condition of the transition signal and the outputs of the first and second flip-flops. Single wire synchronous receiving device for identification.